計算機組成與結構：chapter10 Instruction Sets Characteristics and Functions

ComputerOrganization&ArchitectureChapter10

InstructionSets:CharacteristicsandFunctions10.1MachineinstructioncharacteristicsWhatisTheInstructionSetArchitectures?Theattributesofasystemasseenbytheprogrammer,i.e.,theconceptualstructureandfunctionalbehavior,asdistinctfromtheorganizationofthedataflowsandcontrols,thelogicdesign,andthephysicalimplementation.

-Amdahl,BlaawandBrooks,1964...theportionofthemachinevisibletotheprogrammerorcompilerwriter.

-HennesseyandPatterson,1990SoftwareHardwareISAInstructionSetThecollectionofinstructionsthatCPUcanexecuteTheinstructionsetdeterminatesthefunctionofCPUMachineCode,BinaryForconvenience,usuallyrepresentedbyassemblycodesElementsofanInstructionOperationcode(Opcode)DothisSourceOperandreferenceTothisResultOperandreferencePuttheanswerhereNextInstructionReferenceWhenyouhavedonethat,dothis...BranchinstructionPC

InstructionCycleStateDiagramWherearealltheOperands?Cache

or

mainmemoryorvirtualmemoryCPUregistersIfonlyoneregisterexists,referencetoitmaybeimplicitFormanyregisters,eachisassignedauniquenumberI/OdeviceTheinstructionmustspecifytheI/Omodule&deviceoranothermemoryaddressfortheoperationInstructionRepresentation

Inmachinecode,eachinstructionhasauniquebitsequenceTheinstructionisdividedintofieldssuchasthefollowingformat:Itisdifficultforboththeprogrammerandreaderstodealwithbinarycodeofmachineinstructions,thus,asymbolicrepresentationisusede.g.ADD,SUB,MPY,DIV

LOAD,STOR,etc.OperandscanalsoberepresentedinthiswayADDA,BInstructionTypesDataprocessingDatastorage(mainmemory)Datamovement(I/O)Programflowcontrol:testandbranchAnydata-processingtaskmaybeexpressedbyaboveinstructionsAnyprogramwritteninhigh-levellanguagemaybetranslatedintoaboveinstructionsNumberofAddresses3addressesOpcodeOperand1,Operand2,Result(Operand1)OP(Operand2)→Resulta=b+c;Maybeaforth-nextinstruction(usuallyimplicit)NotcommonNeedsverylongwordstoholdeverything2addressesOpcodeOperand1,Operand2(Operand1)OP(Operand2)→Operand1Oneaddressdoublesasoperandandresulta=a+bReduceslengthofinstructionSometimes,requiressomeextrawork:usingMOVinstructionTemporarystoragetoholdsomeresults1addressOpcodeOperand1OP(Operand1)→Operand1or(Operand1)OP(OperandX)→Operand1ImplicitsecondaddressUsuallyaregister(accumulator,AC)Commononearlymachines

E.g:ACACOPA0(zero)addressesOpcodeAlladdressesimplicitornoaddressUsesastack0addressesinstructionswouldreferencetoptwounitsofstackE.g.TTOP(T-1)NOPHowManyAddresses?MoreaddressesMorecomplex(powerful?)instructionsMoreregistersInter-registeroperationsarequickerFewerinstructionsperprogramFeweraddressesLesscomplex(powerful?)instructionsMoreinstructionsperprogramFasterfetch/executionofinstructions,buttheprogramislonger,morecomplicatedandslowerModerncomputersadopttwo-orthree-addressinstructionsInstructionSetDesignDecisionsOperationrepertoireHowmanyops?Whatcantheydo?Howcomplexarethey?DatatypesAddresses,Numbers,Characters,LogicalDataInstructionformatsLengthofopcodefieldNumberofaddresses

RegistersNumberofCPUregistersavailableWhichoperationscanbeperformedonwhichregisters?Addressingmodes(later…)RISCvCISC10.2TypesofOperandsAddressesUnsignedintegerNumbersInteger/floatingpoint/decimalUsingdecimalcanavoidconversionManymachinessupportpackeddecimal4bitsbinarycodeadecimaldigit246=001001000110CharactersASCII,EBCDIC,etc.LogicalDataBitsorflagsBoolean10.3PentiumandPowerPCdatatypePentiumDataTypes8bit(Byte)16bit(word)32bit(doubleword)generaldatatypes64bit(quadword)Addressingisby8bitunitA32bitdoublewordisreadataddressesdivisibleby4(32bitdatabus)Little-endian:theleastsignifcandisstoredinthelowestaddressSpecificDataTypesGeneral-arbitrarybinarycontentsInteger-signedbinaryvalue,complementrepresentationOrdinal-unsignedintegerUnpackedBCD-OnedigitperbytePackedBCD-2BCDdigitsperbyteNearPointer-32bitoffsetwithinsegmentBitfieldByteStringFloatingPointPentiumDataTypesPowerPCDataTypes8(byte),16(halfword),32(word)and64(doubleword)lengthdatatypesSomeinstructionsneedoperandalignedon32bitboundaryCanbebig-orlittle-endianFixedpointprocessorrecognises:Unsignedbyte,unsignedhalfword,signedhalfword,unsignedword,signedword,unsigneddoubleword,bytestring(<128bytes)FloatingpointIEEE754Singleordoubleprecision10.4TypesofOperationsDataTransferArithmeticLogicalConversionI/OSystemControlTransferofControlDataTransferDatatransferinstructionsarethemostfundamentaltypeofmachineinstructionSpecifySourceDestination:registers,memory,topofstackAmountofdataModeofaddressingDatatransferinstructionsMoveStoreLoadExchange:swapcontentsofsourceanddestinationClear:all0Set:all1Push/popArithmeticAdd,Subtract,Multiply,DivideSignedIntegerFloatingpointMayincludeIncrement(a++)Decrement(a--)Negate(-a)absoluteLogicalBitwiseoperations/BooleanoperationsAND,OR,NOT,Exclusive-ORTest,compareSetcontrolVariables:setcontrolsforprotectingpurpose,interrupthandling,timercontrol,etc.ShiftRotateshiftLogicalShiftArithmeticShiftCyclicShiftConversionTranslateSomevaluesinmemoryareconvertedbytablequeryASCIIEBCDICConvertBaseconversionE.g.BinarytoDecimalInput/OutputInput/readOutput/writeStartI/OTestI/OMaybespecificinstructionsMaybedoneusingdatamovementinstructions(memorymapped)Maybedonebyaseparatecontroller(DMA)SystemsControlPrivilegedinstructionsCPUneedstobeinspecificstateUpdatecontrolregisterForoperatingsystemsuseScheduleaprocessUpdatePCBTransferofControlBranch/jumpJumpconditionalJumptosubroutineReturnexecuteSkipSkipconditionalHaltWait(hold)NooperationProcedureCallInstructionAprocedureisaself-containedcomputerprogramthatisincorporatedintoalargerprogramCodereuseTaskdecomposingProcedureCallInstructionisajumpinstructionAcallinstructionAreturninstructionNestedProcedureReturnAddressForcorrectlyexecutingmainprogram’ssequence,thereturnaddressmustbeprotectedThreemainmethods:RegisterStartofprocedureTopofstackStack&ReturnAddressStack&ParameterspassingWithaprocedurecall,inadditiontoprovidingareturnaddress,passingorreturnedparametersisalsoneededHowtopassparameters?RegistersMemorystackStackFrame:asetofparametersincludingreturnaddress10.5PentiumIIOperationTypesPp.356~357–table10.8NoneedtorememberCall/ReturnInstructionsPIIprovides4instructionstosupportprocedurecall/returnCALL:pushPCintostack,PC=startaddressoftheprocedure(jump)ENTER:createastackframeLEAVE:clearastackframeRETURN:endofprocedureMemoryManagementInstructionsDealwithmemorysegmentationsPrivilegedinstructionsusedbyOSE.g.loadasegmenttablecheckoralteraprivilegeofasegmentConditionCodesBitsinspecialregistersSetbycertainoperationsandusedinconditionaljumpinstructionsPIICCsC:carryP:parity–1meansevenA:auxiliarycarry—carryofhalfbytesinALZ:0S:signO:overflowThesecodescanbecombinedtoformaconditionMMXTechniquesMMX—MultiMedia

eXtensionAsetofhighlyoptimizedinstructionsformultimediaapplications57SIMDinstructions,64-bitdatafieldPerformthesameoperationonmultipledataelementsatonceinasingleclockcycleForproperapplications,theseparalleloperationscanyieldaspeedupof2~8timesMMXRegisters864-bitregistersMMXDataTypes64-bitdatafield,3types:SIMDExecutionModelSIMDallowsthesameoperationtobecarriedoutonmultipledataelementsinparallel.TheMMXtechnologysupportsparalleloperationsonbyte,word,anddoubleworddataelementswhencontainedinMMXregisters.Wraparound&SaturationArithmeticWraparoundArithmeticWithordinaryunsignedarithmetic,whenanoperationoverflows,theextrabitistruncatedthatis,thecarryoroverflowbitisignoredandonlytheleastsignificantbitsoftheresultarereturnedtothedestinationcontroltherangeofoperandstopreventout-of-rangeresultsSaturationArithmeticIfadditionresultsoverfloworsubtractionresultsunderflow,theresultissettothelargestorsmallestvaluerepresentable0or255DataRangeLimitsforSaturationMMXInstructionsTheMMXinstructionsetconsistsof57instructions,groupedintothefollowingcategories:DatatransferArithmeticComparisonConversionUnpackingLogicalShiftEmptyMMXstateinstruction(EMMS)ExampleFade-outandfade-ininvideoapplicationAlgorithm:Result-pixel=Apixel

fade+Bpixel

(1-fade)=(Apixel-Bpixel)fade+Bpixel

MMXCodespxormm7,mm7;zerooutmm7movqmm3,fad_val;loadfadevaluereplicated4timesmovdmm0,imageA;load4redpixelcomponentsfromimageAmovdmm1,imageB;load4redpixelcomponentsfromimageBpunpcklbwmm0,mm7;unpack4pixelsto16bitspunpckblwmm1,mm7;unpack4pixelsto16bitspsubwmm0,mm1;subtractimageBfromimageApmulhwmm0,mm3;multiplythesubtractresultbyfadevaluespadddwmm0,mm1;addresulttoimageBpackuswbmm0,mm7;pack16-bitresultsbacktobytesSpecification8-bitpixelcomponentsareconvertedto16-bitelementstoaccommodatetheMMX16-bitmultiplycapabilityIfimages’resolutionis640*480,andthedissolveusesall255possiblefadevaluesthen,totalnumberofinstructionsinMMXis535million,withoutMMX,is1.4billionNotesAssemblelanguageisneeded50cyclestimeisneededfromMMXtofloatingpointinstructionsDoyourbesttoavoidshuffleusageofMMXandFPinstructionsSSESSE—StreamSIMDExtensionsMMX28new128-bitXMMregistersSSEregistersUsedforPentiumIIIprocessorfamilyEnhancetheperformanceofIA-32processorsforadvanced2-Dand3-Dgraphics,motionvideo,imageprocessing,speechrecognition,audiosynthesis,telephony,andvideoconferencingSSEInstructionsTheSSEinstructionsaredividedintofourfunctionalgroupsPackedandscalarsingle-precisionfloating-pointinstructions.64-bitSIMDintegerin