基于VHDL的八路彩燈控制器

..目錄1.任務(wù)需求22.總體設(shè)計22.1各個花樣的狀態(tài)圖22.2總體框圖43.模塊設(shè)計43.1分頻器模塊43.2花樣一模塊53.3花樣二模塊63.4花樣三模塊83.5頂層設(shè)計104.仿真圖114.1分頻器仿真波形114.2花樣一仿真波形114.3花樣二仿真波形124.4花樣三仿真波形134.5總體仿真波形135.心得體會146.參考文獻(xiàn)151.任務(wù)需求現(xiàn)今生活中,市場上未能吸取顧客的注意,高出各式各樣的方法,其中彩燈的裝飾便是其中非常普遍的一種。使用彩燈即可起裝飾宣傳作用,又可以現(xiàn)場氣氛,城市也因為眾多的彩燈而變得燦爛輝煌。VHDL語言作為可編程邏輯器件的標(biāo)準(zhǔn)語言描述能力強(qiáng),覆蓋面廣,抽象能力強(qiáng),在實際應(yīng)用中越來越廣泛。在這個階段,人們開始追求貫徹整個系統(tǒng)設(shè)計的自動化,可以從繁重的設(shè)計工作中徹底解脫出來,把精力集中在創(chuàng)造性的方案與概念構(gòu)思上,從而可以提高設(shè)計效率,縮短產(chǎn)品的研制周期。整個過程通過EDA工具自動完成,大大減輕了設(shè)計人員的工作強(qiáng)度,提高了設(shè)計質(zhì)量,減少了出錯的機(jī)會。要求設(shè)計一個8路彩燈控制器,要求彩燈可以演示以下花型：從兩邊向中間亮,再從中間向兩邊亮；實現(xiàn)淡入淡出效果從左至右逐個亮,在從右到左逐個亮；2.總體設(shè)計2.1各個花樣的狀態(tài)圖當(dāng)選擇花樣一時狀態(tài)圖如下：S0="ZZZZZZZZ" S1="10000001" S2="01000010" S3="00100100"S4="00011000" S5="00100100" S6="01000010"S0S0S1CLRS1S2S6S2S6S3S5S3S5S4S4當(dāng)選擇花樣二時狀態(tài)圖如下：S0="ZZZZZZZZ" S1="00000000" S2="10000000" S3="11000000"S4="11100000" S5="11110000" S6="11111000" S7="11111100"S8="11111110"S9="11111111"S10="01111111"S11="00111111"S12="00011111"S13="00001111"S14="00000111" S15="00000011"S16="00000001"SS0s1CLRs1S16S2S16S2S4S4S15S15S5S5s14s14s6s6s13s13S7S7s12s12S8s11S8s11S9s10S9s10當(dāng)選擇花樣三時狀態(tài)圖如下：S0="ZZZZZZZZ" S1="10000000" S2="01000000" S3="00100000"S4="00010000" S5="00001000" S6="00000100" S7="00000010"S8="00000001" S9="00000010" S10="00000100" S11="00001000"S12="0001000" S13="00100000" S14="01000000"SS0s1CLRs1S2S2s14s14S3s13S3s13S4s12S4s12s11S5s11S5s10s6s10s6S7S9S7S9S8S82.2總體框圖分分頻器CLK狀態(tài)狀態(tài)機(jī)LED顯示選擇器選擇器XUAN3.模塊設(shè)計3.1分頻器模塊--由于機(jī)器時鐘周期太短,不能滿足要求--此模塊實現(xiàn)分頻,得到需要的時鐘LIBRARYIEEE;USEIEEE.std_logic_1164.ALL;USEIEEE.std_logic_unsigned.ALL;ENTITYfenpinqiISPORT<CLK:INSTD_LOGIC;--原機(jī)器時鐘CLR:INSTD_LOGIC;CLK1:OUTSTD_LOGIC>;--分頻后的時鐘ENDfenpinqi;ARCHITECTUREARTOFfenpinqiISSIGNALCK:STD_LOGIC;BEGINPROCESS<CLK,CLR>ISVARIABLETEMP:STD_LOGIC_VECTOR<2DOWNTO0>;BEGINIFCLR='1'THENCK<='0';TEMP:="000";ELSIF<CLK'EVENTANDCLK='1'>THENIFTEMP="111"THENTEMP:="000";CK<=NOTCK;ELSETEMP:=TEMP+'1';ENDIF;ENDIF;ENDPROCESS;CLK1<=CK;ENDART;3.2花樣一模塊--用分頻器分頻后的時鐘來顯示花樣實現(xiàn)--從兩邊向中間亮,再從中間向兩邊亮；LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYhy1ISPORT<CLK1:INSTD_LOGIC;CLR:INSTD_LOGIC; XUAN:INSTD_LOGIC_VECTOR<1DOWNTO0>;LED1:OUTSTD_LOGIC_VECTOR<7DOWNTO0>>;ENDENTITYhy1;ARCHITECTUREARTOFhy1ISTYPESTATEIS<S0,S1,S2,S3,S4,S5,S6>;--設(shè)計狀態(tài)機(jī),實現(xiàn)花樣轉(zhuǎn)換SIGNALCURRENT_STATE:STATE;SIGNALLIGHT:STD_LOGIC_VECTOR<7DOWNTO0>;BEGINPROCESS<CLR,CLK1,XUAN>IS--定義花樣<1為燈亮,0為燈滅>CONSTANTL1:STD_LOGIC_VECTOR<7DOWNTO0>:="10000001";CONSTANTL2:STD_LOGIC_VECTOR<7DOWNTO0>:="01000010";CONSTANTL3:STD_LOGIC_VECTOR<7DOWNTO0>:="00100100";CONSTANTL4:STD_LOGIC_VECTOR<7DOWNTO0>:="00011000";CONSTANTL5:STD_LOGIC_VECTOR<7DOWNTO0>:="00100100";CONSTANTL6:STD_LOGIC_VECTOR<7DOWNTO0>:="01000010";BEGIN IFXUAN="01"THEN IFCLR='1'THEN CURRENT_STATE<=S0; ELSIF<CLK1'EVENTANDCLK1='1'>THEN CASECURRENT_STATEIS--狀態(tài)機(jī)轉(zhuǎn)換 WHENS0=>LIGHT<="ZZZZZZZZ";CURRENT_STATE<=S1; WHENS1=>LIGHT<=L1;CURRENT_STATE<=S2; WHENS2=>LIGHT<=L2;CURRENT_STATE<=S3; WHENS3=>LIGHT<=L3;CURRENT_STATE<=S4; WHENS4=>LIGHT<=L4;CURRENT_STATE<=S5; WHENS5=>LIGHT<=L5;CURRENT_STATE<=S6; WHENS6=>LIGHT<=L6;CURRENT_STATE<=S1; ENDCASE; ENDIF; ENDIF;ENDPROCESS;LED1<=LIGHT;ENDART;3.3花樣二模塊--用分頻器分頻后的時鐘來顯示花樣實現(xiàn)--實現(xiàn)淡入淡出效果LIBRARYIEEE;L;ENTITYhy2ISPORT<CLK1:INSTD_LOGIC;CLR:INSTD_LOGIC; XUAN:INSTD_LOGIC_VECTOR<1DOWNTO0>;LED2:OUTSTD_LOGIC_VECTOR<7DOWNTO0>>;ENDENTITYhy2;ARCHITECTUREARTOFhy2IS--設(shè)計狀態(tài)機(jī),實現(xiàn)花樣轉(zhuǎn)換TYPESTATEIS<S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16>;SIGNALCURRENT_STATE:STATE;SIGNALLIGHT:STD_LOGIC_VECTOR<7DOWNTO0>;BEGINPROCESS<CLR,CLK1,XUAN>IS--定義花樣<1為燈亮,0為燈滅>CONSTANTL1:STD_LOGIC_VECTOR<7DOWNTO0>:="00000000";CONSTANTL2:STD_LOGIC_VECTOR<7DOWNTO0>:="10000000";CONSTANTL3:STD_LOGIC_VECTOR<7DOWNTO0>:="11000000";CONSTANTL4:STD_LOGIC_VECTOR<7DOWNTO0>:="11100000";CONSTANTL5:STD_LOGIC_VECTOR<7DOWNTO0>:="11110000";CONSTANTL6:STD_LOGIC_VECTOR<7DOWNTO0>:="11111000";CONSTANTL7:STD_LOGIC_VECTOR<7DOWNTO0>:="11111100";CONSTANTL8:STD_LOGIC_VECTOR<7DOWNTO0>:="11111110";CONSTANTL9:STD_LOGIC_VECTOR<7DOWNTO0>:="11111111";CONSTANTL10:STD_LOGIC_VECTOR<7DOWNTO0>:="01111111";CONSTANTL11:STD_LOGIC_VECTOR<7DOWNTO0>:="00111111";CONSTANTL12:STD_LOGIC_VECTOR<7DOWNTO0>:="00011111";CONSTANTL13:STD_LOGIC_VECTOR<7DOWNTO0>:="00001111";CONSTANTL14:STD_LOGIC_VECTOR<7DOWNTO0>:="00000111";CONSTANTL15:STD_LOGIC_VECTOR<7DOWNTO0>:="00000011";CONSTANTL16:STD_LOGIC_VECTOR<7DOWNTO0>:="00000001";BEGIN IFXUAN="10"THEN IFCLR='1'THEN CURRENT_STATE<=S0; ELSIF<CLK1'EVENTANDCLK1='1'>THEN CASECURRENT_STATEIS--狀態(tài)機(jī)轉(zhuǎn)換 WHENS0=>LIGHT<="ZZZZZZZZ";CURRENT_STATE<=S1; WHENS1=>LIGHT<=L1;CURRENT_STATE<=S2; WHENS2=>LIGHT<=L2;CURRENT_STATE<=S3; WHENS3=>LIGHT<=L3;CURRENT_STATE<=S4; WHENS4=>LIGHT<=L4;CURRENT_STATE<=S5; WHENS5=>LIGHT<=L5;CURRENT_STATE<=S6; WHENS6=>LIGHT<=L6;CURRENT_STATE<=S7; WHENS7=>LIGHT<=L7;CURRENT_STATE<=S8; WHENS8=>LIGHT<=L8;CURRENT_STATE<=S9; WHENS9=>LIGHT<=L9;CURRENT_STATE<=S10; WHENS10=>LIGHT<=L10;CURRENT_STATE<=S11; WHENS11=>LIGHT<=L11;CURRENT_STATE<=S12; WHENS12=>LIGHT<=L12;CURRENT_STATE<=S13; WHENS13=>LIGHT<=L13;CURRENT_STATE<=S14; WHENS14=>LIGHT<=L14;CURRENT_STATE<=S15; WHENS15=>LIGHT<=L15;CURRENT_STATE<=S16; WHENS16=>LIGHT<=L16;CURRENT_STATE<=S1; ENDCASE; ENDIF; ENDIF;ENDPROCESS;LED2<=LIGHT;ENDART;3.4花樣三模塊--用分頻器分頻后的時鐘來顯示花樣實現(xiàn)--從左至右逐個亮,在從右到左逐個亮LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYhy3ISPORT<CLK1:INSTD_LOGIC;CLR:INSTD_LOGIC; XUAN:INSTD_LOGIC_VECTOR<1DOWNTO0>;LED3:OUTSTD_LOGIC_VECTOR<7DOWNTO0>>;ENDENTITYhy3;ARCHITECTUREARTOFhy3IS--設(shè)計狀態(tài)機(jī),實現(xiàn)花樣轉(zhuǎn)換TYPESTATEIS<S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14>;SIGNALCURRENT_STATE:STATE;SIGNALLIGHT:STD_LOGIC_VECTOR<7DOWNTO0>;BEGINPROCESS<CLR,CLK1,XUAN>IS--定義花樣<1為燈亮,0為燈滅>CONSTANTL1:STD_LOGIC_VECTOR<7DOWNTO0>:="10000000";CONSTANTL2:STD_LOGIC_VECTOR<7DOWNTO0>:="01000000";CONSTANTL3:STD_LOGIC_VECTOR<7DOWNTO0>:="00100000";CONSTANTL4:STD_LOGIC_VECTOR<7DOWNTO0>:="00010000";CONSTANTL5:STD_LOGIC_VECTOR<7DOWNTO0>:="00001000";CONSTANTL6:STD_LOGIC_VECTOR<7DOWNTO0>:="00000100";CONSTANTL7:STD_LOGIC_VECTOR<7DOWNTO0>:="00000010";CONSTANTL8:STD_LOGIC_VECTOR<7DOWNTO0>:="00000001";CONSTANTL9:STD_LOGIC_VECTOR<7DOWNTO0>:="00000010";CONSTANTL10:STD_LOGIC_VECTOR<7DOWNTO0>:="00000100";CONSTANTL11:STD_LOGIC_VECTOR<7DOWNTO0>:="00001000";CONSTANTL12:STD_LOGIC_VECTOR<7DOWNTO0>:="00010000";CONSTANTL13:STD_LOGIC_VECTOR<7DOWNTO0>:="00100000";CONSTANTL14:STD_LOGIC_VECTOR<7DOWNTO0>:="01000000";BEGIN IFXUAN="11"THEN IFCLR='1'THEN CURRENT_STATE<=S0; ELSIF<CLK1'EVENTANDCLK1='1'>THEN CASECURRENT_STATEIS--狀態(tài)機(jī)轉(zhuǎn)換 WHENS0=>LIGHT<="ZZZZZZZZ";CURRENT_STATE<=S1; WHENS1=>LIGHT<=L1;CURRENT_STATE<=S2; WHENS2=>LIGHT<=L2;CURRENT_STATE<=S3; WHENS3=>LIGHT<=L3;CURRENT_STATE<=S4; WHENS4=>LIGHT<=L4;CURRENT_STATE<=S5; WHENS5=>LIGHT<=L5;CURRENT_STATE<=S6; WHENS6=>LIGHT<=L6;CURRENT_STATE<=S7; WHENS7=>LIGHT<=L7;CURRENT_STATE<=S8; WHENS8=>LIGHT<=L8;CURRENT_STATE<=S9; WHENS9=>LIGHT<=L9;CURRENT_STATE<=S10; WHENS10=>LIGHT<=L10;CURRENT_STATE<=S11; WHENS11=>LIGHT<=L11;CURRENT_STATE<=S12; WHENS12=>LIGHT<=L12;CURRENT_STATE<=S13; WHENS13=>LIGHT<=L13;CURRENT_STATE<=S14; WHENS14=>LIGHT<=L14;CURRENT_STATE<=S1; ENDCASE; ENDIF; ENDIF;ENDPROCESS;LED3<=LIGHT;ENDART;3.5頂層設(shè)計--將以上幾個模塊整合起來,實現(xiàn)八路彩燈的花樣控制LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcaidengISPORT<CLK:INSTD_LOGIC;CLR:INSTD_LOGIC; XUAN:INSTD_LOGIC_VECTOR<1DOWNTO0>;LED:OUTSTD_LOGIC_VECTOR<7DOWNTO0>>;ENDENTITYcaideng;ARCHITECTUREARTOFcaidengISCOMPONENTfenpinqi--對分頻器模塊進(jìn)行定義PORT<CLK:INSTD_LOGIC;CLR:INSTD_LOGIC;CLK1:OUTSTD_LOGIC>;ENDCOMPONENTfenpinqi;COMPONENThy1--對花樣一模塊進(jìn)行定義PORT<CLK1:INSTD_LOGIC;CLR:INSTD_LOGIC; XUAN:INSTD_LOGIC_VECTOR<1DOWNTO0>;LED1:OUTSTD_LOGIC_VECTOR<7DOWNTO0>>;ENDCOMPONENThy1;COMPONENThy2--對花樣二模塊進(jìn)行定義PORT<CLK1:INSTD_LOGIC;CLR:INSTD_LOGIC; XUAN:INSTD_LOGIC_VECTOR<1DOWNTO0>;LED2:OUTSTD_LOGIC_VECTOR<7DOWNTO0>>;ENDCOMPONENThy2;COMPONENThy3--對花樣三模塊進(jìn)行定義PORT<CLK1:INSTD_LOGIC;CLR:INSTD_LOGIC; XUAN:INSTD_LOGIC_VECTOR<1DOWNTO0>;LED3:OUTSTD_LOGIC_VECTOR<7DOWNTO0>>;ENDCOMPONENThy3;SIGNALS:STD_LOGIC;--定義中間變量SIGNALL1:STD_LOGIC_VECTOR<7DOWNTO0>;SIGNALL2:STD_LOGIC_VECTOR<7DOWNTO0>;SIGNALL3:STD_LOGIC_VECTOR<7DOWNTO0>;BEGINU1:fenpinqiPORTMAP<CLK,CLR,S>;--對分頻器模塊進(jìn)行例化 U2:hy1PORTMAP<S,CLR,XUAN,L1>;--對花樣一模塊進(jìn)行定義 U3:hy2PORTMAP<S,CLR,XUAN,L2>;--對花樣二模塊進(jìn)行例化 U4:hy3PORTMAP<S,CLR,XUAN,L3>;--對花樣三模塊進(jìn)行例化 LED<=L1WHENXUAN="01"ELSE--讓LED顯示選定的花樣 L2WHENXUAN="10"ELSE L3;ENDART;4.仿真圖4.1分頻器仿真波形CLK為輸入,是機(jī)器時鐘。上升沿有效CLR為輸入,是異步復(fù)位端,當(dāng)為高電平時有效,CLK1保持狀態(tài)CLK1為輸出,是分頻后得到的我們需要的時鐘,周期是原時鐘的十六倍4.2花樣一仿真波形CLK1為輸入,是分頻后得到的時鐘CLR為輸入,是異步復(fù)位端,當(dāng)為高電平時有效X