89c51單片機(jī)外文翻譯

89c51單機(jī)翻

GeneralofChapter1ofareinacommercialsuchasmotor-controlairconditionerautomotiveengineandandperipheralthesemakethemsuitableforHowever,theseapplicationalsothatarereliable.ThehighlowbeaprocessandaproperenvironmentforthemicrocontrollersandatEngineeringdevelopedenvironmentforAT89C51automotiveThegoalsofthisenvironmentwastoprovideaenvironmenttheautomotivemicrocontrollers,toenvironmentbefortheseveralotherfutureTheenvironmentwasdevelopedconjunctionwithMicrosoft(AT89C51).describestheandofitswithenvironmentalandAT89C51.1.1TheAT89C51arehandlecalculationsandfastMCSareusedforapplicationsincludemotor-controlaircontrolTheautomotiveMCSinengine-controlsystems(ABS).AT89C51issuitedtoapplicationsandenhancedon-chipperipheralfunctionsset,suchasautomotivesuspension,braking,stabilitythesecriticalthe

acontrolleralowinterruptlatencytoservicetimeperipheralsneededrealtimeCPUwithaverageasinglepackage.Thefinancialriskhavingthatunpredictablyhigh.Onceparticularlyinmissionapplicationssuchasanoranti-lockbrakingsystem,Redesigncostsrunashigha$500K,muchmoreifthefixannotatingitacrossaproductfamilythatperipheraldesignflaw.Inaddition,asdevicesaresealedinwithavalueseveralthatofToitessentialofatthecomponentsystemworstcaseandThisandnotonlyaprocessbutproperenvironmentandtoolstofacilitateexecutesuccessfully.ChandlerPlatformpostsilicon(SV)ofvariousThesystemvalidationintoTheofdeviceitsapplicationrequirementsdeterminetypesoftestingare1.2AT89C51standardfeatures:4KbytesofFlash,32I/Olines,atwo-levelfulldupleport,oscillatorclockIntheAT89C51iswithstaticdownzerosupportstwosoftwareselectablesavingmodes.TheModestopsCPUwhilethetimer/counters,serialportinterruptfunctioning.ModesavesRAMoscillatordisablingall

pinscanasinputs0alsobeconfiguredtobethemultiplexedlowaddress/databusaccessestoexternaldatamemory.Inthishasinternalpullups.Port0alsoreceivesbytesFlashoutputsthecodebytesduringverification.pullupsarerequiredduringprogramPort：Port1isI/OportwithinternalPortfourTTL1swrittenPortbyinternalusedasinputs.Asinputs,Port1pinsthatareexternallypulledwillsourcecurrent(IIL)becausePortreceiveslow-orderaddressbytesprogrammingandverification.Port：2I/OportwithinternalThePortfourTTL1swrittenPortbyinternalusedasinputs.Asinputs,Port2thatareexternallypulledsource(IIL)becausepullups.PortemitsbyteduringfetchesexternalmemoryduringaccessestoPortpinsareexternallybeingpulledlowwillsourcecurrent(IIL)becauseinternalPort2thehigh-orderbyteduringfetchesprogrammemoryduringaccessestothat16-bitaddressesInapplication,itusesstronginternalwhenemittingaccessesexternalmemoryaddresses(MOVXRI),PortthetheP2SpecialFunctionPortalsoreceivestheandcontrolsignalsduringprogrammingPortPortisan8-bitI/OwithinternalThePortfourTTL1swrittenPortbyinternalusedasinputs.Asinputs,Port3thatexternallybeingpulledsource(IIL)becausepullups.PortofspecialsofttheasRSTResetinput.Ahighonthisfortwocyclestheoscillatorrunning

ALE/PROGAddressLatchoutputpulseforlowaddressaccessestoexternalmemory.isthepulseinput(PROG)duringInnormaloperationALEemittedaconstant1/6oscillatorfrequency,andbeusedtimingorclockinghowever,ALEduringaccesstoexternalDataIfdesired,ALEoperationdisabledbysettingbit0ofSFRlocationWithbitactiveduringaMOVXorMOVCinstruction.Otherwise,ishigh.theALE-disablehasifinPSEN：ProgramStoreEnablestrobeprogramWhenisexternalprogramtwiceeachmachinethattwoPSENactivationseachtoexternaldatamemory.EA/VPPExternalEnable.mustbetoordertodevicefetchexternalprogramlocationsat0000HuptoFFFFH.however,thatifbit1isEAwillbeinternallylatchedreset.EAtoexecutions.Thispinalltheprogramming12-voltXTAL1：InputoscillatorandtotheclockoperatingXTAL2:Outputinvertingamplifier.CharacteristicsXTAL1XTAL2theinputandoutput,aninvertingwhichforuseasanon-chipFigure1.Eitherquartscrystalormaybeused.drivethedeviceanexternalclocksource,XTAL2XTAL1asshowninFigure2.Therearerequirementsonthecycleofthesignal,sincetheinputinternalclockingcircuitryisthroughabutminimummaximumvoltagelowtimespecificationsmustIdleInidleCPUputssleepwhilealltheonperipheralsmodeisinvokedTheon-chipRAMandallspecialregistersremainduringidlemodecanterminatedanyenabledorbyreset.It

benotedthatwhenidleisterminatedbyathedevicenormallyprogramexecution,whereituptomachinecyclesinternalresetalgorithmtakesOn-chipaccesstointernalRAMinthisbutportisnotTopossibilityunexpectedwriteaIdleterminatedbyinstructiontheinvokesIdlebewritesaortomemory.ModeInpower-downmode,oscillatorisinvokesislastTheon-chipRAMRegistersretainuntilthemodeterminated.Theexitpower-downisahardwarereset.ResetSFRbutdoestheon-chipRAM.notitsnormalmustbeenoughtoallowoscillatorAT89C51codememoryarrayprogrammedbyteinprogrammingmode.anynonblanktheon-chipFlashentirememorymustbeerasedusingtheEraseProgrammingthethedatacontrolbesetFlashprogrammingmodeFigure4.ToprogramtheAT89C51,takesteps.1.InputdesiredonInputthe3.correctofsignals.EA/VPP12Vthehigh-voltagemode.ALE/PROGaarrayortheistypically1.5ms.Repeatsteps1throughtheandfortheentirearrayorendofisreached.DataPolling:TheAT89C51Pollingtheofwriteawritecycle,anreadthelastbytewrittenwillinofdatumPO.7.Oncethewritecyclebeentruevalidonallmayafterawritecycle

2.1Ready/Busy:TheprogrammingcanalsobyRDY/BSYoutputhighprogrammingtoindicateBUSY.P3.4ishighagainwhenprogrammingistoindicateProgramVerify:IflockLB2thecodereadbackviadataforverification.Thecannotdirectly.Verificationthebitsisfeaturesare2-1-1

2-2-2Verifying2.2Erase:ThearrayiserasedelectricallybythecombinationofcontrolsignalsandbyALE/PROGlow10ms.codearrayiswrittenall“1Thechiperaseoperationmuthememorycan2.3ReadingtheSignatureBytes:Thesignaturereadsameprocedurenormalverificationoflocations030H,031H,032H,musttoalow.Thevaluesreturnedareas:(030H)=1EHindicatesby(031H)=51Hindicates89C51(032H)=FFHindicates12Vprogramming(032H)=05Hindicates5V2.4ProgrammingInterface

codeinarrayandarraycanbeerasedtheofTheoperationisselftimedandoncewillautomaticallycompletion.Amicrocomputerinterfaceinformationbetweentwoforms.Outsidemicrocomputertheansystemasaphysicalitisnumerically.Theofanyinterfacecanamodifythedatainsomeprocessofbetweenexternalcarriedoutinanumbersteps.Anistovariablesignaltoacorrespondingcantakeoneanumberpossiblebinaryvalues.Iftheoftransducerdoesvarycontinuously,ADCisnecessary.Incasetheconditioningsectiontheincomingaformnextpartofthetheinput/outputsectionmicrocomputerinterfacesasimilarobviousbeingflowinformationistheoppositedirection;itthetheoutsideIncasethecallansupervisestheoperationandnumbersmayneededforconverter.Thissubroutineinformationturnproducesacorrespondingelectricalsignal,couldconvertedintoaisaformsuitablean.microcomputeraresmalltoctlytotheoutsideworld”andsomekindofinterfacemustbeusedtotomoreform.TheofsectionisoftheimportantfacingwishingtoapplyWeseeninmicrocomputersinformationisrepresenteddiscretethisdigitalformmicrocomputerwhichswitchedorwherebitrepresentthestateofaorTosolvereal-worldamorethanCPU,aadatamemory.InmustcontainCPUtoinformationoutsideworld.OncetheCPUgathersinformationthedata,itmustalsobeableto

portionoftheoutsidecalledtheCPU’swindowtheoutside.Themostmicrocontrollersgeneralport.EachofI/Opinscanbeusedaseitherinputoutput.TheofeachdeterminedorcorrespondingacorrespondingdirectionthestageofaEachpinaoralogicCPUinstructionsmayviewedCPUinstructions.ontoallowtheCPUtobit-seriallywithexternalbitformatinsteadbit-parallelI/Operformcommunicationfunction,whichitSerialareperformedeithersynchronouslyorasynchronously.AT89C51的概況1AT89C51應(yīng)單片機(jī)泛應(yīng)用于商：諸如制解調(diào)器，動(dòng)機(jī)控系統(tǒng)，空調(diào)制系統(tǒng)，汽發(fā)動(dòng)機(jī)和其一些領(lǐng)。這些單片的高速理速度和增型外圍備集合得它們適合這種高事件應(yīng)用場(chǎng)。然而這些關(guān)鍵應(yīng)領(lǐng)域也求這些片機(jī)高度可。健壯測(cè)試環(huán)境和于驗(yàn)證些無論在元件層次是系統(tǒng)別的單片機(jī)合適的具環(huán)境保證高可靠和低市場(chǎng)風(fēng)。Intel平臺(tái)工部門開發(fā)了種面向象的用于驗(yàn)它的AT89C51汽車單片機(jī)多性測(cè)試環(huán)。這種環(huán)境目標(biāo)不是為AT89C51汽車單片提供種健壯試環(huán)境，而開發(fā)一種能容易擴(kuò)并重復(fù)用來證其他種將來的單機(jī)。開的這種境連接了AT89C51本文討論了這種試環(huán)境設(shè)計(jì)和原理它的和種硬件軟件環(huán)境部的交互，以及如何用AT89C51

1.1介8位T89C51CHMOS工藝單片被設(shè)計(jì)用于理高速算和快速輸輸出。MCS51單片機(jī)典的應(yīng)用是高事件控系統(tǒng)商業(yè)應(yīng)包括調(diào)制解器，電機(jī)控制系統(tǒng)打印機(jī)影印機(jī)，空控制系，磁盤驅(qū)動(dòng)和醫(yī)療備車工把M單片機(jī)用發(fā)動(dòng)機(jī)制系懸掛系和反鎖動(dòng)系。AT89C51尤其很好用于得于它的處理度和增型片上外圍能集，如：汽動(dòng)力控制，輛動(dòng)態(tài)掛，反鎖制和穩(wěn)定控制應(yīng)用。于這些定性應(yīng)，市場(chǎng)需要種可靠具有低干擾伏響應(yīng)費(fèi)用效能控制，服務(wù)大量時(shí)和事件驅(qū)動(dòng)在實(shí)時(shí)用需要的集外圍的力，具有在一程序中高出均處理功率中央處器。擁有操不可預(yù)的設(shè)備的經(jīng)和法律險(xiǎn)是很的。一旦進(jìn)市場(chǎng)，其任務(wù)決定應(yīng)用諸自動(dòng)駕駛儀反鎖制系統(tǒng)，錯(cuò)誤是財(cái)力所禁止的。新設(shè)計(jì)費(fèi)用可以高500K美元，果產(chǎn)品族享同樣內(nèi)核或圍設(shè)計(jì)陷的話，費(fèi)會(huì)更高另外，部件替代品域是極昂貴的，因設(shè)備要來把模塊典地焊接一個(gè)總體的值比各部件高倍。為了緩這些問，在最壞的境和電條件下對(duì)這單片機(jī)行無論部件級(jí)別還系統(tǒng)級(jí)上的綜合測(cè)是必需。IntelChandler平臺(tái)工程組供了各種單機(jī)和處器的系統(tǒng)驗(yàn)。這種統(tǒng)的驗(yàn)證處可以被解為三主要部分。統(tǒng)的類和應(yīng)用需求定了能在設(shè)備上執(zhí)的測(cè)試型。1.2供下準(zhǔn)能4k字節(jié)FLASH閃速存器，字節(jié)內(nèi)部R，32個(gè)/O口線2個(gè)16位定/數(shù)器，一個(gè)5向量兩級(jí)斷結(jié)構(gòu)，個(gè)全雙串行通信口片內(nèi)振蕩器及鐘電路。同，AT89C51降至Hz的靜態(tài)邏輯操作，支持兩可選的節(jié)工作模式。閑方式制的工作，允許RAM，定時(shí)計(jì)數(shù)，串行通口及中斷系繼續(xù)工。電方保存RAM中內(nèi)容，振蕩器體制工作并止其他所有見工作到下一個(gè)硬復(fù)位。

圖1-2-1AT89C51方框圖1.3腳能明電源電地口：口是一組位漏極開型雙向/O口，即地址數(shù)據(jù)總線復(fù)用。作輸出口用時(shí)每位能收電流的方驅(qū)動(dòng)個(gè)TL邏輯門電路對(duì)端口寫“可作為高抗輸入用。在訪問部數(shù)據(jù)儲(chǔ)器或程序儲(chǔ)器時(shí)這組口線時(shí)轉(zhuǎn)換地址低8位）和數(shù)總線復(fù)，在訪問期激活內(nèi)上拉電阻。在lash編程時(shí)，P0口接受指令節(jié)，而程序驗(yàn)時(shí)，出指令字節(jié)校驗(yàn)時(shí)要求外接上電阻。

口：P1是一個(gè)帶內(nèi)上拉電的位雙向I/O口P1的出緩沖可驅(qū)動(dòng)吸收或輸出流）個(gè)TL邏輯門電路對(duì)端口寫“，通過內(nèi)的上拉電把端口拉到電平，時(shí)可作輸入。作為入口使用時(shí)因?yàn)閮?nèi)存在上電阻，某個(gè)腳被外信號(hào)拉低時(shí)輸出一電流（IIL）。編程和程校驗(yàn)期間，P1接受低位地址口：P2是一個(gè)帶有部上拉阻的8位雙向I/O口P2的輸出緩級(jí)可驅(qū)（吸收或輸電流）個(gè)TL邏輯門電路對(duì)端口“”，過內(nèi)部的上拉阻把端口拉高電平此時(shí)可作輸口。作輸入口使用，因?yàn)椴看嬖诶娮?，某引腳被部信號(hào)拉低會(huì)輸出個(gè)電流（IIL）。在訪問外部程存儲(chǔ)器或16位四肢的部數(shù)據(jù)儲(chǔ)器（例如行MOVX@DPTR令）時(shí)，口送出8位地址據(jù)，在問8位地址的外部據(jù)存儲(chǔ)（例執(zhí)行MOVX@RI指令）時(shí)P2口線上的內(nèi)（也即特殊能寄存（SFR）區(qū)中R寄存器的容），整個(gè)訪問期不改變編程和程序校時(shí)，P2也接收高位地址和他控制號(hào)?？冢篜3是一個(gè)帶有部上拉阻的8位雙向I/O口P3的輸出緩級(jí)可驅(qū)（吸收或輸電流）個(gè)邏輯門電路對(duì)端口“”，通內(nèi)部的上拉阻把端口拉高電平此時(shí)可作輸口。作輸入口使用，因?yàn)椴看嬖诶娮?，某引腳被部信號(hào)拉低會(huì)輸出個(gè)電流IIL）。P3口還接收一用于Flash閃速存器編程程序校驗(yàn)的制信號(hào)復(fù)位輸。當(dāng)振器工作時(shí)，引腳出現(xiàn)兩個(gè)器周期上高電平將單片機(jī)復(fù)位·ALE/PROG當(dāng)訪問部程序存儲(chǔ)或數(shù)據(jù)儲(chǔ)器，ALE地址鎖允許）輸脈沖用于鎖地址的位字。即使訪問外部存器，仍以時(shí)鐘振頻率的1/6輸出固定正脈沖信號(hào)因此它可對(duì)外出時(shí)鐘用于定時(shí)目的要注意是每當(dāng)訪外部數(shù)據(jù)存器時(shí)將過一LE脈沖。對(duì)存儲(chǔ)器程期間，該腳還用輸入編程脈（PROG。如必要，通過特殊功寄存器（SFR）中的8單元D位置，可禁ALE操作。位置位后只有一條MOVX和OVC指令A(yù)LE才會(huì)被活。此外，引腳會(huì)微弱拉，單片機(jī)執(zhí)外部程時(shí)，應(yīng)設(shè)置ALE無。程序存允許輸出是部程序儲(chǔ)器的讀選型號(hào)，89C51由外部存器取指令（數(shù)據(jù)），每個(gè)機(jī)器期兩次PSEN有效，即出兩個(gè)脈沖。此期間，當(dāng)問外部據(jù)存儲(chǔ)器，兩次有的PSEN信號(hào)不出。：外訪問允。欲使CPU僅訪問外部程存儲(chǔ)器地址為0000H），EA端必須保持低電平接地）需注意的是如果加密位B1被編程復(fù)位時(shí)部會(huì)鎖存EA端狀態(tài)如EA端為高電（接Vcc

端），則執(zhí)行內(nèi)程序存儲(chǔ)器的指令Flash存儲(chǔ)器編時(shí)，該腳加上+12v的編允許電Vpp，當(dāng)這必須該器使用12v編程電壓V?！TAL1：振蕩器相放大及內(nèi)時(shí)鐘發(fā)器的輸入端XTAL2振蕩器相放大器的出端。中有一個(gè)于構(gòu)成內(nèi)部蕩器的增益反相放器引腳XTAL1和XTAL2分是該放器的輸入端輸出端。個(gè)放大器與為反饋件的片外石晶體或瓷諧振器一構(gòu)成自振蕩器振蕩電路參圖5。接石英體或陶瓷諧器及電C2接在大器的饋回路中構(gòu)并聯(lián)振電路。對(duì)電C、雖沒有十分嚴(yán)格的求，但電容量的大小會(huì)微影響蕩頻率的高、振蕩工作的穩(wěn)定、起振難易程及溫度穩(wěn)定，如果用石英晶體我們推電容使用Pf，而如使陶瓷諧振器議選擇。戶也可采用外部時(shí)。這種況下，部時(shí)鐘脈沖到XTAL1端，即內(nèi)部時(shí)發(fā)生器輸入端XTAL2則懸空。·掉電式：在掉電式下，振蕩停止工，進(jìn)入掉電式的指是最后一條執(zhí)行的指令，片內(nèi)RAM和特殊功能存器的容在止掉電式前被凍結(jié)推出掉電模式唯一方法是件復(fù)位復(fù)位后將重定義全特殊功能寄器但不變R中的內(nèi)，在Vcc恢復(fù)到正工作電平前復(fù)位應(yīng)效，且必須持一定時(shí)以使振蕩器啟動(dòng)并定工作。89C51的程序存儲(chǔ)陣列是用字節(jié)寫入方編程的，每寫入一字符，要對(duì)個(gè)芯片EPROM程序存儲(chǔ)器寫入一個(gè)空字節(jié)，必使用片除的方法將個(gè)存儲(chǔ)的內(nèi)容清楚2編程法編程前設(shè)置好地?cái)?shù)據(jù)及制信號(hào)編程單元地址加在1口和P2口的2.0—P2.3（11位地范圍為0000H—0FFFH），數(shù)據(jù)P0口輸，引腳P2.6、P2.7和PP3.7的電平設(shè)置表6，PSEB為低電平，RST持高電平，EA/Vpp引腳編程電源的入端，要求加上編電壓，ALE/PROG引腳輸入程脈（負(fù)脈）編程時(shí)可采用4的時(shí)振蕩89C51編程方如下：在地線上加要編程單元地址信在數(shù)據(jù)線上上要寫的數(shù)據(jù)節(jié)。激活相的控制號(hào)。在高電編程方時(shí)，將EA/Vpp端加上+12v編程電壓。每Flash存儲(chǔ)陣列寫入一個(gè)節(jié)或每入一程序加位，加上一ALE/PROG編程脈沖改變編程單的地址寫入的數(shù)據(jù)重復(fù)—步驟，道全部文件程結(jié)束每個(gè)字節(jié)寫周期是身定時(shí)的，常約為1.5ms數(shù)據(jù)查詢9C51單片機(jī)數(shù)據(jù)查方式來檢測(cè)個(gè)寫周是否結(jié)束，在一個(gè)周期中，如要讀取