FPGA可編程邏輯器件芯片EP1S10B672C6中文規(guī)格書

fFormoreinformationaboutprogrammingserialconfigurationdevicesandfastAS

ConfigurationTiming,refertotheSerialConfigurationDevices(EPCS1,EPCS4,

EPCS16,EPCS64,andEPCS128)DataSheetintheConfigurationHandbook.

PassiveSerialConfiguration

YoucanprogramPSconfigurationofStratixIIIdevicesusinganintelligenthost,such

asaMAXIIdeviceormicroprocessorwithflashmemory,oradownloadcable.Inthe

PSscheme,anexternalhost(aMAXIIdevice,embeddedprocessor,orhostPC)

controlsconfiguration.ConfigurationdataisclockedintothetargetStratixIIIdevice

byusingtheDATA0pinateachrisingedgeofDCLK.

1TheStratixIIIdecompressionanddesignsecurityfeaturesarefullyavailablewhen

configuringyourStratixIIIdeviceusingPSmode.

Table11–9liststheMSELpinsettingswhenusingthePSconfigurationscheme.

Table11–9.StratixIIIMSELPinSettingsforPSConfigurationScheme

ConfigurationScheme

MSEL2

MSEL1

MSEL0

PS

0

1

0

PSConfigurationUsingaMAXIIDeviceasanExternalHost

Inthisconfigurationscheme,youcanuseaMAXIIdeviceasanintelligenthostthat

controlsthetransferofconfigurationdatafromastoragedevice,suchasflash

memory,tothetargetStratixIIIdevice.Youcanstoreconfigurationdatain.rbf,.hex,

or.ttfformat.Figure11–13showstheconfigurationinterfaceconnectionsbetweena

StratixIIIdeviceandaMAXIIdeviceforsingledeviceconfiguration.

Figure11–13.SingleDevicePSConfigurationUsinganExternalHost

Memory

VCCPGM(1)VCCPGM

(1)

ADDR

DATA0

StratixIIIDevice

10kΩ10kΩ

CONF_DONE

nSTATUS

ExternalHost

(MAXIIDeviceor

Microprocessor)

nCE

nCEO

N.C.

GND

VCCPGM

DATA0

MSEL2

MSEL1

MSEL0

nCONFIG

DCLK

GND

NotetoFigure11–13:

(1)ConnecttheresistortoasupplythatprovidesanacceptableinputsignalfortheStratixIIIdevice.V

highenoughtomeettheVspecificationoftheI/Oontheexternalhost.Itisrecommendedtopowerupall

mustbe

CCPGM

IH

configurationsystems’I/OwithV

.

CCPGM

StratixIIIDeviceHandbook,Volume1

Chapter11:ConfiguringStratixIIIDevices

PassiveSerialConfiguration

Whenthedeviceisinusermode,youcaninitiateareconfigurationbytransitioning

thenCONFIGpinlow-to-high.ThenCONFIGpinmustbelowforatleast2μs.When

nCONFIGispulledlow,thedevicealsopullsnSTATUSandCONF_DONElowandall

I/Opinsaretri-stated.WhennCONFIGreturnstoalogichighlevelandnSTATUSis

releasedbythedevice,reconfigurationbegins.

Figure11–14showshowtoconfiguremultipledevicesusingaMAXIIdevice.This

circuitissimilartothePSconfigurationcircuitforasingledevice,exceptStratixIII

devicesarecascadedformulti-deviceconfiguration.

Figure11–14.Multi-DevicePSConfigurationUsinganExternalHost

Memory

VCCPGM(1)VCCPGM

(1)

ADDR

DATA0

StratixIIIDevice1

StratixIIIDevice2

10kΩ

10kΩ

CONF_DONE

nSTATUS

CONF_DONE

nCEO

N.C.

nSTATUS

nCE

nCEO

ExternalHost

(MAXIIDeviceor

Microprocessor)

nCE

VCCPGM

VCCPGM

GND

MSEL2

MSEL1

MSEL0

MSEL2

MSEL1

MSEL0

DATA0

DATA0

nCONFIG

DCLK

nCONFIG

DCLK

GND

GND

NotetoFigure11–14:

(1)ConnecttheresistortoasupplythatprovidesanacceptableinputsignalforallStratixIIIdevicesonthechain.V

meettheVspecificationoftheI/Oontheexternalhost.Itisrecommendedtopowerupallconfigurationsystems’I/OwithV

mustbehighenoughto

.

CCPGM

IH

CCPGM

Inmulti-devicePSconfiguration,thefirstdevice’snCEpinisconnectedtoGNDwhile

itsnCEOpinisconnectedtonCEofthenextdeviceinthechain.Thelastdevice’snCE

inputcomesfromthepreviousdevice,whileitsnCEOpinisleftfloating.Afterthefirst

devicecompletesconfigurationinamulti-deviceconfigurationchain,itsnCEOpin

driveslowtoactivatetheseconddevice’snCEpin,whichpromptstheseconddevice

tobeginconfiguration.Theseconddeviceinthechainbeginsconfigurationwithin

oneclockcycle.Therefore,thetransferofdatadestinationsistransparenttothe

MAXIIdevice.Allotherconfigurationpins(nCONFIG,nSTATUS,DCLK,DATA0,and

CONF_DONE)areconnectedtoeverydeviceinthechain.Configurationsignalscan

requirebufferingtoensuresignalintegrityandpreventclockskewproblems.Ensure

thattheDCLKandDATAlinesarebufferedforeveryfourthdevice.Becausealldevice

CONF_DONEpinsaretiedtogether,alldevicesinitializeandenterusermodeatthe

sametime.

SinceallnSTATUSandCONF_DONEpinsaretiedtogether,ifanydevicedetectsan

error,configurationstopsfortheentirechainandyoumustreconfiguretheentire

chain.Forexample,ifthefirstdeviceflagsanerroronnSTATUS,itresetsthechainby

pullingitsnSTATUSpinlow.Thisbehaviorissimilartoasingledevicedetectingan

error.

StratixIIIDeviceHandbook,Volume1

Chapter11:ConfiguringStratixIIIDevices

PassiveSerialConfiguration

IftheAuto-restartconfigurationaftererroroptionisturnedon,thedevicesrelease

theirnSTATUSpinsafteraresettime-outperiod(maximumof100μs).Afterall

nSTATUSpinsarereleasedandpulledhigh,theMAXIIdevicecanattemptto

reconfigurethechainwithoutneedingtopulsenCONFIGlow.Ifthisoptionisturned

off,theMAXIIdevicemustgeneratealow-to-hightransition(withalowpulseofat

least2μs)onnCONFIGtorestarttheconfigurationprocess.

1IfyouhaveenabledtheAuto-restartconfigurationaftererroroption,thenSTATUSpin

transitionsfromhightolowandbackagaintohighwhenaconfigurationerroris

detected.ThisappearsasalowpulseatthenSTATUSpinwithaminimumpulsewidth

of10μstoamaximumpulsewidthof500μs,asdefinedinthet

specification.

STATUS

Inyoursystem,youcanhavemultipledevicesthatcontainthesameconfiguration

data.Tosupportthisconfigurationscheme,alldevicenCEinputsaretiedtoGND,

whilenCEOpinsareleftfloating.Allotherconfigurationpins(nCONFIG,nSTATUS,

DCLK,DATA0,andCONF_DONE)areconnectedtoeverydeviceinthechain.

Configurationsignalscanrequirebufferingtoensuresignalintegrityandprevent

clockskewproblems.EnsurethattheDCLKandDATAlinesarebufferedforevery

fourthdevice.Devicesmustbethesamedensityandpackage.Alldeviceswillstart

andcompleteconfigurationatthesametime.Figure11–15showsmulti-devicePS

configurationwhenbothStratixIIIdevicesarereceivingthesameconfigurationdata.

Figure11–15.Multiple-DevicePSConfigurationWhenBothDevicesReceivetheSameData

Memory

VCCPGM(1)VCCPGM

(1)

ADDR

DATA0

StratixIIIDevice

StratixIIIDevice

10kΩ

10kΩ

CONF_DONE

nSTATUS

CONF_DONE

nCEO

N.C.(2)

nSTATUS

nCE

N.C.(2)

nCEO

ExternalHost

(MAXIIDeviceor

Microprocessor)

nCE

V

CCPGMGND

VCCPGM

GND

MSEL2

MSEL1

MSEL0

MSEL2

MSEL1

MSEL0

DATA0

DATA0

nCONFIG

DCLK

nCONFIG

DCLK

GND

GND

NotestoFigure11–15:

(1)ConnecttheresistortoasupplythatprovidesanacceptableinputsignalforallStratixIIIdevicesonthechain.V

meettheVspecificationoftheI/Oontheexternalhost.Itisrecommendedtopowerupallconfigurationsystems’I/OwithV

mustbehighenoughto

.

CCPGM

IH

CCPGM

(2)ThenCEOpinsofbothdevicesareleftunconnectedwhenconfiguringthesameconfigurationdataintomultipledevices.

YoucanuseasingleconfigurationchaintoconfigureStratixIIIdeviceswithother

Alteradevices.Toensurethatalldevicesinthechaincompleteconfigurationatthe

sametime,orthatanerrorflaggedbyonedeviceinitiatesreconfigurationinall

devices,allofthedeviceCONF_DONEandnSTATUSpinsmustbetiedtogether.

fFormoreinformationaboutconfiguringmultipleAlteradevicesinthesame

configurationchain,refertotheConfiguringMixedAlteraFPGAChainschapterinthe

ConfigurationHandbook.

StratixIIIDeviceHandbook,Volume1

Chapter11:ConfiguringStratixIIIDevices

DeviceConfigurationPins

StratixIIIDeviceHandbook,Volume1

Chapter11:ConfiguringStratixIIIDevices

DeviceConfigurationPins

Table11–13.StratixIIIConfigurationPinSummary(Note1)(Part2of2)

Description

MSEL[2..0]

Input/Output

Dedicated

PoweredBy

ConfigurationMode

Input

Yes

V

Allmodes

CCPGM

NotestoTable11–13:

(1)Thetotalnumberofpinsis30.Thetotalnumberofdedicatedpinsis19.

(2)TheJTAGoutputpinTDOandallJTAGinputpinsarepoweredbythe2.5V/3.0V/3.3-VV

powersupplyofI/Obank1A.

CCPD

(3)ThesedualpurposepinsarepoweredbyV

configurationmodes.

duringconfiguration,thenarepoweredbyV

whileinusermode.Thisappliesforall

CCIO

CCPGM

Table11–14describesthededicatedconfigurationpins,whicharerequiredtobe

connectedproperlyonyourboardforsuccessfulconfiguration.Someofthesepins

maynotberequiredforyourconfigurationschemes.

Table11–14.DedicatedConfigurationPinsontheStratixIIIDevice(Part1of5)

Configuration

Scheme

PinName

UserMode

PinType

Description

Dedicatedpowerpin.Usethispintopoweralldedicated

configurationinputs,dedicatedconfigurationoutputs,

dedicatedconfigurationbi-directionpins,andsomeof

thedualfunctionalpinsthatareusedforconfiguration.

Youmustconnectthispinto1.8-V,2.5-V,3.0-V,or

mustramp-upfrom0-Vto3.3-Vwithin100

isnotrampedupwithinthisspecifiedtime,

VCCPGM

N/A

All

Power

3.3-V.V

ms.IfV

CCPGM

CCPGM

yourStratixIIIdevicewillnotconfiguresuccessfully.If

yoursystemdoesnotallowforaVCCPGMramp-up

timeof100msorless,youmustholdnCONFIGlow

untilallpowersuppliesarestable.

Dedicatedpowerpin.UsethispintopowertheI/O

pre-drive