多核處理器(共23張PPT)

多核處理器□

Evolvement

of

computer

architecturescalarsequenceoverlap

Fun

parallelMulti

fun

Pipe

linePseudo-vecto

Obvious

vectopm

m

I'-

1Eedgend

Multi

multiprocesprocessor

processing

array

computerMulti-Core第二節(jié)共享存儲器多處理機(jī)系統(tǒng)口

多核處理器系統(tǒng)■

系統(tǒng)中包含一個多核的處理器芯片■

每個處理器核能夠獨(dú)立運(yùn)行程序口

單核多處理器系統(tǒng)■

多個單核的處理器構(gòu)成的系統(tǒng)■

處理器之間的通信延遲時間較長口

多核多處理器系統(tǒng)■

多個多核處理器構(gòu)成的并行系統(tǒng)■

兩個并行處理的層次□

按程序特征MIMD■

SPMD□

代

替SIMD□

按處理機(jī)特征■

同

構(gòu)homogenius■

異構(gòu)heterogenius多處理機(jī)系統(tǒng)的結(jié)構(gòu)分類互連網(wǎng)絡(luò)MCPUCPUCPUMM□

獨(dú)立的指令執(zhí)行和控制單元■獨(dú)立的功能部件■

獨(dú)立的控制器□

完整的指令流水線多核處理器分類□

單核多線程處理器■

單

核CPU

構(gòu)

成□

多核處理器■

多核芯片構(gòu)成□

多核多線程處理器■

每個核都是多線程的DRAMs

DRAMsMemory

Memorycontroller

controllerL2

L2cache

bank

cache

bankGlobal

switchInstruction

Data

Instruction

Data

cache

cache

cache

cacheMultithreaded

Multithreadedcore

coreMemorycontrollerL2cache

bank

VOInstruction|

Datacache

cacheMultithreadedcore·

DRAMs·ArchitectualState

Architectual

StateExecution

Engine

Execution

EngineLocal

APIC

Local

APICSecond

Level

CacheBus

InterfaceMutli-core

Memory

HierarchyLocal

LocalAPIC

APICSecond

Level

CacheBus

InterfaceLocal

LocalAPIC

APICSecond

Level

CacheBus

InterfaceLocalAPICSecond

Level

CacheBus

InterfaceLocalAPICSecond

Level

CacheBus

InterfaceArch.

Arch.

Arch.

Arch.State

State

State

StateExecution

Engine

Execution

EngineArchitectual

State

Architectual

StateExecution

Engine

Execution

EngineSystem

BusSystem

BusSystem

Bus多核處理器的分類CacheCacheCUEUEUCache單核多線程處理器單核單線程處理器多核多線程處理器CUEU多核處理器InterruptCU:CPUstate

+CacheCUCUCachelogicEUEUCUCUCUCU□CU

EU

CU

EU

CU

EU

CU

EUCache多

核

處

理

機(jī)共享存儲器CU

EUCU

EU

CU

EUCache

Cache

Cache單核多處理機(jī)系統(tǒng)共享存儲器互連網(wǎng)絡(luò)CU

EU

CU

EU

CU

EU

CU

EUCache多核多處理機(jī)系統(tǒng)共享存儲器互連網(wǎng)絡(luò)Deeper

Pipelining□

d

pe

atyhet

c

o

pli

rmance

further

is

toa

a

pipeline

twice

as

deep

as

the

original

pipeline

is□

Once

the

deep

pipeline

is

filled,

two

new

instructionsefoneripeepvrralaimpsonweneeOcapable

of

twice

the

peak

execution

rate.are

completed

every

original

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Pipeliningshallow

scalar

pipelinedeep

scalar

pipelineDeeper

Pipelining□

However,

in

practice,

doubling

pipeline

depth

does

not

doubler

because

there

are

relatively

more

stall

cycles

that

need

totednceaaermlrootfee□

A

larger

instruction

window

is

needed

to

hide

lengthier

stalls

due

todata

hazards

(for

example,

data

cache

misses

take

more

cycles

toresolve

since

memory

access

time

in

nanoseconds

is

unchanged).□

is

edic

n

l

t(

o

s

b

n

I

ean

a

).EXnchdbrFthtweeecauseebsdtageneedereismorrcedigerrapshicltyranabeetion

paccuratpremormAsuperscalar

processing□

An

alternative

to

deeper

pipelining

is

to

fetch,issue,

and

execute

multiple

instructions

in

paralleleach

cycle,

exceeding

the

scalar

bottleneckexplicitly.□

This

approach

is

called,

appropriately,

superscalarprocessing.□

A

dual-issue

superscalar

processor

doubles

thepeak

execution

rate

with

respect

to

the

originalscalar

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processingscalarsuperscalarHardware

multithreading□

Hardware

multithreading

is

a

means

for

improving

pipeline□

It

enables

the

simultaneous

execution

of

multiple

independentprograms

on

the

same

pipeline.□

Independent

programs

are

an

abundant

source

of

instruction-leve/parallelism,

since

there

are

no

dependences

between

instructionsutilization

when

bottlenecks

prevent

further

speedup

of

single-from

different

threads.□

Hardware

multithreading

improves

pipeline

utilization

by

convertingthread-level

parallelism

to

instruction-level

parallelismthreaded

programs.early

forms

of

hardwaremultithreadinga

instructions

are

fetched

from

a

different

threadeach

cyclePipeline

stage:IFIDEXMEMWBDua/-issueT5T4T3T2T1superscalarpipelineT5T4T3T2T1Two

parallel

instructions

from

Thread

5Pipeline

stage:IFIDEXMEMWBDual-issueT1T4T1T2T1superscalarpipelineT3T1T1T4T5Simultaneous

multithreading□

Simultaneous

multithreading(SMT)

is

even

moreflexible:

a

singlepipeline

stage

may

mix

instructions

from

multiple

threads

during

theTwo

parallel

instructions,

one

from

Thread1

andone

fromThread3same

cycleDynamic

Scheduling□

Dynamic

scheduling

provides

a

means

forindependent

instructions

to

circumvent

previousstalled

instructions

and,

therefore,

execute

out-of-order.a

Out-of-order

execution

allows

useful

work

to

beoverlapped

with

the

load-use

stallsDynamic

Scheduling□

The

key

mechanism

forout-of-orderexecution

is

a

pool

of

instruction

buffersthat

decouples

the

instruction

fetch/decodestages

from

later

execution

stagesThese

instruction

buffers,

collectively

called

thescheduling

window

or

instruction

window,

providea

staging

area

in

which

instructions

wait

fortheir

source

operands

to

become

available.Instruction

fetch

engineInstruction

windowInstruction

executionengineDynamic

Scheduling□

Dynamic

scheduling

adds

another

stage

to

thepipeline

between

decode(ID)

and

execute