直接數(shù)字頻率合成技術(shù)中英文對(duì)照外文翻譯文獻(xiàn)

中英文資料外文翻譯文獻(xiàn) 原文：DDSdevicestoproducehigh-qualitywaveform:asimple,efficientandflexibleSummaryDirectdigitalfrequencysynthesis(DDS)technologyforthegenerationandregulationofhigh-qualitywaveforms,widelyusedinmedical,industrial,instrumentation,communications,defenseandmanyotherareas.Thisarticlewillbrieflydescribethetechnology,onitsstrengthsandweaknesses,examinesomeapplicationexamples,andalsointroducedsomenewproductsthatcontributetothepromotionIntroductionAkeyrequirementinmanyindustriesisanexactproduction,easyoperationandquickchangeofdifferentfrequencies,differenttypesofwaveforms.Whetheritisbroadbandtransceiverrequireslowphasenoiseandexcellentspurious-freedynamicperformanceofagilefrequencysource,orforindustrialmeasurementandcontrolsystemneedsastablefrequencyexcitation,fast,easyandeconomicaltoproduceadjustablewaveformwhilemaintainingphasecontinuitycapabilitiesarecriticaltoadesignstandard,whichiswhattheadvantagesofdirectdigitalfrequencysynthesis.FrequencysynthesistaskThegrowingcongestionofthespectrum,coupledwithlowerpowerconsumption,qualityofnever-endingdemandforhighermeasuringequipment,thesefactorsrequiretheuseofthenewfrequencyrange,requiresabetteruseofexistingfrequencyrange.Aresult,thesearchforbettercontrol,inmostcases,bymeansoffrequencysynthesizerforfrequencygeneration.Thesedevicesuseagivenfrequency,fCoftogenerateatargetfrequency(andphase)fOUTthegeneralrelationshipcanbesimplyexpressedas:fOUT=εx×fCAmongthem,thescalefactorεx,sometimesknownasthenormalizedfrequency.Theequationisusuallygradualapproximationoftherealnumberalgorithms.Whenthescalefactorisarationalnumber,tworelativelyprimenumbers(outputfrequencyandreferencefrequency)thantheharmonic.However,inmostcases,εxmaybelongtoabroadersetofrealnumbers,theapproximationprocessiswithintheacceptablerangewillbetruncatedDirectDigitalFrequencySynthesizerThefrequencysynthesizerapracticalwaytoachieveisthedirectdigitalfrequencysynthesis(ofDDFS),usuallyreferredtoasdirectdigitalsynthesis(DDS).Thistechniqueusingdigitaldataprocessingtogenerateafrequencyandphaseadjustableoutput,theoutputandafixedfrequencyreferenceclocksourcefC.related.DDSarchitecture,thereferenceorthesystemclockfrequencydividedbyascalefactortoproducethedesiredfrequency,thescalefactoriscontrolledbythebinarytuningwordprogrammable.Inshort,directdigitalfrequencysynthesizertoconvertabunchofclockpulsesintoananalogwaveform,usuallyasinewave,trianglewaveorsquarewave.ShowninFigure1,itsmainparts:thephaseaccumulator(toproducetheoutputwaveformphaseangledata),relativetodigitalconverter,(abovethephasedataisconvertedtotheinstantaneousoutputamplitudedata),anddigital-to-analogconverter(DAC)(themagnitudeofdataintoasampledanalogdatapoints)Figure1.DDSfunctionofthesystemblockdiagram.Forthesinewaveoutput,relativetodigitalconverterisusuallyasinelookuptable(Figure2).PhaseaccumulatorunitcountNarelativetothefrequencyoffC,accordingtothefollowingequation:ThenumberofpulsesofthefC:Mistheresolutionofthetuningword(24-48)NcorrespondstothesmallestincrementofphasechangeofthephaseaccumulatoroutputwordFigure2.TypicalDDSarchitectureandsignalpath(withDACs).ChangingNwillimmediatelychangetheoutputphaseandfrequency,sothesystemhasitsowncontinuousphasecharacteristics,whichisoneofthekeyattributesofmanyapplications.Noloopsettlingtime,whichisdifferentfromtheanalogsystem,suchasphase-lockedloops(PLLs).DACisusuallyahigh-performancecircuit,designedspecificallyfortheDDScore(phaseaccumulatorandphaseamplitudeconverter).Inmostcases,theresultsofthedevice(usuallysingle-chip)isgenerallyreferredtoasthepureDDSortheC-DDS.ActualDDSdevicesaregenerallymultipleregisters,inordertoachieveadifferentfrequencyandphasemodulationscheme.Suchasphaseregister,theirstoragephaseofincreaseintheoutputphaseofthephaseaccumulator.Inthisway,thecorrespondingdelayoutputsinewavephaseinaphasetuningword.Thisisusefulforphasemodulationapplicationsforcommunicationsystems.Theresolutionoftheaddercircuitdeterminesthenumberofbitsofthephasetuningword,therefore,alsodecidedtodelaytheresolution.IntegratedinasingledeviceontheengineofaDDSandaDAChasbothadvantagesanddisadvantages,however,whetherintegratedornot,needaDACtoproduceultra-highpurityhigh-qualityanalogsignal.DACwillconvertdigitalsinusoidaloutputtoananalogsinewavemaybesingle-endedordifferential.Someofthekeyrequirementsforlowphasenoise,excellentwideband(WB)andnarrowband(NB),spurious-freedynamicrange(SFDR),andlowpowerconsumption.Iftheexternaldevice,theDACmustbefastenoughtohandlethesignal,sothebuilt-inparallelportdeviceisverycommon.DDSandothersolutionsThefrequencyanalogphase-lockedloops(PLLs),clockgenerator,andtheuseofFPGAdynamicprogrammingoftheoutputoftheDAC.Byexaminingthespectrumofperformanceandpowerofthesetechnologies,asimplecomparison,Table1showsthequalitativeresultsofthecomparisonTable1.DDSwithcompetingtechnologies-AdvancedcomparePowerconsumptionSpectralpurityRemarksDDSLowMiddleEaseoftuningDiscreteDAC+FPGAMiddleMiddle-HighWithtuningcapabilitiesAnalogPLLMilddleHighDifficulttuningPhase-lockedloopisafeedbackloopanditscomponents:aphasecomparator,adividerandapressure-controlledoscillator(VCO),phasecomparatorreferencefrequencyandoutputfrequency(usuallytheoutputfrequencyisN)frequency)werecompared.TheerrorvoltagegeneratedbythephasecomparatorisusedtoadjusttheVCO,thustheoutputfrequency.Whentheloopisestablished,theoutputfrequencyand/orphasewiththereferencefrequencytomaintainapreciserelationship.PLLhaslongbeenconsideredinaparticularfrequencyrange,highfidelityandconsistentsignallowphasenoiseandhighspuriousfreedynamicrange(SFDR)areidealforapplications.

PLLcannotbepreciselyandquicklytuningthefrequencyoutputwaveform,andtheslowresponse,whichlimitstheirapplicabilityforfastfrequencyhoppingandpartofthefrequencyshiftkeyingandphaseshiftkeyingapplications.

Otherprograms,includingintegratedDDSenginefieldprogrammablegatearrays(FPGAs)-asyntheticsinewaveoutputwiththeoff-the-shelfDAC-thoughthePLLfrequency-hoppingproblemcanbesolved,butthereownshortcomings.Thedefectsofthemajorsystemsworkandinterfacepowerrequirements,highcost,largesize,andsystemdevelopersmustalsoconsidertheadditionalsoftware,hardwareandmemory.Forexample,usingtheDDSengineoptioninthemodernFPGAtogeneratethe10MHzoutputsignaldynamicrangeis60dBupto72kBmemoryspace.Inaddition,designersneedtoacceptandbefamiliarwiththesubtlebalanceDDScorearchitecture..

Fromapracticalpointofview(seeTable2),thankstotherapiddevelopmentofCMOStechnologyandmoderndigitaldesigntechniques,aswellastheimprovementoftheDACtopology,DDStechnologyhasbeenabletoachieveunprecedentedlowpowerconsumptioninawiderangeofapplications,spectrumperformanceandcostlevels.AlthoughthepureDDSproductsinperformanceanddesignflexibilitytoachievethelevelofhigh-endDACtechnologyandFPGA,buttheadvantagesofDDSintermsofsize,powerconsumption,costandsimplicity,makingittheprimarychoiceformanyapplications.Table2BenchmarkAnalysisSummary-frequencygenerationtechnique(<50MHz)Phase-lockedloopDAC+FPGADDSSpectralperformanceHighHighMiddleSystempowerrequirementsHighHighMiddleDigitalfrequencytuningNoYesYesTuningresponsetimeHighLowLowSolutionsizeMiddleHighLowWaveformflexibilityLowMiddleHighCostMiddleHighLowDesignreuseMiddleLowHighImplementationcomplexityMiddleHighLowAlsobenotedthattheDDSdevicefordigitalmethodstoproducetheoutputwaveform,itcansimplifysomeofthearchitectureofthesolution,orthewaveformofdigitalprogrammingtocreatetheconditions.UsuallywithasinewavetoexplainthefunctionsandworkingprincipleoftheDDS,butusingmodernDDSICscaneasilygenerateatrianglewaveorsquarewave(clock)output,therebyeliminatingtheformercasethelookuptable,andthelattercasetheDACtheneedtointegrateasimpleandaccurateenough.PerformanceandlimitationsoftheDDSImageandenvelope:Sin(x)xxroll-offTheactualoutputoftheDACisnotacontinuoussinewave,butaseriesofpulseswithasinusoidaltimeenvelope.Thecorrespondingspectrumisaseriesofimageandsignalaliasing.Imagealongthesin(x)/xenvelopedistribution(seeFigure3|margin|graph).Theneedforthefiltertosuppressfrequenciesoutsidethetargetband,butcannotinhibitthehigh-levelinthepassbandaliasing(forexample,causedduetoDACnon-linear)TheNyquistcriterionrequiresthateachcyclerequiresatleasttwosamplingpointsinordertorebuildthedesiredoutputwaveform.TheMirroringresponsearisingfromsamplingtheoutputfrequencyK,CLOCK×OUTInthisexample,whichCLOCK=2525MHzandfOUT=5MHz,thefirstandsecondmirrorfrequencyappearin(seeFigure3)fCLOCK×fOUT,??o20MHzand30MHz.Thethirdandfourthmirrorfrequencyat45MHzand55MHz.Note,sin(x)/xvalueofzeroatmultiplesofthesamplingfrequency.WhenfOUTgreaterthantheNyquistbandwidth(1/2fCLOCK),thefirstmirrorfrequencywillappearintheNyquistbandwidth,theoccurrenceofaliasing(suchas15MHzsignalaliasingdownto10MHz).Cannotusethetraditionalquistanti-aliasingfiltertofilteroutaliasingmirrorfrequencyfromtheoutputSin,inFigure3.DDS,(x)/xroll-off.InatypicalDDSapplication,theuseofalow-passfiltertosuppressthemirrorfrequencyresponseoftheoutputspectrum.Tomakethelow-passfiltercutofffrequencytoremainatreasonablelevels,andkeepitsimplefilterdesign,afeasibleapproachistheuseofaneconomiclow-passoutputfilterbandwidthlimitedtoabout40%ofthefrequencyofclock.

Anygivenmirrorfrequencyrelativetotheamplitudeofthefundamentalformulaofsin(x)/xcalculation.Becausethefunctionofthefrequencyroll-off,thebasicoutputoftheamplitudeandtheoutputfrequencyisinverselyproportionaltodecrease;intheDDSsystem,reducetheamountofDC-Nyquistbandwidthrangeof-3.92dB.

Significantreductioninfrequencyinthefirstmirror-thefundamental3dBrange.InordertosimplifytheDDSapplicationfiltering,frequencyplanmustbeformulatedandanalyzedtomirrorthefrequencyandmagnitudeofthesin(x)/xresponseintheOUTandCLOCKtargetfrequencyspectrumrequirements.Otherunwantedfrequenciesintheoutputspectrum(suchasintegralanddifferentiallinearityerroroftheDAC,thesurgeofenergyassociatedwiththeDACandclockfeedthroughnoise)doesnotfollowthesin(x)/xroll-offresponse.Theseunwantedfrequencieswillbeharmonicandspuriousenergyintheoutputspectruminmanyplaces-butitsmagnitudeisgenerallyfarbelowthemirrorfrequencyresponse.DDSdevicestothegeneralbackgroundnoise,substratenoise,thermalnoiseeffects,groundcouplingandothersignalsourcecouplingfactorcumulativeportfoliodecisions.DDSdevices,thenoisefloorperformanceofstrayandjitterbythecircuitboardlayout,powerquality,and-mostimportantly-Entertheprofoundimpactofthequalityofthereferenceclock.ShakeTheedgeoftheperfectclocksourcewillbetheprecisetimeinterval,theintervalwillneverchange.Ofcourse,thisisnotpossible;eventhebestoscillatorisalsotheidealcomponentsconstitute,withnoiseandotherdefects.Qualityandlowphasenoisecrystaloscillatorjitterpicosecond,andisbuiltupfromonemillionthenumberofclockedge.Thefactorsleadingtojitterexternalinterference,thermalnoise,theoscillatorcircuitinstabilityandpower,groundandoutputconnectionsbring,allthesefactorswillinterferewiththetimingcharacteristicsoftheoscillator.Inaddition,theoscillatorbytheexternalmagneticfieldorelectricfieldandthenearbytransmitterRFinterference.Oscillatorcircuit,asimpleamplifier,inverterorbuffertosignaladditionaljitter.

Therefore,thechoiceofalow-jitter,andtheedgeofsteepstablereferenceclockoscillatoriscritical.Higherfrequencyreferenceclockallowsalargersample,anddividetosomeextent,reducethejitter,becausethesignaltodividealongtimetoproducethesameamountofjitter,whichcanreducethejitteronthesignalpercentage.Noise-includingthephasenoiseThesamplingsystemnoisedependsonmanyfactors,themostimportantfactoristhereferenceclockjitter,thisjitterperformanceofphasenoiseonfundamentalsignal.IntheDDSsystem,theregisteroutputofthetruncatedphasemaybringthesystemerrorcode.Thebinaryworddoesnotleadtothetruncationerror.Butfornon-binaryword,phasenoisetruncationerrorinthespectrumspurious.Spuriousfrequency/amplitudedependsonthecodeword.QuantificationandlinearityerroroftheDACwillbebroughttothesystemharmonicnoise.Time-domainerror(suchasowedtothered/overshootandcodeerrors)willincreasetheoutputsignaldistortion.ApplicationDDSapplicationscanbedividedintotwocategories:Requireagilefrequencysourcefordatacodingandmodulationapplications,communicationsandradarsystems

Requiremeasurementoftheuniversalfrequencysynthesizerfeaturesandprogrammabletuning,scanning,andmotivationalskills,industrialandopticalapplicationsBothcases,thetrendtowardhigherspectralpurity(lowphasenoiseandhigherspuriousfreedynamicrange),alsolowpowerandsmallsizerequirementstoaccommodatetheremoteordemandforbattery-powereddevices.Modulation/dataencoding,andsynchronizationoftheDDSDDSproductsfirstappearedontheradarandmilitaryapplicationsandthedevelopmentofsomeofitscharacteristics(performanceimprovements,costandsize,etc.)DDStechnologyisbecomingmoreprevalentinthemodulationanddataencodingapplications.ThissectionwilldiscussthetwodataencodingschemeintheDDSsystem.Binaryfrequencyshiftkeying(BFSK,orreferredtoasFSK)oneofthemostsimpleformofdataencoding.Thelaunchofthedataisacontinuouscarrierfrequencyintwodiscretefrequency(binaryone,ie,passnumber,abinary0,namely,thetransformationbetweenthespace).Figure4showstherelationshipbetweenthedataandtransmitsignals.Figure4binaryFSKmodulation.Binary1and0fortwodifferentfrequenciesf0andf1,respectively.ThisencodingschemecanbeeasilyDDSdevice.OnbehalfoftheoutputfrequencyoftheDDSfrequencytuningwordchangetof0andf1,willlaunchthe1and0.TotransformtheoutputfrequencyshalldedicatedpinFSELECT,containingtheappropriatetuningwordregisters(seeFigure5)Figure5.AD9834orAD9838DDStuningwordselectorrealizationoftheFSKencoding.Phaseshiftkeying(PSK)isasimpleformofdataencoding.InPSK,thecarrierfrequencyremainsthesame,bychangingthephaseofthetransmittedsignaltotransmitinformation.CantakeadvantageofavarietyofprogramstoachievePSK,.TheeasiestwayisoftenreferredtoasbinaryPSK(BPSK),usingonlytwosignalphase:0°(logic1)and180°(logic0).Membersstatedependsonthestatusoftheformerone.Ifthewavephaseremainsunchanged,thesignalstatewillremainthesame(loworhigh).Wavephasechange180°,ie,phaseinversion,thesignalstatewillchange(lowintohighorhightolow).PSKcodinginDDSproductscanbeeasilyachieved,becausemostdeviceshaveaseparateinputregister(phaseregister),andphasevaluescanbeloaded.Thisvalueisaddeddirectlytothecarrierphase,withoutchangingitsfrequency.Changethecontentsoftheregisterwillbemodulatedcarrierphase,resultinginaPSKoutput.Forapplicationsthatrequirehigh-speedmodulation,built-inphaseregisteroftheAD9834andAD9838allowPSELECTpinsignaltransformation,accordingtoneedmodulatedcarrierinthepreloadedphaseregisters.

ThemorecomplexthePSKfouroreight-wavephase.Thus,wheneverthephasechangeofbinarydatatransferratewillbehigherthantheBPSKmodulation.Inthefour-phasemodulation(QuadraturePSK),inthephaseangleof0°to+90°,-90°and+180°;eachphasetotransformthetwosignalsmayrepresentafactorAD9830,AD9831,AD9832,andtheAD9835providesfourphaseregisters,canbecontinuouslyupdatedregisterofdifferentphaseshift,thecomplexphasemodulationscheme.TheuseofsynchronousmodeofmultipleDDSdevicestoachievetheI/QMultipleDDScomponentstoachievethemanyapplicationsoftheI/Qsinewaveorsquarewavesignalofknownphaserelationshipbetweentwoormoresynchronousmode.Acommonexampleisthesamephaseandquadraturemodulation(I/Q)inthistechnique,thephaseangleof0°and90°fromthecarrierfrequencysignalinformation.ToruntwoseparateDDScomponents,youcanusethesamesourceclocktooutputcandirectlycontrolandmanipulatethesignalofthephaserelationship.InFigure6,withareferenceclockontheAD9838deviceprogramming;theRESETpinisusedtoupdatethetwodevices.Inthisway,youcanachieveasimpleI/Qmodulation

RESETafterpowerandinitializedbeforeanydatatotheDDStransmission.DDSoutputresultscanbeplacedinaknownphase,makingitacommonreferencepointofview,inordertosynchronizemultipleDDSdevices.WhennewdataissenttomultipleDDSdevices,theDDScanremainrelevantphaserelationship,orbythephaseoffsetregistercanpredicttherelativephaseshiftbetweentheadjustmentsofmultipleDDS.TheAD983xseriesofDDSproductshavea12phaseresolution,theeffectiveresolutionof0.1°.Figure6.SynchronizethetwoDDScomponents.譯文：DDS器件產(chǎn)生高質(zhì)量波形：簡(jiǎn)單、高效而靈活摘要

直接數(shù)字頻率合成(DDS)技術(shù)用于產(chǎn)生和調(diào)節(jié)高質(zhì)量波形，廣泛用于醫(yī)學(xué)、工業(yè)、儀器儀表、通信、國(guó)防等眾多領(lǐng)域。本文將簡(jiǎn)要介紹該技術(shù)，說(shuō)明其優(yōu)勢(shì)和不足，考察一些應(yīng)用示例，同時(shí)介紹一些有助于該技術(shù)推廣的新產(chǎn)品。簡(jiǎn)介

許多行業(yè)中一個(gè)關(guān)鍵的需求是精確產(chǎn)生、輕松操作并快速更改不同頻率、不同類型的波形。無(wú)論是寬帶收發(fā)器要求具有低相位噪聲和出色的無(wú)雜散動(dòng)態(tài)性能的捷變頻率源，還是工業(yè)測(cè)量和控制系統(tǒng)需要穩(wěn)定的頻率激勵(lì)，快速、輕松、經(jīng)濟(jì)地產(chǎn)生可調(diào)波形并同時(shí)維持相位連續(xù)性的能力都是至關(guān)重要的一項(xiàng)設(shè)計(jì)標(biāo)準(zhǔn)，而這正是直接數(shù)字頻率合成技術(shù)的優(yōu)勢(shì)所在。頻率合成的任務(wù)。

不斷增多的頻譜擁堵，加上對(duì)功耗更低、質(zhì)量更高的測(cè)量設(shè)備的永無(wú)止境的需求，這些因素都要求使用新的頻率范圍，要求更好地利用現(xiàn)有頻率范圍。結(jié)果，人們尋求對(duì)頻率產(chǎn)生進(jìn)行更好的控制，多數(shù)情況下，均是借助于頻率合成器.這些器件利用一個(gè)給定頻率,fC來(lái)產(chǎn)生一個(gè)相關(guān)的目標(biāo)頻率（和相位）fOUT.其一般關(guān)系可以簡(jiǎn)單地表示為：fOUT=εx×fC其中，比例因子εx,有時(shí)也被稱為歸一化頻率.該等式通常利用實(shí)數(shù)逐步逼近的算法實(shí)現(xiàn)。當(dāng)比例因子為有理數(shù)時(shí)，兩個(gè)相對(duì)質(zhì)數(shù)（輸出頻率和基準(zhǔn)頻率）之比將諧波相關(guān)。但在多數(shù)情況下，εx可能屬于更廣泛的實(shí)數(shù)集，逼近過(guò)程一旦處于可接受的范圍之內(nèi)即會(huì)被截?cái)唷Ｖ苯訑?shù)字頻率合成

頻率合成器的一種實(shí)用型實(shí)現(xiàn)方式是直接數(shù)字頻率合成(DDFS),通常簡(jiǎn)稱為直接數(shù)字合成(DDS).這種技術(shù)利用數(shù)字?jǐn)?shù)據(jù)處理來(lái)產(chǎn)生一個(gè)頻率和相位可調(diào)的輸出，該輸出與一個(gè)固定的頻率參考或時(shí)鐘源fC.相關(guān)。在DDS架構(gòu)中，參考或系統(tǒng)時(shí)鐘頻率由一個(gè)比例因子分頻來(lái)產(chǎn)生所需頻率，該比例因子由二進(jìn)制調(diào)諧字可編程控制。簡(jiǎn)言之，直接數(shù)字頻率合成器將一串時(shí)鐘脈沖轉(zhuǎn)換成一個(gè)模擬波形，通常為一個(gè)正弦波、三角波或方波。如圖1所示，其主要部分為：相位累加器（產(chǎn)生輸出波形相位角度的數(shù)據(jù)），相數(shù)轉(zhuǎn)換器,（將上述相位數(shù)據(jù)轉(zhuǎn)換為瞬時(shí)輸出幅度數(shù)據(jù)），以及數(shù)模轉(zhuǎn)換器(DAC)（將該幅度數(shù)據(jù)轉(zhuǎn)換成采樣模擬數(shù)據(jù)點(diǎn)）。圖1.DDS系統(tǒng)的功能框圖對(duì)于正弦波輸出，相數(shù)轉(zhuǎn)換器通常為一個(gè)正弦查找表（圖2）。相位累加器以N為單位計(jì)數(shù)，并根據(jù)以下等式產(chǎn)生一個(gè)相對(duì)于fC的頻率:其中：

M為調(diào)諧字的分辨率（24至48位）

N為對(duì)應(yīng)于相位累加器輸出字最小增量相位變化的fC的脈沖數(shù)圖2.典型的DDS架構(gòu)和信號(hào)路徑（帶DAC）由于更改N會(huì)立即改變輸出相位和頻率，因此，系統(tǒng)自身具有相位連續(xù),特點(diǎn)，這是許多應(yīng)用的關(guān)鍵屬性之一。無(wú)需環(huán)路建立時(shí)間，這與模擬系統(tǒng)不同，如鎖相環(huán)(PLL)。DAC通常為一個(gè)高性能電路，專門針對(duì)DDS內(nèi)核（相位累加器和相幅轉(zhuǎn)換器）而設(shè)計(jì)。多數(shù)情況下，這樣結(jié)果形成的器件（通常為單芯片）一般稱為純DDS或C-DDS。實(shí)際的DDS器件一般集成多個(gè)寄存器，以實(shí)現(xiàn)不同的頻率和相位調(diào)制方案。如相位寄存器，其存儲(chǔ)的相位內(nèi)容被加在相位累加器的輸出相位上。這樣，可以對(duì)應(yīng)于一個(gè)相位調(diào)諧字延遲輸出正弦波的相位。對(duì)于通信系統(tǒng)相位調(diào)制應(yīng)用，這非常有用。加法器電路的分辨率決定著相位調(diào)諧字的位數(shù)，因此，也決定著延遲的分辨率。在單個(gè)器件上集成一個(gè)DDS引擎和一個(gè)DAC既有優(yōu)點(diǎn)也有缺點(diǎn)，但是，無(wú)論集成與否，都需要一個(gè)DAC來(lái)產(chǎn)生純度超高的高品質(zhì)模擬信號(hào)。DAC將數(shù)字正弦輸出轉(zhuǎn)換為一個(gè)模擬正弦波，可能是單端，也可能是差分。一些關(guān)鍵要求是低相位噪聲、優(yōu)秀的寬帶(WB)和窄帶(NB)無(wú)雜散動(dòng)態(tài)范圍(SFDR)以及低功耗。如果是外部器件，則DAC必須足夠快以處理信號(hào)，因此，內(nèi)置并行端口的器件非常常見。DDS與其他解決方案

其他產(chǎn)生頻率的方法包括模擬鎖相環(huán)(PLL),時(shí)鐘發(fā)生器和利用FPGA對(duì)DAC的輸出進(jìn)行動(dòng)態(tài)編程。通過(guò)考察頻譜性能和功耗，可以對(duì)這些技術(shù)進(jìn)行簡(jiǎn)單的比較，表1以定性方式展示了比較結(jié)果。表1.DDS與競(jìng)爭(zhēng)技術(shù)——高級(jí)比較功耗頻譜純度備注DDS低中易于調(diào)諧分立式DAC+FPGA中中-高具有調(diào)諧能力模擬PLL中高難以調(diào)諧鎖相環(huán)是一種反饋環(huán)路，其組成部分為：一個(gè)相位比較器,一個(gè)除法器和一個(gè)壓控制振蕩器(VCO).相位比較器將基準(zhǔn)頻率與輸出頻率（通常是輸出頻率的N)分頻）進(jìn)行比較。相位比較器產(chǎn)生的誤差電壓用于調(diào)節(jié)VCO，從而輸出頻率。當(dāng)環(huán)路建立后，輸出將在頻率和/或相位上與參考頻率保持一種精確的關(guān)系。PLL長(zhǎng)期以來(lái)一直被認(rèn)為是在特定頻帶范圍內(nèi)要求高保真度和穩(wěn)定信號(hào)的低相位噪聲和高無(wú)雜散動(dòng)態(tài)范圍(SFDR)應(yīng)用的理想選擇。由于PLL無(wú)法精確、快速地調(diào)諧頻率輸出和波形，而且響應(yīng)較慢，這限制了它們對(duì)于快速跳頻和部分頻移鍵控和相移鍵控應(yīng)用的適用性。其他方案，包括集成DDS引擎的現(xiàn)場(chǎng)可編程門陣列(FPGAs)——配合現(xiàn)成DAC以合成輸出正弦波——雖然可以解決PLL的跳頻問(wèn)題，但也存在自身的缺陷。主要系統(tǒng)缺陷包括較高的工作和接口功耗要求、成本較高、尺寸較大，而且系統(tǒng)開發(fā)人員還須考慮額外的軟件、硬件和存儲(chǔ)器問(wèn)題。例如，利用現(xiàn)代FPGA中的DDS引擎選項(xiàng)，要產(chǎn)生動(dòng)態(tài)范圍為60dB的10MHz輸出信號(hào)，需要多達(dá)72kB的存儲(chǔ)器空間。另外，設(shè)計(jì)師需要接受并熟悉細(xì)微權(quán)衡和DDS內(nèi)核的架構(gòu)。從實(shí)用角度來(lái)看（見表2），得益于CMOS工藝和現(xiàn)代數(shù)字設(shè)計(jì)技術(shù)的快速發(fā)展以及DAC拓?fù)浣Y(jié)構(gòu)的改進(jìn)，DDS技術(shù)已經(jīng)能在廣泛的應(yīng)用中實(shí)現(xiàn)前所未有的低功耗、頻譜性能和成本水平。雖然純DDS產(chǎn)品不可能在性能和設(shè)計(jì)靈活性上達(dá)到高端DAC技術(shù)與FPGA相結(jié)合的水平，但DDS在尺寸、功耗、成本和簡(jiǎn)單性方面的優(yōu)勢(shì)使其成為許多應(yīng)用的首要選擇。表2.基準(zhǔn)分析小結(jié)——頻率產(chǎn)生技術(shù)(<50MHz)鎖相環(huán)DAC+FPGADDS頻譜性能高高中系統(tǒng)功耗要求高高低數(shù)字頻率調(diào)諧無(wú)是是調(diào)諧響應(yīng)時(shí)間高低低解決方案尺寸中高低波形靈活性低中高成本中高低設(shè)計(jì)重用中低高實(shí)現(xiàn)復(fù)雜度中高低同時(shí)需要指出，由于DDS器件從根本上來(lái)說(shuō)是用數(shù)字方法產(chǎn)生輸出波形，因此它可以簡(jiǎn)化一些解決方案的架構(gòu)，或者為對(duì)波形進(jìn)行數(shù)字化編程創(chuàng)造條件。盡管通常利用正弦波來(lái)解釋DDS的功能和工作原理，但利用現(xiàn)代DDSIC也可以輕松產(chǎn)生三角波或方波（時(shí)鐘）輸出，由此消除了前一種情況的查找表以及后一種情況的DAC的必要性，因?yàn)榧梢粋€(gè)簡(jiǎn)單而精確的比較器就夠了。DDS的性能與限制

圖像和包絡(luò)：Sin(x)xx滾降

DAC的實(shí)際輸出不是連續(xù)的正弦波，而是帶有正弦時(shí)間包絡(luò)的一系列脈沖。對(duì)應(yīng)的頻譜是一系列圖像和混疊信號(hào)。圖像沿sin(x)/x包絡(luò)分布（見圖3中的|幅度|曲線圖）。有必要進(jìn)行濾波，以抑制目標(biāo)頻帶之外的頻率，但是不能抑制通帶中出現(xiàn)的高階混疊（例如，因DAC非線性所致）。奈奎斯特準(zhǔn)則要求，每個(gè)周期至少需要兩個(gè)采樣點(diǎn)才能重建所需輸出波形。鏡像響應(yīng)產(chǎn)生于采樣輸出頻率中KfCLOCK×fOUT.在本例中，其中fCLOCK=2525MHz且fOUT=5MHz，第一和第二鏡頻出現(xiàn)在（見圖3）fCLOCK×fOUT,o即20MHz和30MHz。第三和第四鏡頻出現(xiàn)在45MHz和55MHz。注意，sin(x)/x零值出現(xiàn)在采樣頻率的倍數(shù)處。當(dāng)fOUT大于奈奎斯特帶寬(1/2fCLOCK),時(shí)，第一鏡頻將出現(xiàn)于奈奎斯特帶寬之內(nèi)，發(fā)生混疊（例如，15MHz的信號(hào)將向下混疊至10MHz）。無(wú)法用傳統(tǒng)的奈奎斯特抗混疊濾波器從輸出中濾掉混疊鏡頻。圖3.DDS中的Sin(x)/x滾降在典型的DDS應(yīng)用中，利用一個(gè)低通濾波器來(lái)抑制輸出頻譜中鏡頻響應(yīng)的影響。為了使低通濾波器的截止頻率要求保持于合理水平，并使濾波器設(shè)計(jì)保持簡(jiǎn)單，一種可行的做法是利用一個(gè)經(jīng)濟(jì)的低通輸出濾波器將fOUT帶寬限制在fCLOCK頻率的40%左右。任何給定鏡頻相對(duì)于基波的幅度可用sin(x)/x公式來(lái)計(jì)算。由于該函數(shù)隨頻率滾降，因此基本輸出的幅度