西電verilog課件第六章

第6章VerilogHDL組合電路設計1/15/20241MicroelectronicsSchoolXidianUniversity6.1組合邏輯電路的特點1/15/20242MicroelectronicsSchoolXidianUniversity6.1.1真值表1/15/20243MicroelectronicsSchoolXidianUniversity例6.1-1：設計一個4個裁判A，B，C，D的表決電路，其權重分別為3，2，1，1。當四個或四個以上的票數(shù)為同意時，輸出結果為“1”，否則輸出“0”。ABCDOUT00000000100010000110010000101001100011111000010011101011011111001110111110111111例6.1-2：設計一個4選1多路選擇器。Sel[1]Sel[0]out00data[0]01data[1]10data[2]11data[3]6.1.2卡諾圖簡化和邏輯函數(shù)表達式1/15/20244MicroelectronicsSchoolXidianUniversity

OUT=AB+AC+AD+BCD

6.1.3電路邏輯圖1/15/20245MicroelectronicsSchoolXidianUniversity6.2VerilogHDL組合電路設計方法1/15/20246MicroelectronicsSchoolXidianUniversity6.2.1真值表方式表決電路的真值表如表6.2-1所示。ABCDOUT00000000100010000110010000101001100011111000010011101011011111001110111110111111moduledecision(A,B,C,D,OUT);inputA,B,C,D;outputOUT;regOUT;always@(AorBorCorD)case({A,B,C,D})4'b0000:OUT<=0;4'b0001:OUT<=0;4'b0010:OUT<=0;4'b0011:OUT<=0;4'b0100:OUT<=0;4'b0101:OUT<=0;4'b0110:OUT<=0;4'b0111:OUT<=1;4'b1000:OUT<=0;4'b1001:OUT<=1;4'b1010:OUT<=1;4'b1011:OUT<=1;4'b1100:OUT<=1;4'b1101:OUT<=1;4'b1110:OUT<=1;4'b1111:OUT<=1;endcaseendmodule1/15/20247MicroelectronicsSchoolXidianUniversity例6.2-2：用真值表方式設計4選1數(shù)據(jù)選擇電路moduleMUX(out,data,sel);outputout;input[3:0]data;input[1:0]sel;regout;always@(dataorsel)case(sel)2'b00:out<=data[0];2'b01:out<=data[1];2'b10:out<=data[2];2'b11:out<=data[3];endcaseendmodule6.2.2邏輯表達式方式1/15/20248MicroelectronicsSchoolXidianUniversity例6.1-1的邏輯表達式為：OUT=AB+AC+AD+BCD，采用邏輯表達式方式設計moduledecision(A,B,C,D,OUT);inputA,B,C,D;outputOUT;assignOUT=(A&B)|(A&C)|(A&D)|((B&C)&D);endmodule例6.2-4：用邏輯表達方式設計4選1數(shù)據(jù)選擇器。

moduleMUX(out,data,sel);outputout;input[3:0]data;input[1:0]sel;wirew1,w2,w3,w4;assignw1=(~sel[1])&(~sel[0])&data[0];assignw2=(~sel[1])&sel[0]&data[1];assignw3=sel[1]&(~sel[0])&data[2];assignw4=sel[1]&sel[0]&data[3];assignout=w1|w2|w3|w4;endmodule6.2.3結構描述方式1/15/20249MicroelectronicsSchoolXidianUniversity例6.1-1的邏輯電路圖如圖6.1-4所示。該電路的VerilogHDL程序moduledecision(A,B,C,D,OUT);inputA,B,C,D;outputOUT;andU1(w1,A,B);andU2(w2,A,C);andU3(w3,A,D);andU4(w4,B,C,D);orU5(OUT,w1,w2,w3,w4);endmodule例6.2-6：用結構描述方式設計4選1數(shù)據(jù)選擇器。moduleMUX(out,data,sel);outputout;input[3:0]data;input[1:0]sel;wirew1,w2,w3,w4;not U1(w1,sel[1]);U2(w2,sel[0]);and U3(w3,w1,w2,data[0]);U4(w4,w1,sel[0],data[1]);U5(w5,sel[1],w2,data[2]);U6(w6,sel[1],sel[0],data[3]);or U7(out,w3,w4,w5,w6);endmodule6.2.4抽象描述方式1/15/202410MicroelectronicsSchoolXidianUniversity例6.1-1采用抽象方式時，將四個輸入變量相加，當相加器的結果大于等于4時表示判決成功，即表示投票成功。

moduledecision(A,B,C,D,OUT);inputA,B,C,D;outputOUT;regOUT;wire[2:0]SUM;assignSUM=3*A+2*B+C+D;assignOUT=(SUM>4)?1:0;endmodulemoduledecision_tb;regA,B,C,D;wireOUT;decisionU0(.A(A),.B(B),.C(C),.D(D),.OUT(OUT));initialbeginA=1'b0;B=1'b1;C=1'b0;D=1'b0;#100A=1'b1;D=1'b1;#100A=1'b0;C=1'b1;#100B=1'b0;D=1'b0;#100A=1'b1;#100C=1'b0;D=1'b1;#100A=1'b0;D=1'b0;#100C=1'b1;D=1'b1;#100A=1'b1;B=1'b1;#200$finish;endendmodule1/15/202411MicroelectronicsSchoolXidianUniversity例6.2-8：用抽象描述方式設計4選1數(shù)據(jù)選擇器。moduleMUX(data,out,sel);input[3:0]data;input[1:0]sel;outputout;wireout;wire[1:0]w1;assignw1=sel[0]?{data[3],data[1]}:{data[2],data[0]};assignout=sel[1]?{w1[1]}:{w1[0]};endmodule6.3數(shù)字加法器1/15/202412MicroelectronicsSchoolXidianUniversity6.3.12輸入1bit信號全加器。ABC_INSUMC_OUT0000000110010100110110010101011100111111SUM=A⊕B⊕C_IN

1/15/202413MicroelectronicsSchoolXidianUniversity例6.3-1：用連續(xù)賦值語句設計2輸入1bit全加器電路。modulefulladder_1(SUM,C_OUT,A,B,C_IN);input A,B,C_IN;output SUM,C_OUT;assign SUM=(A^B)^C_IN;assign C_OUT=(A&B)|((A^B)&C_IN);//functionofoutputendmodule例6.3-2：用行為描述設計2輸入1bit全加器電路。moduleadder_1(SUM,C_OUT,A,B,C_IN);output SUM,C_OUT;input A,B,C_IN;assign {C_OUT,SUM}=A+B+C_IN;endmodulemoduleadder_1_tb;regA,B,C_IN;wireSUM,C_OUT;adder_1U1(.A(A),.B(B),.C_IN(C_IN),.SUM(SUM),.C_OUT(C_OUT));initialbeginA=1'b0;B=1'b0;C_IN=1'b0;#100A=1'b1;B=1'b1;#100A=1'b0;B=1'b1;#100C_IN=1'b1;#100A=1'b1;#100B=1'b0;#100C_IN=1'b0;#200$finish;endendmodule1/15/202414MicroelectronicsSchoolXidianUniversity1/15/202415MicroelectronicsSchoolXidianUniversity例6.3-3：設計一個2輸入8bits加法器moduleadder_8(SUM,C_OUT,A,B,C_IN);output[7:0] SUM;output C_OUT;input[7:0] A,B;input C_IN;assign{C_OUT,SUM}=A+B+C_IN;endmodulemoduleadder_8_tb;reg[7:0]A,B;regC_IN;wire[7:0]SUM;wireC_OUT;adder_8U2(.A(A),.B(B),.C_IN(C_IN),.SUM(SUM),.C_OUT(C_OUT));initialbeginA=8'b00000000;B=8'b00000000;C_IN=1'b0;#100A=8'b00000011;B=8'b00111000;#100A=8'b00011010;B=8'b11100110;#100C_IN=1'b1;#100A=8'b00001001;#100C_IN=1'b0;#100A=8'b11000100;B=8'b01011001;#200$finish;endendmodule1/15/202416MicroelectronicsSchoolXidianUniversity6.3.24位超前進位加法器

1/15/202417MicroelectronicsSchoolXidianUniversity1/15/202418MicroelectronicsSchoolXidianUniversitymodulefastaddder_4(sum,c_out,a,b,c_in);input[3:0] a,b; //theotherofaddnumberinput c_in; //carryinfrombeforeleveloutput[3:0] sum; //theaddoftwoinputoutput c_out; //carryouttonextlevelwire[4:0] g,p,c; //wirebetweeneveryc_outandc_inassignc[0]=c_in;assignp=a^b;assigng=a&b;assignc[1]=g[0]|(p[0]&c[0]);assignc[2]=g[1]|(p[1]&(g[0]|(p[0]&c[0])));assignc[3]=g[2]|(p[2]&(g[1]|(p[1]&(g[0]|(p[0]&c[0])))));assignc[4]=g[3]|(p[3]&(g[2]|(p[2]&(g[1]|(p[1]&(g[0]|(p[0]&c[0])))))));assignsum=p^c[3:0];assignc_out=c[4];endmodule1/15/202419MicroelectronicsSchoolXidianUniversitymodulefastadder_4_tb;reg[3:0]a,b;regc_in;wire[3:0]sum;wirec_out;fastaddder_4U3(.a(a),.b(b),.c_in(c_in),.sum(sum),.c_out(c_out));initialbegina=4'b0001;b=4'b0101;c_in=1'b0;#100a=4'b0001;b=4'b0111;#100a=4'b0111;b=4'b1100;#100b=4'b1111;c_in=1'b1;#100a=4'b1101;b=4'b0100;#100a=4'b0000;b=4'b1001;c_in=1'b0;#100a=4'b1000;b=4'b0110;#200$finish;endendmodule1/15/202420MicroelectronicsSchoolXidianUniversity6.4數(shù)據(jù)比較器1/15/202421MicroelectronicsSchoolXidianUniversity例6.4-1：1位數(shù)據(jù)比較器。

1/15/202422MicroelectronicsSchoolXidianUniversitymodulecomp_1b(a,b,agb,aeb,alb);inputa,b;outputagb,aeb,alb;wireagb,aeb,alb;assignagb=a&(~b);assignaeb=a^~b;assignalb=(~a)&b;endmodulemodulecomp_1b_tb;rega,b;wireagb,aeb,alb;comp_1bU1(.a(a),.b(b),.agb(agb),.aeb(aeb),.alb(alb));initialbegina=1'b1;b=1'b1;#100a=1'b0;#100a=1'b1;b=1'b0;#100a=1'b0;#100b=1'b1;#200$finish;endendmodule1/15/202423MicroelectronicsSchoolXidianUniversity例6.4-3：設計一個8位數(shù)據(jù)比較器。輸入輸出a7b7a6b6a5b5a4b4a3b3a2b2a1b1a0b0agbaebalba7>b7xxxxxxx100a7<b7xxxxxxx001a7=b7a6>b6xxxxxx100a7=b7a6<b6xxxxxx001a7=b7a6=b6a5>b5xxxxx100a7=b7a6=b6a5<b5xxxxx001a7=b7a6=b6a5=b5a4>b4xxxx100a7=b7a6=b6a5=b5a4<b4xxxx001a7=b7a6=b6a5=b5a4=b4a3>b3xxx100a7=b7a6=b6a5=b5a4=b4a3<b3xxx001a7=b7a6=b6a5=b5a4=b4a3=b3a2>b2xx100a7=b7a6=b6a5=b5a4=b4a3=b3a2<b2xx001a7=b7a6=b6a5=b5a4=b4a3=b3a2=b2a1>b1x100a7=b7a6=b6a5=b5a4=b4a3=b3a2=b2a1<b1x001a7=b7a6=b6a5=b5a4=b4a3=b3a2=b2a1=b1a0>b0100a7=b7a6=b6a5=b5a4=b4a3=b3a2=b2a1=b1a0<b0001a7=b7a6=b6a5=b5a4=b4a3=b3a2=b2a1=b1a0=b00101/15/202424MicroelectronicsSchoolXidianUniversitymodulecomp_8b(a,b,agb,aeb,alb);parameterw=8;input[w-1:0]a,b;outputagb,aeb,alb;regagb,aeb,alb;always@(aorb)if(a>b){agb,aeb,alb}=3'b100;elseif(a<b){agb,aeb,alb}=3'b001;else{agb,aeb,alb}=3'b010;endmodulemodulecomp_8b_tb;reg[7:0]a,b;wireagb,aeb,alb;comp_8bU3(.a(a),.b(b),.agb(agb),.aeb(aeb),.alb(alb));initialbegina=8'b00110101;b=8'b00110100;#100a=8'b00110011;b=8'b00110011;#100a=8'b00110011;b=8'b10110011;#100a=8'b11110011;b=8'b01110011;#100a=8'b01100110;b=8'b01100110;#100a=8'b00110000;b=8'b11000011;#100a=8'b00111111;b=8'b00000000;#200$finish;endendmodule6.5數(shù)據(jù)選擇器1/15/202425MicroelectronicsSchoolXidianUniversity6.5.12選1數(shù)據(jù)選擇器例6.5-1：采用“？”操作符設計一個2選1選擇器

modulemux2to1_tb;reg[1:0]d_in;regsel;wired_out;mux2to1U2(.d_in(d_in),.d_out(d_out),.sel(sel));initialbegind_in=2'b10;sel=1'b0;#100sel=1'b1;#100d_in=2'b11;#100sel=1'b0;#100d_in=2'b01;#100sel=1'b1;#100d_in=00;#100sel=1'b0;#200$finish;endendmodulemodulemux2to1(d_in,d_out,sel);input[1:0]d_in;inputsel;outputd_out;wired_out;assignd_out=sel?d_in[1]:d_in[0];endmodule1/15/202426MicroelectronicsSchoolXidianUniversity例6.5-2：使用“if-else”語句設計一個2選1數(shù)據(jù)選擇器modulemux2to1_1(d_in,d_out,sel);input[1:0]d_in;inputsel;outputd_out;regd_out;always@(d_inorsel)beginif(sel)d_out=d_in[1];elsed_out=d_in[0];endendmodule1/15/202427MicroelectronicsSchoolXidianUniversity6.5.24選1數(shù)據(jù)選擇器sel[1]sel[0]d_out00d_in[0]01d_in[1]10d_in[2]11d_in[3]表6.5-1

4選1數(shù)據(jù)選擇器真值表

1/15/202428MicroelectronicsSchoolXidianUniversitymodulemux4to1_2(d_in,d_out,sel);input[3:0]d_in;input[1:0]sel;outputd_out;wired_out;wire[1:0]w1;assignw1=sel[0]?{d_in[3],d_in[1]}:{d_in[2],d_in[0]};assignd_out=sel[1]?w1[1]:w1[0];endmodulemodulemux4to1_2_tb;reg[3:0]d_in;reg[1:0]sel;wired_out;mux4to1_2U1(.d_in(d_in),.d_out(d_out),.sel(sel));initialbegind_in=4'b1010;sel=2'b00;#100sel=2'b01;#100sel=2'b11;#100sel=2'b10;#100d_in=4'b1100;#100sel=2'b11;#100sel=2'b00;#100sel=2'b01;#200$finish;endendmodule1/15/202429MicroelectronicsSchoolXidianUniversity1/15/202430MicroelectronicsSchoolXidianUniversitymodulemux4to1_1(d_in,d_out,sel);input[3:0]d_in;input[1:0]sel;outputd_out;regd_out;always@(d_inorsel)beginif(sel[1]==1)beginif(sel[0]==1)d_out=d_in[3];elsed_out=d_in[2];endelsebeginif(sel[0]==1)d_out=d_in[1];elsed_out=d_in[0];endendendmodulemodulemux4to1(d_in,d_out,sel);input[3:0]d_in;input[1:0]sel;outputd_out;regd_out;always@(d_inorsel)

case(sel)2'b00:d_out<=d_in[0];2'b01:d_out<=d_in[1];2'b10:d_out<=d_in[2];2'b11:d_out<=d_in[3];default:d_out<=1'b0;endcaseendmodule6.6數(shù)據(jù)分配器1/15/202431MicroelectronicsSchoolXidianUniversity6.6.11-4數(shù)據(jù)分配器輸入輸出ensel1sel0dout3dout2dout1dout00xx0000100000din10100din01100din00111din0001/15/202432MicroelectronicsSchoolXidianUniversitymoduledmux_4(en,din,dout,sel);inputen,din;input[1:0]sel;output[3:0]dout;reg[3:0]dout;always@(enorselordin)if(!en)dout=4'b0;elsecase(sel)2'b00:dout[0]=din;2'b01:dout[1]=din;2'b10:dout[2]=din;2'b11:dout[3]=din;endcaseendmodulemoduledmux_4_tb;regen,din;reg[1:0]sel;wire[3:0]dout;dmux_4U1(.din(din),.en(en),.sel(sel),.dout(dout));initialbeginen=1'b0;din=1'b1;sel=2'b00;#100en=1'b1;#100sel=2'b01;#100sel=2'b11;#100din=1'b0;sel=2'b01;#100din=1'b1;#100sel=2'b11;#200$finish;endendmodule6.7數(shù)據(jù)編碼器1/15/202433MicroelectronicsSchoolXidianUniversity6.7.1BCD編碼器表6.7-18421BCD真值表輸入DCBA0（Y0）00001（Y1）00012（Y2）00103（Y3）00114（Y4）01005（Y5）01016（Y6）01107（Y7）01118（Y8）10009（Y9）10011/15/202434MicroelectronicsSchoolXidianUniversitymoduleBCD8421(d_in,d_out);input[8:0]d_in;output[3:0]d_out;reg[3:0]d_out;always@(d_in)case(d_in)9'b000000000:d_out=4'b0000;9'b000000001:d_out=4'b0001;9'b000000010:d_out=4'b0010;9'b000000100:d_out=4'b0011;9'b000001000:d_out=4'b0100;9'b000010000:d_out=4'b0101;9'b000100000:d_out=4'b0110;9'b001000000:d_out=4'b0111;9'b010000000:d_out=4'b1000;9'b100000000:d_out=4'b1001;defaultd_out=4'b0000;endcaseendmodulemoduleBCD8421_tb;reg[8:0]d_in;wire[3:0]d_out;BCD8421U0(.d_in(d_in),.d_out(d_out));initialbegind_in=9'b010000000;#100d_in=9'b000000001;#100d_in=9'b000000010;#100d_in=9'b000000100;#100d_in=9'b000001000;#100d_in=9'b000010000;#100d_in=9'b100001000;#100d_in=9'b000100000;#100d_in=9'b001000000;#100d_in=9'b000000000;#100d_in=9'b100000000;#200$finish;endendmodule6.7.28線-3線編碼器1/15/202435MicroelectronicsSchoolXidianUniversity表6.7-28線-3線編碼器真值表輸入輸出1000000000001000000001001000000100001000001100001000100000001001011/15/202436MicroelectronicsSchoolXidianUniversitymodulecode8_3(din,dout);input[7:0]din;output[2:0]dout;reg[3:0]dout;always@(din)case(din)8'b00000001:dout=3'b000;8'b00000010:dout=3'b001;8'b00000100:dout=3'b010;8'b00001000:dout=3'b011;8'b00010000:dout=3'b100;8'b00100000:dout=3'b101;8'b01000000:dout=3'b110;8'b10000000:dout=3'b111;default:dout=3'b000;endcaseendmodulemodulecode8_3_tb;reg[7:0]din;wire[2:0]dout;code8_3U1(.din(din),.dout(dout));initialbegindin=8'b00001000;#100din=8'b00000001;#100din=8'b01000000;#100din=8'b00000000;#100din=8'b00010000;#100din=8'b00000000;#100din=8'b00100000;#100din=8'b01000000;#100din=8'b10000000;#100din=8'b11000000;#200$finish;endendmodule6.7.38線-3線優(yōu)先編碼器1/15/202437MicroelectronicsSchoolXidianUniversity表6.7-38線-3線優(yōu)先編碼器真值表輸入輸出enysyex1xxxxxxxx1111100xxxxxxx00010010xxxxxx001100110xxxxx0101001110xxxx01110011110xxx100100111110xx1011001111110x1101001111111011110011111111111011/15/202438MicroelectronicsSchoolXidianUniversitymodulecode8_3_p(din,dout,en,ys,yex);input[7:0]din;inputen;outputys,yex;output[2:0]dout;reg[2:0]dout;regys,yex;always@(dinoren)if(en){dout,ys,yex}={3'b111,1'b1,1'b1};elsebegincasex(din)8'b0???????:{dout,ys,yex}={3'b000,1'b1,1'b0};8'b10??????:{dout,ys,yex}={3'b001,1'b1,1'b0};8'b110?????:{dout,ys,yex}={3'b010,1'b1,1'b0};8'b1110????:{dout,ys,yex}={3'b011,1'b1,1'b0};8'b11110???:{dout,ys,yex}={3'b100,1'b1,1'b0};8'b111110??:{dout,ys,yex}={3'b101,1'b1,1'b0};8'b1111110?:{dout,ys,yex}={3'b110,1'b1,1'b0};8'b11111110:{dout,ys,yex}={3'b111,1'b1,1'b0};8'b11111111:{dout,ys,yex}={3'b111,1'b0,1'b1};endcaseendendmodulemodulecode8_3_p_tb;reg[7:0]din;regen;wireys,yex;wire[2:0]dout;code8_3_pU2(.din(din),.dout(dout),.en(en),.ys(ys),.yex(yex));initialbegindin=8'b00001100;en=1'b1;#100en=1'b0;din=8'b10000001;#100din=8'b11000010;#100din=8'b11000100;#100din=8'b11101000;#100din=8'b11110000;#100din=8'b11111010;#100din=8'b11111100;#100din=8'b11111110;#100din=8'b11111111;#200$finish;endendmodule6.7.4余3編碼1/15/202439MicroelectronicsSchoolXidianUniversitymodulecode_yu3(d_in,d_out);input[3:0]d_in;output[3:0]d_out;assignd_out=d_in+4'b0011;endmodulemodulecode_yu3_tb;reg[3:0]d_in;wire[3:0]d_out;code_yu3U4(.d_in(d_in),.d_out(d_out));initialbegind_in=4'b0001;#100d_in=4'b0101;#100d_in=4'b0100;#100d_in=4'b1001;#100d_in=4'b0111;#100d_in=4'b0000;#200$finish;endendmodule表6.7-4余三碼的真值表與8421BCD碼的對比十進制數(shù)8421BCD碼余3碼0000000111000101002001001013001101104010001115010110006011010017011110108100010119100111006.8數(shù)據(jù)譯碼器1/15/202440MicroelectronicsSchoolXidianUniversity6.8.13線-8線譯碼器表6.8-23線-8線譯碼器真值表endindout0xxx0000_000010000000_000110010000_001010100000_010010110000_100011000001_000011010010_000011100100_000011111000_0000

1/15/202441MicroelectronicsSchoolXidianUniversitymoduledecode3_8(en,din,dout);input[2:0]din;inputen;output[7:0]dout;reg[7:0]dout;always@(enordin)if(!en)dout=8'b0;elsecase(din)3'b000:dout=8'b00000001;3'b001:dout=8'b00000010;3'b010:dout=8'b00000100;3'b011:dout=8'b00001000;3'b100:dout=8'b00010000;3'b101:dout=8'b00100000;3'b110:dout=8'b01000000;3'b111:dout=8'b10000000;endcaseendmodulemoduledecode3_8_tb;reg[2:0]din;regen;wire[7:0]dout;decode3_8U2(.din(din),.en(en),.dout(dout));initialbeginen=1'b1;din=3'b000;#100din=3'b001;#100din=3'b011;#100din=3'b110;#100en=1'b0;din=3'b111;#100en=1'b1;#100din=3'b010;#100din=3'b100;#200$finish;endendmodule6.8.28421BCD轉二進制譯碼1/15/202442MicroelectronicsSchoolXidianUniversity表6.8-3BCD譯碼器真值表d_ind_out000000000000010001000000001000100000000100001100000010000100000001000001010000100000011000010000000111001000000010000100000000100110000000001010000000000010110000000000110000000000001101000000000011100000000000111100000000001/15/202443MicroelectronicsSchoolXidianUniversitymoduledecode_BCD(d_in,d_out);input[3:0]d_in;output[9:0]d_out;reg[9:0]d_out;always@(d_in)begincase(d_in)4'b0000:d_out=10'b0000000001;4'b0001:d_out=10'b0000000010;4'b0010:d_out=10'b0000000100;4'b0011:d_out=10'b0000001000;4'b0100:d_out=10'b0000010000;4'b0101:d_out=10'b0000100000;4'b0110:d_out=10'b0001000000;4'b0111:d_out=10'b0010000000;4'b1000:d_out=10'b0100000000;4'b1001:d_out=10'b1000000000;default:d_out=10'b0;endcaseendendmodulemoduledecode_BCD_tb;