第七章 行為級(jí)建模雙語版

（1）2024/3/12HardwareDescriptionLanguages

硬件描述語言

青島科技大學(xué)信息學(xué)院宋廷強(qiáng)songtq@163.com

2024/3/1227BehavioralModeling

行為級(jí)建模（3）2024/3/12Main

contents本章學(xué)習(xí)目標(biāo)Explainthesignificanceofstructuredproceduresalwaysandinitialinbehavioralmodeling.掌握結(jié)構(gòu)化過程always和initial在行為級(jí)建模中的方法。Defineblockingandnonblockingproceduralassignments.掌握阻塞（blocking）和非阻塞（non-blocking）過程性賦值語句的定義方法。Understanddelay-basedtimingcontrolmechanisminbehavioralmodeling.Useregulardelays,intra-assignmentdelays,andzerodelays.理解行為級(jí)建模中基于延遲的時(shí)序控制機(jī)制。學(xué)習(xí)使用一般延遲、內(nèi)嵌賦值延遲和零延遲。Describeevent-basedtimingcontrolmechanisminbehavioralmodeling.Useregulareventcontrol,namedeventcontrol,andeventORcontrol.理解行為級(jí)建模中基于事件的時(shí)序控制機(jī)制。學(xué)習(xí)使用一般事件控制、命名事件控制和事件OR（或）控制。（4）2024/3/12Uselevel-sensitivetimingcontrolmechanisminbehavioralmodeling.理解行為級(jí)建模中使用電平敏感的時(shí)序控制機(jī)制。Explainconditionalstatementsusingifandelse.掌握使用if和else解釋條件語句。Describemultiwaybranching,usingcase,casex,andcasezstatements.掌握使用case，casex和casez語句講解多路分支。Understandloopingstatementssuchaswhile,for,repeat,andforever.掌握使用while，for，repeat和forever等循環(huán)語句。Definesequentialandparallelblocks.掌握定義順序塊和并行塊語句。Understandnamingofblocksanddisablingofnamedblocks.理解命名塊和命名塊的禁用。Usebehavioralmodelingstatementsinpracticalexamples.在設(shè)計(jì)實(shí)例中進(jìn)行行為級(jí)建模。Verilogprovidesdesignerstheabilitytodescribedesignfunctionalityinanalgorithmicmanner.Inotherwords,thedesignerdescribesthebehaviorofthecircuit.Thus,behavioralmodelingrepresentsthecircuitataveryhighlevelofabstraction.提供的Verilog設(shè)計(jì)人員描述一個(gè)算法的方式設(shè)計(jì)功能的能力。換言之，設(shè)計(jì)者描述的電路的行為。因此，行為建模表示電路的抽象一個(gè)非常高的水平。DesignatthislevelresemblesCprogrammingmorethanitresemblesdigitalcircuitdesign.在這個(gè)級(jí)別的設(shè)計(jì)，類似于C語言編程也類似于數(shù)字電路設(shè)計(jì)。（5）2024/3/12（6）2024/3/12BehavioralVerilogconstructsaresimilartoClanguageconstructsinmanyways.Verilogisrichinbehavioralconstructsthatprovidethedesignerwithagreatamountofflexibility.行為級(jí)Verilog結(jié)構(gòu)體在許多方面似于C語言語法結(jié)構(gòu)。Verilog的豐富的行為結(jié)構(gòu)為設(shè)計(jì)人員提供極大的靈活性。7.1StructuredProceduresTherearetwostructuredprocedurestatementsinVerilog:alwaysandinitial.Thesestatementsarethetwomostbasicstatementsinbehavioralmodeling.Allotherbehavioralstatementscanappearonlyinsidethesestructuredprocedurestatements.在Verilog中有兩種結(jié)構(gòu)化的過程語句：initial語句和always語句，它們是行為級(jí)建模的兩種基本語句。其他所有的行為語句只能出現(xiàn)在這兩種結(jié)構(gòu)化過程語句里。（7）2024/3/12（8）2024/3/12VerilogisaconcurrentprogramminglanguageunliketheCprogramminglanguage,whichissequentialinnature.ActivityflowsinVerilogruninparallelratherthaninsequence.EachalwaysandinitialstatementrepresentsaseparateactivityflowinVerilog.Eachactivityflowstartsatsimulationtime0.Thestatementsalwaysandinitialcannotbenested.Thefundamentaldifferencebetweenthetwostatementsisexplainedinthefollowingsections.與C語言不同，Verilog在本質(zhì)上是并發(fā)而非順序的。Verilog中的各個(gè)執(zhí)行流程（進(jìn)程）并發(fā)執(zhí)行，而不是順序執(zhí)行的。每個(gè)initial語句和always語句代表一個(gè)獨(dú)立的執(zhí)行過程，每個(gè)執(zhí)行過程從仿真時(shí)間0開始執(zhí)行，并且這兩種語句不能嵌套使用。7.1.1initialStatementAllstatementsinsideaninitialstatementconstituteaninitialblock.所有在initial語句內(nèi)的語句構(gòu)成了一個(gè)initial塊。

Aninitialblockstartsattime0,executesexactlyonceduringasimulation,andthendoesnotexecuteagain.initial塊從仿真0時(shí)刻開始執(zhí)行，在整個(gè)仿真過程中只執(zhí)行一次。Iftherearemultipleinitialblocks,eachblockstartstoexecuteconcurrentlyattime0.如果一個(gè)模塊中包括了若干個(gè)initial塊，則這些initial塊從仿真0時(shí)刻開始并發(fā)執(zhí)行，且每個(gè)塊的執(zhí)行是各自獨(dú)立的。（9）2024/3/12（10）2024/3/12Eachblockfinishesexecutionindependentlyofotherblocks.Multiplebehavioralstatementsmustbegrouped,typicallyusingthekeywordsbeginandend.Ifthereisonlyonebehavioralstatement,groupingisnotnecessary.如果在塊內(nèi)包含了多條行為語句，那么需要將這些語句組成一組，一般是使用關(guān)鍵字begin和end將它們組合為一個(gè)塊語句；如果塊內(nèi)只有一條語句，則不必使用begin和end。Thisissimilartothebegin-endblocksinPascalprogramminglanguageorthe{}groupingintheCprogramminglanguage.Example7-1illustratestheuseoftheinitialstatement.這一點(diǎn)類似于Pascal語言中的begin和end塊或C語言中的{}語句塊。例7.1給出了使用initial語句的例子。Example7-1initialStatement（11）2024/3/12Theinitialblocksaretypicallyusedforinitialization,monitoring,waveformsandotherprocessesthatmustbeexecutedonlyonceduringtheentiresimulationrun.Thefollowingsubsectionsdiscussionhowtoinitializevaluesusingalternateshorthandsyntax.Theuseofsuchshorthandsyntaxhasthesameeffectasaninitialblockcombinedwithavariabledeclaration.由于initial塊語句在整個(gè)仿真期間只能執(zhí)行一次，因此它一般被用于初始化，信號(hào)監(jiān)視，生成仿真波形等目的。在下面的小結(jié)中，我們討論如何使用另一種簡潔的語法來進(jìn)行初始化。這種方法與initial語句和變量聲明的組合具有相同的效果。（12）2024/3/12timestatementexecuted0m=1'b0;5a=1'b1;10x=1'b0;30b=1'b0;35y=1'b1;50$finish;CombinedVariableDeclarationandInitialization在變量聲明的同時(shí)進(jìn)行初始化（13）2024/3/12Example7-3CombinedPort/DataDeclarationandVariableInitializationmoduleadder(sum,co,a,b,ci);outputreg[7:0]sum=0;//Initialize8bitoutputsumoutputregco=0;//Initialize1bitoutputcoinput[7:0]a,b;inputci;----endmoduleCombinedANSICStylePortDeclarationandInitializationANSIC風(fēng)格端口聲明的聲明初始化（14）2024/3/12moduleadder(outputreg[7:0]sum=0,//Initialize8bitoutputoutputregco=0,//Initialize1bitoutputcoinput[7:0]a,b,inputci);----endmoduleExample7-4CombinedANSICPortDeclarationandVariableInitialization7.1.2alwaysStatementAllbehavioralstatementsinsideanalwaysstatementconstituteanalwaysblock.Thealwaysstatementstartsattime0andexecutesthestatementsinthealwaysblockcontinuouslyinaloopingfashion.Thisstatementisusedtomodelablockofactivitythatisrepeatedcontinuouslyinadigitalcircuit.Anexampleisaclockgeneratormodulethattogglestheclocksignaleveryhalfcycle.Inrealcircuits,theclockgeneratorisactivefromtime0toaslongasthecircuitispoweredon.Example7-5illustratesonemethodtomodelaclockgeneratorinVerilog.always語句包括的所有行為語句構(gòu)成了一個(gè)always語句塊。該always語句塊從仿真0時(shí)刻開始順序執(zhí)行其中的行為語句；在最后一條執(zhí)行完成后，再次開始執(zhí)行其中的第一條語句，如此循環(huán)往復(fù)，直至整個(gè)仿真結(jié)束。（15）2024/3/12（16）2024/3/12always語句通常用于對(duì)數(shù)字電路中一組反復(fù)執(zhí)行的活動(dòng)進(jìn)行建模。例如時(shí)鐘信號(hào)發(fā)生器，每半個(gè)時(shí)鐘周期時(shí)鐘信號(hào)翻轉(zhuǎn)一次。在現(xiàn)實(shí)電路中只要電源接通，時(shí)鐘信號(hào)發(fā)生器從時(shí)刻0就有效，一直工作下去。例7.5說明了用Verilog語言為時(shí)鐘發(fā)生器建立模型的一種方法。Example7-5alwaysStatementmoduleclock_gen(outputregclock);//Initializeclockattimezeroinitialclock=1'b0;//Toggleclockeveryhalf-cycle(timeperiod=20)always#10clock=~clock;initial#1000$finish;endmodule（17）2024/3/12InExample7-5,thealwaysstatementstartsattime0andexecutesthestatementclock=~clockevery10timeunits.在例7.5中，always語句從仿真0時(shí)刻起，每隔10個(gè)時(shí)間單位執(zhí)行一次對(duì)clock信號(hào)的取反操作。Noticethattheinitializationofclockhastobedoneinsideaseparateinitialstatement.Ifweputtheinitializationofclockinsidethealwaysblock,clockwillbeinitializedeverytimethealwaysisentered.Also,thesimulationmustbehaltedinsideaninitialstatement.Ifthereisno$stopor$finishstatementtohaltthesimulation,theclockgeneratorwillrunforever.注意，在這個(gè)例子中，clock信號(hào)是在initial語句中進(jìn)行的初始化的；如果我們將初始化語句放在always塊內(nèi)，那么always語句的每次執(zhí)行都會(huì)導(dǎo)致clock被初始化，而不是像initial那樣只執(zhí)行一次。如果我們沒有使用（$finish）或者($stop)語句停止仿真，那么這個(gè)時(shí)鐘發(fā)生器將一直初始化。（18）2024/3/12（19）2024/3/12Cprogrammersmightdrawananalogybetweenthealwaysblockandaninfiniteloop.Buthardwaredesignerstendtoviewitasacontinuouslyrepeatedactivityinadigitalcircuitstartingfrompoweron.Theactivityisstoppedonlybypoweroff($finish)orbyaninterrupt($stop).從C語言角度來看，always類似于一個(gè)無限循環(huán)；而從硬件設(shè)計(jì)角度看，always反映了硬件電路通電之后連續(xù)地反復(fù)執(zhí)行的特點(diǎn)。這種執(zhí)行職能通過斷電（$finish）或者中斷($stop)來停止7.2ProceduralAssignmentsProceduralassignmentsupdatevaluesofreg,integer,real,ortimevariables.Thevalueplacedonavariablewillremainunchangeduntilanotherproceduralassignmentupdatesthevariablewithadifferentvalue.TheseareunlikecontinuousassignmentsdiscussedinChapter6,DataflowModeling,whereoneassignmentstatementcancausethevalueoftheright-hand-sideexpressiontobecontinuouslyplacedontotheleft-hand-sidenet.Thesyntaxforthesimplestformofproceduralassignmentisshownbelow.過程賦值語句的更新對(duì)象是寄存器、整數(shù)、實(shí)數(shù)或時(shí)間變量。這些類型的變量在被賦值后，其值將保持不變，直到被其他過程賦值語句賦予新值。這與連續(xù)賦值語句是不同的，連續(xù)賦值語句總是處于活動(dòng)狀態(tài)，任意一個(gè)操作數(shù)的變化會(huì)導(dǎo)致表達(dá)式的重新計(jì)算并且重新賦值。但是過程賦值語句只有在執(zhí)行到得時(shí)候才起作用。過程賦值語句最簡單的語法形式如下：assignment::=variable_lvalue=[delay_or_event_control]expression（20）2024/3/12Theleft-handsideofaproceduralassignment<lvalue>canbeoneofthefollowing:過程賦值語句的左側(cè)值可以是：Areg,integer,real,ortimeregistervariableoramemoryelementreg，整型數(shù)、實(shí)型數(shù)、時(shí)間寄存器變量或存儲(chǔ)器單元。Abitselectofthesevariables(e.g.,addr[0])上述各種類型的位選（例如，addr[0]）。Apartselectofthesevariables(e.g.,addr[31:16])上述各種類型的域選（例如，addr[31:16]）。Aco上面三種類型的拼接。ncatenationofanyoftheabove（21）2024/3/12Theright-handsidecanbeanyexpressionthatevaluatestoavalue.Inbehavioralmodeling,alloperatorslistedinTable6-1onpage96canbeusedinbehavioralexpressions.賦值符的右側(cè)可以是任意類型的合法表達(dá)式，在表達(dá)式中可以使用表6.1列出的所有操作符。Therearetwotypesofproceduralassignmentstatements:blockingandnonblocking.Verilog包括兩種類型的過程賦值語句：阻塞賦值和非阻塞賦值語句（22）2024/3/127.2.1BlockingAssignmentsBlockingassignmentstatementsareexecutedintheordertheyarespecifiedinasequentialblock.Ablockingassignmentwillnotblockexecutionofstatementsthatfollowinaparallelblock.BothparallelandsequentialblocksarediscussedinSection7.7,SequentialandParallelBlocks.The=operatorisusedtospecifyblockingassignments.串行塊中的阻塞賦值語句按順序執(zhí)行，它不會(huì)阻塞其后并行塊中語句的執(zhí)行。我們將在7.7節(jié)中對(duì)串塊和并行塊進(jìn)行討論。阻塞賦值語句使用“=”作為賦值符。（23）2024/3/12Example7-6BlockingStatementsregx,y,z;reg[15:0]reg_a,reg_b;integercount;//Allbehavioralstatementsmustbeinsideaninitialoralwaysblockinitialbeginx=0;y=1;z=1;//Scalarassignmentscount=0;//Assignmenttointegervariablesreg_a=16'b0;reg_b=reg_a;//initializevectors#15reg_a[2]=1'b1;//Bitselectassignmentwithdelay#10reg_b[15:13]={x,y,z}//Assignresultofconcatenationto//partselectofavectorcount=count+1;//Assignmenttoaninteger(increment)end（24）2024/3/12InExample7-6,thestatementy=1isexecutedonlyafterx=0isexecuted.Thebehaviorinaparticularblockissequentialinabegin-endblockifblockingstatementsareused,becausethestatementscanexecuteonlyinsequence.Thestatementcount=count+1isexecutedlast.Thesimulationtimesatwhichthestatementsareexecutedareasfollows:在例7.6中，只有在語句x=0執(zhí)行完成后,才會(huì)執(zhí)行y=1，而語句count=count+1按順序在最后執(zhí)行。由于阻塞賦值語句是按順序執(zhí)行的，因此如果在一個(gè)begin-end塊中使用了阻塞賦值語句，那么這個(gè)塊語句表現(xiàn)的是串行行為。在例7.6中，begin-end塊中各條語句執(zhí)行的時(shí)間為：Allstatementsx=0throughreg_b=reg_aareexecutedattime0X=0到仿真0時(shí)刻執(zhí)行Statementreg_a[2]=0attime=15Statementreg_b[15:13]={x,y,z}attime=25Statementcount=count+1attime=25Sincethereisadelayof15and10intheprecedingstatements,count=count+1willbeexecutedattime=25units（25）2024/3/12（26）2024/3/12Allstatementsx=0throughreg_b=reg_aareexecutedattime0X=0到仿真0時(shí)刻執(zhí)行Statementreg_a[2]=0attime=15reg_a[2]=0仿真時(shí)刻15執(zhí)行Statementreg_b[15:13]={x,y,z}attime=25仿真時(shí)刻25執(zhí)行Statementcount=count+1attime=25count=count+1仿真時(shí)刻25執(zhí)行Sincethereisadelayof15and10intheprecedingstatements,count=count+1willbeexecutedattime=25units由于前面的語句中包含了15和10個(gè)單位的延遲，因此語句count=count+17.2.2NonblockingAssignmentsNonblockingassignmentsallowschedulingofassignmentswithoutblockingexecutionofthestatementsthatfollowinasequentialblock.A<=operatorisusedtospecifynonblockingassignments.Notethatthisoperatorhasthesamesymbolasarelationaloperator,less_than_equal_to.Theoperator<=isinterpretedasarelationaloperatorinanexpressionandasanassignmentoperatorinthecontextofanonblockingassignment.Toillustratethebehaviorofnonblockingstatementsanditsdifferencefromblockingstatements,letusconsiderExample7-7,whereweconvertsomeblockingassignmentstononblockingassignments,andobservethebehavior.非阻塞賦值語句允許賦值調(diào)度，但他不會(huì)阻塞位于同一個(gè)順序塊中后面語句的執(zhí)行。非阻塞語句使用“<=”作為賦值符?！?lt;=”在表達(dá)式中被解釋為關(guān)系操作；“<=”在非阻塞賦值的環(huán)境下被解釋成非阻塞賦值。為了說明非阻塞賦值語句的意義以及與阻塞賦值語句之間的區(qū)別，讓我們來考慮例7.6中的部分阻塞賦值語句改為非阻塞語句的結(jié)果，例7.7給出了修改后的語句。（27）2024/3/12Example7-7NonblockingAssignmentsregx,y,z;reg[15:0]reg_a,reg_b;integercount;//AllbehavioralstatementsmustbeinsideaninitialoralwaysblockInitial所有的行為語句必須寫在initial和

always塊內(nèi)beginx=0;y=1;z=1;//Scalarassignments變量賦值

count=0;//Assignmenttointegervariables整形變量賦值

reg_a=16‘b0;reg_b=reg_a;//Initializevectors向量的初始化

reg_a[2]<=#151‘b1;//Bitselectassignmentwithdelay帶延遲的地位選賦值reg_b[15:13]<=#10{x,y,z};//Assignresultofconcatenationtopartselectofavector把拼接操作的結(jié)果賦值給向量的部分位count<=count+1;//Assignmenttoaninteger(increment)End//給整型變量賦值（28）2024/3/12Inthisexample,thestatementsx=0throughreg_b=reg_aareexecutedsequentiallyattime0.Thenthethreenonblockingassignmentsareprocessedatthesamesimulationtime.在本例中,語句通過reg_bx=0=reg_a在時(shí)間順序執(zhí)行。然后三個(gè)非阻塞在同一仿真時(shí)間處理。reg_a[2]=0isscheduledtoexecuteafter15units(i.e.,time=15)reg_b[15:13]={x,y,z}isscheduledtoexecuteafter10timeunits(i.e.,time=10)count=count+1isscheduledtobeexecutedwithoutanydelay(i.e.,time=0)（29）2024/3/12Thus,thesimulatorschedulesanonblockingassignmentstatementtoexecuteandcontinuestothenextstatementintheblockwithoutwaitingforthenonblockingstatementtocompleteexecution.Typically,nonblockingassignmentstatementsareexecutedlastinthetimestepinwhichtheyarescheduled,thatis,afteralltheblockingassignmentsinthattimestepareexecuted.因此，模擬器調(diào)度非阻塞賦值語句來執(zhí)行，并繼續(xù)在該塊中的下一個(gè)語句，而無需等待非阻塞語句來完成執(zhí)行。通常情況下，非阻塞賦值語句在其被調(diào)度，也就是說，在該時(shí)間步長的所有阻塞的分配被執(zhí)行之后的時(shí)間步最后被執(zhí)行。（30）2024/3/12（31）2024/3/12Intheexampleabove,wemixedblockingandnonblockingassignmentstoillustratetheirbehavior.However,itisrecommendedthatblockingandnonblockingassignmentsnotbemixedinthesamealwaysblock.在上面的例子中，我們用混合阻塞和非阻塞賦值來說明它們的行為。然而，我們建議不要在同一個(gè)always塊中混合使用阻塞和非阻塞賦值語句。ApplicationofnonblockingassignmentsHavingdescribedthebehaviorofnonblockingassignments,itisimportanttounderstandwhytheyareusedindigitaldesign.Theyareusedasamethodtomodelseveralconcurrentdatatransfersthattakeplaceafteracommonevent.Considerthefollowingexamplewherethreeconcurrentdatatransferstakeplaceatthepositiveedgeofclock.在描述了非阻塞賦值的行為，理解他們?yōu)槭裁丛跀?shù)字化設(shè)計(jì)中是非常重要的。它們被用作一個(gè)方法來模擬多個(gè)并發(fā)數(shù)據(jù)傳輸所發(fā)生的公共事件之后。考慮下面的例子，其中三個(gè)并行數(shù)據(jù)傳輸發(fā)生在時(shí)鐘的上升沿。always@(posedgeclock)beginreg1<=#1in1;reg2<=@(negedgeclock)in2^in3;reg3<=#1reg1;//Theoldvalueofreg1end（32）2024/3/12Ateachpositiveedgeofclock,thefollowingsequencetakesplaceforthenonblockingassignments.在每個(gè)時(shí)鐘的上升沿，按以下順序發(fā)生了非阻塞賦值。Areadoperationisperformedoneachright-hand-sidevariable,in1,in2,in3,andreg1,atthepositiveedgeofclock.Theright-hand-sideexpressionsareevaluated,andtheresultsarestoredinternallyinthesimulator.在每個(gè)時(shí)鐘上升沿到來時(shí)讀取in1，in2，in3和reg1，計(jì)算右側(cè)表達(dá)式的值；Thewriteoperationstotheleft-hand-sidevariablesarescheduledtobeexecutedatthetimespecifiedbytheintra-assignmentdelayineachassignment,thatis,schedule"write"toreg1after1timeunit,toreg2atthenextnegativeedgeofclock,andtoreg3after1timeunit.對(duì)左值的賦值由仿真器調(diào)度到相應(yīng)的仿真時(shí)刻，延遲時(shí)間由語句中內(nèi)嵌的延遲值確定。在本例中，對(duì)reg1的賦值需要等一個(gè)時(shí)間單位，對(duì)reg2的賦值需要等到時(shí)鐘信號(hào)下降沿到來的時(shí)刻，對(duì)reg3的賦值需要等一個(gè)時(shí)間單位；（33）2024/3/12（34）2024/3/12Thewriteoperationsareexecutedatthescheduledtimesteps.Theorderinwhichthewriteoperationsareexecutedisnotimportantbecausetheinternallystoredright-hand-sideexpressionvaluesareusedtoassigntotheleft-hand-sidevalues.每個(gè)賦值操作在被調(diào)度的仿真時(shí)刻完成。注意，對(duì)左側(cè)變量的賦值使用的是由仿真器保存的表達(dá)式“舊值”。Thus,thefinalvaluesofreg1,reg2,andreg3arenotdependentontheorderinwhichtheassignmentsareprocessed.在本例中，對(duì)reg3賦值使用的是reg1的“舊值”，而不是在此之前對(duì)reg1賦予的新值，reg1的“舊值”是在賦值事件調(diào)度時(shí)由仿真器保存的。Example7-8NonblockingStatementstoEliminateRaceConditions//Illustration1:Twoconcurrentalwaysblockswithblocking//statementsalways@(posedgeclock)a=b;always@(posedgeclock)b=a;//Illustration2:Twoconcurrentalwaysblockswithnonblocking//statementsalways@(posedgeclock)a<=b;always@(posedgeclock)b<=a;（35）2024/3/12（36）2024/3/12However,nonblockingstatementsusedinIllustration2eliminatetheracecondition.Atthepositiveedgeofclock,thevaluesofallright-hand-sidevariablesare"read,"andtheright-hand-sideexpressionsareevaluatedandstoredintemporaryvariables.Duringthewriteoperation,thevaluesstoredinthetemporaryvariablesareassignedtotheleft-hand-sidevariables.Separatingthereadandwriteoperationsensuresthatthevaluesofregistersaandbareswappedcorrectly,regardlessoftheorderinwhichthewriteoperationsareperformed.Example7-9showshownonblockingassignmentsshowninIllustration2couldbeemulatedusingblockingassignments.例中，產(chǎn)生了競爭的情況：a=b和b=a，具體執(zhí)行順序的先后取決于所使用的仿真器，因此這段代碼達(dá)不到交換a和b值的目的。在每個(gè)時(shí)鐘上升沿到來的時(shí)候，仿真器讀取每個(gè)操作數(shù)的值，進(jìn)而計(jì)算表達(dá)式的值并保存在臨時(shí)變量中；當(dāng)賦值的時(shí)候，仿真器將這些保存的值賦予非阻塞賦值語句的左側(cè)變量。

Example7-9ImplementingNonblockingAssignmentsusingBlockingAssignments例7-9中使用阻塞賦值實(shí)現(xiàn)非阻塞賦值（37）2024/3/12Fordigitaldesign,useofnonblockingassignmentsinplaceofblockingassignmentsishighlyrecommendedinplaceswhereconcurrentdatatransferstakeplaceafteracommonevent.Insuchcases,blockingassignmentscanpotentiallycauseraceconditionsbecausethefinalresultdependsontheorderinwhichtheassignmentsareevaluated.對(duì)于數(shù)字化設(shè)計(jì)，在發(fā)生阻塞賦值使用非阻塞賦值強(qiáng)烈建議在一個(gè)公共事件后并發(fā)的數(shù)據(jù)傳輸發(fā)生的地方。在這種情況下，阻塞賦值可能會(huì)導(dǎo)致競態(tài)條件，因?yàn)樽罱K結(jié)果取決于在其中分配的計(jì)算順序上。（38）2024/3/12（39）2024/3/12Nonblockingassignmentscanbeusedeffectivelytomodelconcurrentdatatransfersbecausethefinalresultisnotdependentontheorderinwhichtheassignmentsareevaluated.Typicalapplicationsofnonblockingassignmentsincludepipelinemodelingandmodelingofseveralmutuallyexclusivedatatransfers.Onthedownside,nonblockingassignmentscanpotentiallycauseadegradationinthesimulatorperformanceandincreaseinmemoryusage.非阻塞賦值可以被有效地用于并行數(shù)據(jù)傳輸進(jìn)行建模，因?yàn)樽罱K的結(jié)果是不依賴于所述分配的計(jì)算順序上。非阻塞賦值的典型應(yīng)用包括多種相互獨(dú)立的數(shù)據(jù)傳輸管道建模和模擬。在下行路上，非阻塞賦值可能會(huì)導(dǎo)致在模擬器性能退化和增加內(nèi)存使用情況。7.3TimingControlsVariousbehavioraltimingcontrolconstructsareavailableinVerilog.InVerilog,iftherearenotimingcontrolstatements,thesimulationtimedoesnotadvance.Timingcontrolsprovideawaytospecifythesimulationtimeatwhichproceduralstatementswillexecute.Therearethreemethodsoftimingcontrol:delay-basedtimingcontrol,event-basedtimingcontrol,andlevel-sensitivetimingcontrol.Verilog中，通過指定過程賦值發(fā)生的時(shí)刻，來控制仿真時(shí)間向前推進(jìn)。Verilog提供了三種時(shí)序控制方法：基于延遲的時(shí)序控制、基于事件的時(shí)序控制和電平敏感的時(shí)序控制。（40）2024/3/127.3.1Delay-BasedTimingControlDelay-basedtimingcontrolinanexpressionspecifiesthetimedurationbetweenwhenthestatementisencounteredandwhenitisexecuted.Weuseddelay-basedtimingcontrolstatementswhenwritingfewmodulesintheprecedingchaptersbutdidnotexplainthemindetail.Inthissection,wewilldiscussdelay-basedtimingcontrolstatements.Delaysarespecifiedbythesymbol#.Syntaxforthedelay-basedtimingcontrolstatementisshownbelow.基于延遲的時(shí)序控制出現(xiàn)在表達(dá)式中，它指定了語句開始執(zhí)行到執(zhí)行完成之間的時(shí)間間隔。我們在前面的章節(jié)寫幾個(gè)模塊時(shí)，沒有具體說明采用延遲型定時(shí)控制語句的方法。在本節(jié)中，我們將討論基于延遲的時(shí)間控制語句。延遲是由符號(hào)＃指定?；谘舆t的定時(shí)控制語句如下所示。delay3::=#delay_value|#(delay_value[,delay_value[,delay_value]])delay2::=#delay_value|#(delay_value[,delay_value])delay_value::=unsigned_number|parameter_identifier|specparam_identifier|mintypmax_expression（41）2024/3/12Delay-basedtimingcontrolcanbespecifiedbyanumber,identifier,oramintypmax_expression.Therearethreetypesofdelaycontrolforproceduralassignments:regulardelaycontrol,intra-assignmentdelaycontrol,andzerodelaycontrol.基于延遲的時(shí)序控制可以由數(shù)字，標(biāo)識(shí)符或表達(dá)式，需要在延遲值前加上關(guān)鍵字#。對(duì)于過程賦值，有三種類型的延遲控制：常規(guī)延遲控制、復(fù)制內(nèi)嵌延遲控制和零延遲控制。（42）2024/3/12RegulardelaycontrolRegulardelaycontrolisusedwhenanon-zerodelayisspecifiedtotheleftofaproceduralassignment.UsageofregulardelaycontrolisshowninExample7-10.常規(guī)延遲控制位于賦值語句的左邊，用于指定一個(gè)非零延遲值。例7.10所示。（43）2024/3/12Example7-10RegularDelayControlparameterlatency=20;//defineparameters定義參數(shù)parameterdelta=2;regx,y,z,p,q;//defineregistervariables定義寄存器變量initialbeginx=0;//nodelaycontrol沒有延遲控制#10y=1;//delaycontrolwithanumber.Delayexecutionofy=1by10units延遲值是數(shù)字的延遲控制。第10個(gè)時(shí)間單位才執(zhí)行y=1

#latencyz=0;//Delaycontrolwithidentifier.Delayof20units使用標(biāo)識(shí)符的的延遲控制。延遲20個(gè)時(shí)間單位。#(latency+delta)p=1;//Delaycontrolwithexpression使用表達(dá)式控制的延遲

#yx=x+1;//Delaycontrolwithidentifier.Takevalueofy.使用標(biāo)識(shí)符的的延遲控制。用v的值

#(4:5:6)q=0;//Minimum,typicalandmaximumdelayvalues.//Discussedingate-levelmodelingchapter.End最小，最大和典型延遲值，第五章已經(jīng)討論過（44）2024/3/12InExample7-10,theexecutionofaproceduralassignmentisdelayedbythenumberspecifiedbythedelaycontrol.Forbegin-endgroups,delayisalwaysrelativetotimewhenthestatementisencountered.Thus,y=1isexecuted10u在實(shí)例7-10中，程序分配的執(zhí)行是通過延遲控制指定的數(shù)字延遲。對(duì)于begin-end塊中的語句，延遲總是指遇到該賦值語句時(shí)，需要等待執(zhí)行的相對(duì)時(shí)間。以例7.10中的語句來說明。

因?yàn)閎egin-end塊中的第一條語句是在時(shí)刻0開始執(zhí)行的，執(zhí)行10個(gè)單元后，遇到第二條語句，于是執(zhí)行y=1。（45）2024/3/12Intra-assignmentdelaycontrolInsteadofspecifyingdelaycontroltotheleftoftheassignment,itispossibletoassignadelaytotherightoftheassignmentoperator.Suchdelayspecificationalterstheflowofactivityinadifferentmanner.Example7-11showsthecontrastbetweenintra-assignmentdelaysandregulardelays.除了可以將延遲控制置于賦值語句之前，還可以將它嵌入到賦值語句中，放在賦值符的右邊。這種延遲方式的效果與常規(guī)延遲賦值是完全不同的。在7.11中我們對(duì)兩種延遲控制進(jìn)行了比較。（46）2024/3/12（47）2024/3/12Notethedifferencebetweenintra-assignmentdelaysandregulardelays.Regulardelaysdefertheexecutionoftheentireassignment.Intra-assignmentdelayscomputetheright-hand-sideexpressionatthecurrenttimeanddefertheassignmentofthecomputedvaluetotheleft-hand-sidevariable.Intra-assignmentdelaysarelikeusingregulardelayswithatemporaryvariabletostorethecurrentvalueofaright-hand-sideexpression.注意常規(guī)延遲和內(nèi)嵌賦值延遲的區(qū)別。對(duì)常規(guī)延遲，它推遲的是整個(gè)賦值語句的執(zhí)行。對(duì)于內(nèi)嵌賦值語句，仿真器首先立即計(jì)算出右側(cè)表達(dá)式的值，推遲指定的時(shí)間之后，再將這個(gè)值賦予左側(cè)變量。因此，內(nèi)嵌延遲的效果相當(dāng)于將表達(dá)式的值保存在臨時(shí)變量中，然后使用常規(guī)延遲控制將這個(gè)值賦予左側(cè)變量。（48）2024/3/12ZerodelaycontrolProceduralstatementsindifferentalways-initialblocksmaybeevaluatedatthesamesimulationtime.Theorderofexecutionofthesestatementsindifferentalways-initialblocksisnondeterministic.Zerodelaycontrolisamethodtoensurethatastatementisexecutedlast,afterallotherstatementsinthatsimulationtimeareexecuted.Thisisusedtoeliminateraceconditions.However,iftherearemultiplezerodelaystatements,theorderbetweenthemisnondeterministic.Example7-12illustrateszerodelaycontrol.

在同一仿真時(shí)刻，位于不同always和initial塊中的過程語句有可能被同時(shí)計(jì)算，但是執(zhí)行（賦值）順序是不確定的，與使用的仿真器類型有關(guān)。在這種情況下，零延遲控制可以保證帶零延遲控制的語句將在執(zhí)行時(shí)刻相同的多條語句中最后執(zhí)行，從而避免發(fā)生競爭。但需要注意的是，如果存在多條帶有零延遲的語句，則它們之間的執(zhí)行順序也將是不確定的。（49）2024/3/12Example7-12ZeroDelayControlinitialbeginx=0;y=0;endinitialbegin#0x=1;//zerodelaycontrol零延遲控制#0y=1;end（50）2024/3/12InExample7-12,fourstatements—x=0,y=0,x=1,y=1—aretobeexecutedatsimulationtime0.However,sincex=1andy=1have#0,theywillbeexecutedlast.Thus,attheendoftime0,xwillhavevalue1andywillhavevalue1.Theorderinwhichx=1andy=1areexecutedisnotdeterministic.在例7.12中，具有零延遲，語句被最后執(zhí)行，仿真0時(shí)刻結(jié)束時(shí)，x和y的值都為1，但它們的執(zhí)行順序是不確定的。Theaboveexamplewasusedasanillustration.However,using#0isnotarecommendedpractice.在實(shí)際設(shè)計(jì)中，盡量不要使用零延遲控制（51）2024/3/127.3.2Event-BasedTimingControlAneventisthechangeinthevalueonaregisteroranet.Eventscanbeutilizedtotriggerexecutionofastatementorablockofstatements.Therearefourtypesofevent-basedtimingcontrol:regulareventcontrol,namedeventcontrol,eventORcontrol,andlevel-sensitivetimingcontrol.在Verilog中，事件是指某一個(gè)寄存器或線網(wǎng)變量的值發(fā)生了變化。Verilog提供了4種類型的事件控制：常規(guī)事件控制、命名事件控制、OR（或）事件控制和電平敏感時(shí)序控制。（52）2024/3/12RegulareventcontrolThe@symbolisusedtospecifyaneventcontrol.Statementscanbeexecutedonchangesinsignalvalueoratapositiveornegativetransitionofthesignalvalue.Thekeywordposedgeisusedforapositivetransition,asshowninExample7-13.事件控制使用符號(hào)@來說明，語句繼續(xù)執(zhí)行的條件是信號(hào)的值發(fā)生變化、發(fā)生正向跳變和負(fù)向跳變。關(guān)鍵字posedge用于指明正向跳變，negedge用于指明負(fù)向跳變。如例7.13所示：（53）2024/3/12NamedeventcontrolVerilogprovidesthecapabilitytodeclareaneventandthentriggerandrecognizetheoccurrenceofthatevent(seeExample7-14).Theeventdoesnotholdanydata.Anamedeventisdeclaredbythekeywordevent.Aneventistriggeredbythesymbol->.Thetriggeringoftheeventisrecognizedbythesymbol@.Verilog語言提供了命名事件控制機(jī)制。用戶可以在程序中聲明event（事件）類型的變量，觸發(fā)該變量，并且識(shí)別該事件是否已經(jīng)發(fā)生。命名事件由關(guān)鍵字event聲明，它不能保存任何值。事件的觸發(fā)用符號(hào)->表示；判斷事件是否發(fā)生使用符號(hào)@來識(shí)別。（54）2024/3/12（55）2024/3/12EventORControlSometimesatransitiononanyoneofmultiplesignalsoreventscantriggertheexecutionofastatementorablockofstatements.ThisisexpressedasanORofeventsorsignals.ThelistofeventsorsignalsexpressedasanORisalsoknownasasensitivitylist.Thekeywordorisusedtospecifymultipletriggers,asshowninExample7-15.有時(shí)，多個(gè)信號(hào)或者事件中發(fā)生的任意一個(gè)變化都能夠觸發(fā)語句或語句塊的執(zhí)行。在Verilog語言中，可以使用“或”表達(dá)式來表示這種情況。由關(guān)鍵詞“or”連接的多個(gè)事件名或者信號(hào)名組成的列表稱為敏感列表。關(guān)鍵詞“or”用于表示這種關(guān)系，如例7.15所示。（56）2024/3/12Sensitivitylistscanalsobespecifiedusingthe