數(shù)字邏輯設(shè)計 - 存儲器與可編程邏輯陣列

存儲器與可編程邏輯陣列數(shù)字系統(tǒng)設(shè)計22015

ZDMCComputer

System

計算機系統(tǒng)數(shù)字系統(tǒng)設(shè)計32015

ZDMCROM（Read

Only

Memory），只讀存儲器

ROM是各種存儲器中結(jié)構(gòu)最簡單的一種。在正常工作時它存儲的數(shù)據(jù)是固定不變的，只能讀出，不能隨時寫入.分類

固定ROM：無法更改，出廠時廠家編程

可編程ROM（PROM）：用戶可寫入一次

可擦可編程ROM（EPROM）：紫外線擦除

電抹可編程ROM（EEPROM）:電可擦4電路結(jié)構(gòu)框圖

n線---2n線譯碼器

二進制譯碼器數(shù)字系統(tǒng)設(shè)計地址輸入容量概念：地址線：A0A1...An-10單元1單元W0W1

.

.

.2n-1單元...D0

D1Db-1

數(shù)據(jù)輸出

“位”線：數(shù)據(jù)線“字”線：只有一個有效

2015

ZDMC地址譯碼器輸出緩沖器三態(tài)

OE控制

.

.

.W2n?1

容量=字×位=

2n

×b（bits）例

EPROM

27256共有15位地址，8位輸出，其容量：

215

×

8

=

262144

=

256K注意：1k=10241M=1024K1G=1024M核心

存儲矩陣有

高電平，D1=0源負(fù)載字線處于低電平，

單

0=1。

矩陣4×2存儲

D

元

D0

=W0

+W25

CMOS-ROM

2-4線譯碼器地址碼輸入端111W0

=

AA0W1

=

A1A0W2

=

AA0W3

=

AA0

2015

ZDMC輸出緩沖器

數(shù)字系統(tǒng)設(shè)計沒接MOS，字線處于表示存0=00時，W0=1，MOS導(dǎo)通，

接MOS表示存儲“1”A

A儲“0”

1地址譯碼器實現(xiàn)“與”功能：與陣列

存儲矩陣實現(xiàn)“或”功能：“或陣”

D1

=W1+W2

+W3

數(shù)字系統(tǒng)設(shè)計62015

ZDMCTypical

timing

for

a

ROM

read

operation7

存儲矩陣即為或陣列把乘積

項組合成m個邏輯函數(shù)輸出。

地址譯碼器產(chǎn)生2n個字線即為固定與陣列產(chǎn)生2n個乘積項

輸入地址信號即為電路的輸入邏輯變量另外：ROM看成查找表（LUT，Look-Up

Table）系統(tǒng)

數(shù)字系統(tǒng)設(shè)計

2015

ZDMCROM應(yīng)用

(ROM

Applications)十進制數(shù)（最小項）二進制碼格雷碼十進制數(shù)（最小項）二進制碼格雷碼B3B2B1B0R3R2R1R0B3B2B1B0R3R2R1R0000000000810001100100010001910011101200100011101010111130011001011101111104010001101211001010501010111131101101160110010114111010017011101001511111000數(shù)字系統(tǒng)設(shè)計82015

ZDMC

ROM為組合電路器件：

實現(xiàn)組合邏輯函數(shù)，實現(xiàn)時序電路

中組合邏輯部分.

方法：“查找表”，將真值表存于ROM中。例：用一個ROM實現(xiàn)二進制碼到格雷碼的轉(zhuǎn)換

表

格雷碼與二進制碼關(guān)系對照表92015

ZDMC?確定地址和輸出輸入變量為B3、B2、B1、B0，地址為4位；函數(shù)R3、R2、R1、R0，輸出為4個，應(yīng)選用24×4的ROM?邏輯圖：

ROM

24×40123A

015[0]A[1]A[2]A[3]A

CS

OE數(shù)字系統(tǒng)設(shè)計B0B1B2B3R0R1R2R3?存儲內(nèi)容（數(shù)據(jù)）：地址0數(shù)據(jù)D3D2D1D000000001001112……151000數(shù)字系統(tǒng)設(shè)計102015

ZDMC例.

用ROM和寄存器實現(xiàn)同時模10加/減可逆計數(shù)器，

X=0，加法；

X=1，減法。模10計數(shù)狀態(tài)需4位，所以選用4位寄存器。根據(jù)時序電路結(jié)構(gòu)，可得框圖：Reg

CP圖中組合電路由ROM實現(xiàn)；而由寄存器作記憶電路。Q44組合電路Y（進位）XDA數(shù)字系統(tǒng)設(shè)計112015

ZDMC?確定地址和輸出輸入變量為Q3、Q2、Q1、Q0和X，地址為5位；輸出D3、D2、D1、D0和Y，5個，應(yīng)選用25×5的ROM?邏輯圖：?存儲內(nèi)容（數(shù)據(jù)）：

地址

數(shù)據(jù)00000000010000100010……0100001001010011000000000110010000010~151000010001……1100000111110010100026~310000001234ROM

25×5

0

[0]A

3

[1]A

1

[2]A

[3]A[4]ACSOEYQ0Q1Q2Q3CPREGX加法計數(shù)計數(shù)狀態(tài)未用

減法狀態(tài)未用A2A1A0B5B4B3B200000000010000010000101100101000100101011011010011111100數(shù)字系統(tǒng)設(shè)計122015

ZDMC例：用ROM設(shè)計一個組合電路，該電路輸入是3位二進制數(shù)，輸出是輸入數(shù)值的平方。

列出組合電路的真值表。一般情況下真值表中所有可能的輸入和輸出都要列出。三個輸入端對應(yīng)8個字，每個字4位，因此ROM的容量是8x4。8x4ROMA0A1A2B0B10B2

B3B4

B5ROM真值表輸入輸出A2A1A0B5B4B3B2B1B0十進制00000000000010000011010000100401100100191000100001610101100125110100100361111100014913電路真值表

輸出B0等于輸入A0,輸出B1一直為0.

本例中有三個輸入端和四個輸出端。數(shù)字系統(tǒng)設(shè)計

2015

ZDMC數(shù)字系統(tǒng)設(shè)計142015

ZDMCSARM

General

Memory

Operation(Static

Random-Access

Memory)Address

Decoder15Typical

SRAM

Organization:

16-word

x

4-bit++++

SRAM

Cell

SRAM

Cell

:

SRAM

Cell-

Sense

Amp

SRAM

Cell

SRAM

Cell

:

SRAM

Cell-

Sense

Amp

SRAM

Cell

SRAM

Cell

:

SRAM

Cell-

Sense

Amp

SRAM

Cell

SRAM

Cell

:

SRAM

Cell-

Sense

Amp

Word

0Word

1Word

15Dout

0

Dout

12015

ZDMCDout

2

Dout

3數(shù)字系統(tǒng)設(shè)計-+Wr

Driver-+Wr

Driver-+Wr

Driver-+Wr

DriverWrEnDin

0Din

1Din

2Din

3A0A1A2A3數(shù)字系統(tǒng)設(shè)計162015

ZDMC

Read

operation:

1.

Select

row

2.

Cell

pulls

one

line

low

and

one

high

3.

Sense

output

on

bit

and

bitWrite

operation:

1.

Drive

bit

lines

(e.g,

bit=1,

bit=0)

2.

Select

rowWhy

does

this

work?

When

one

bit-line

is

low,

it

will

force

output

high;

that

will

set

new

stateStatic

RAM

Cell

(靜態(tài)隨機訪問存儲器單元)Random-Access

Memory

6-Transistor

SRAM

Cellbitbitword(row

select)1001數(shù)字系統(tǒng)設(shè)計172015

ZDMC

Write

Enable

is

usually

active

low

(WE_L)Din

and

Dout

are

combined

to

save

pins:A

new

control

signal,

Output

Enable

(OE_L)

WE_L

is

asserted

(Low),

OE_L

is

unasserted

(High)

–

D

serves

as

the

data

input

pin

WE_L

is

unasserted

(High),

OE_L

is

asserted

(Low)

–

D

is

the

data

output

pin

Neither

WE_L

and

OE_L

are

asserted?

–

Chip

is

disconneted

Never

both

asserted!D2N

“words”

x

M

bit

SRAMM

A

NWE_LOE_LLogic

Diagram

of

a

Typical

SRAMor

chipSelect

(CS)

+

WERead

AccessTime18Typical

SRAM

TimingWrite

Timing:DRead

Timing:WE_L

數(shù)字系統(tǒng)設(shè)計A

Write

Hold

TimeWrite

Setup

Time

2015

ZDMCD2Nwords

x

M

bit

SRAMM

A

NWE_LOE_LData

InWrite

AddressOE_LHigh

ZRead

AddressJunkData

OutRead

Access

TimeData

OutRead

AddressOE

determines

direction

Hi

=

Write,

Lo

=

ReadWrites

are

dangerous!

Be

careful!

Double

signaling:

OE

Hi,

WE

Lo數(shù)字系統(tǒng)設(shè)計202015

ZDMC

ANDarray

ORarrayoutputs

?

?

?product

termsProgrammable

Logic

Arrays

(PLAs)

Pre-fabricated

building

block

of

many

AND/OR

gates

Actually

NOR

or

NAND

”Personalized"

by

making

or

breaking

connections

among

gates

Programmable

array

block

diagram

for

sum

of

products

form

?

?

?

inputs數(shù)字系統(tǒng)設(shè)計212015

ZDMCexample:F0F1F2F3====A

+A

C'B'

C'B'

CB'

C'+

AB

+

AB+

Ainput

side:

1

=

uncomplemented

in

term

0

=

complemented

in

term

–

=

does

not

participateproductpersonality

matrix

inputs

outputs

termABB'CAC'B'C'AA1–1–1B10–0–C–100–F000011F110100F210010F301001output

side:

1

=

term

connected

to

output

0

=

no

connection

to

output

reuse

of

termsEnabling

Concept

Shared

product

terms

among

outputs數(shù)字系統(tǒng)設(shè)計222015

ZDMC

Before

Programming

All

possible

connections

available

before

"programming"

In

reality,

all

AND

and

OR

gates

are

NANDs數(shù)字系統(tǒng)設(shè)計232015

ZDMCSimplified

PLD

Symbology數(shù)字系統(tǒng)設(shè)計242015

ZDMCABCF1F2F3F0

ABB'CAC'B'C'

A

After

Programming

Unwanted

connections

are

"blown"

Fuse

(normally

connected,

break

unwanted

ones)

Anti-fuse

(normally

disconnected,

make

wanted

connections)數(shù)字系統(tǒng)設(shè)計252015

ZDMCAB+A'B'

CD'+C'DAlternate

Representation

for

High

Fan-in

Structures

Short-hand

notation--don't

have

to

draw

all

the

wires

Signifies

a

connection

is

present

and

perpendicular

signal

is

an

input

to

gate

notation

for

implementing

F0

=

A

B

+

A'

B'

F1

=

C

D'

+

C'

D

A

B

C

D

AB

A'B'

CD'

C'D262015

ZDMC

A

B

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

1數(shù)字系統(tǒng)設(shè)計C01010101F1

F20

00

10

10

10

10

10

11

1F3

F41

10

10

10

10

10

10

10

0F5

F60

01

11

10

01

10

00

01

1A'BCAB'C'AB'CABC'ABCA

B

CF1

F2

F3

F4

F5

F6full

decoder

as

for

memory

address

bits

stored

in

memory

A'B'C'

A'B'C

A'BC'Programmable

Logic

Array

Example

Multiple

functions

of

A,

B,

C

F1

=

A

B

CF2

=

A

+

B

+

CF3

=

A'

B'

C'F4

=

A'

+

B'

+

C'F5

=

A

xor

B

xor

CF6

=

(A

xnor

B

xnor

C)’001X01X011XX11XX001X01X000XX00XX00X101X101XX01XXW=A+BD+BCC

027DCA000000001111B000011110001C00110011001–D0101010101––W0000011111––X0000110000––Y0011111100––Z0110000110––DCD

A

BK-map

for

W

A

minimized

functions:

C

X

=

B

C'

Y=B+C

Z

=

A'B'C'D

+

B

C

D

+

A

D'

+

B'

C

D'數(shù)字系統(tǒng)設(shè)計

2015

ZDMC

BK-map

for

YPLA

Design

Example

BCD

to

Gray

code

converterD

A

B

K-map

for

X

A0

0

X

11

0

X

0

1

X

X1

0

X

X

B

K-map

for

Z數(shù)字系統(tǒng)設(shè)計282015

ZDMCW

XYZABDBCBC'BCA'B'C'DBCDAD'BCD'W=A+BD+BCX

=

B

C'Y=B+CZ

=

A'B'C'D

+

B

C

D

+

A

D'

+

B'

C

D'

not

a

particularly

good

candidate

for

PLA

implementation

since

no

terms

are

shared

among

outputs

however,

much

more

compact

and

regular

implementation

when

compared

with

discrete

AND

and

OR

gatesPLA

Design

Example

(cont’d)

Code

converter:

programmed

PLA

A

B

C

D

minimized

functions:01X001X011XX11XX00X110X001XX10XX00X101X101XX01XX01X001X000XX00XX29DCminimized

functions:

W=

X=

Y=

Z=數(shù)字系統(tǒng)設(shè)計A000000001111B000011110001C00110011001–D0101010101––W0000011111––X0000110000––Y0011111100––Z0110000110––DCD

A

BK-map

for

W

A

C2015

ZDMC

BK-map

for

YPLA

Design

Example

BCD

to

Gray

code

converterD

A

BK-map

for

X

A

BK-map

for

ZC01X0011X1X0X11XX00X1011X01XX01XX01X001X000XX00XXC

030D

minimized

functions:

W=

X=

Y=

Z=數(shù)字系統(tǒng)設(shè)計A000000001111B000011110001C00110011001–D0101010101––W0000011111––X0000110000––Y0011111100––Z0110000110––DCD

A

BK-map

for

W

A

C2015

ZDMC

BK-map

for

YPLA

Design

Example

#1

BCD

to

Gray

code

converterD

A

B

K-map

for

X

A0

0

X

11

0

X

0

1

X

X1

0

X

X

B

K-map

for

Z

CBC’數(shù)字系統(tǒng)設(shè)計322015

ZDMCmultiplexerdemultiplexer4x4

switchcontrolcontrolMultiplexer

/

Demultiplexer:

Making

Connections

Direct

point-to-point

connections

between

gatesMultiplexer:

route

one

of

many

inputs

to

a

single

outputDemultiplexer:

route

single

input

to

one

of

many

outputs數(shù)字系統(tǒng)設(shè)計332015

ZDMCfunctional

form

logical

form

two

alternative

forms

for

a

2:1

Mux

truth

tableA01ZI0I1I1000I0001A010Z00101111100111010100111Z

=

A'

I0

+

A

I1Multiplexers/Selectors

Multiplexers/Selectors:

general

concept

2n

data

inputs,

n

control

inputs

(called

"selects"),

1

output

Used

to

connect

2n

points

to

a

single

point

Control

signal

pattern

forms

binary

index

of

input

connected

to

output2n

-1In

general,

Z

=

Σ

(mkIk)ZmuxZ數(shù)字系統(tǒng)設(shè)計34

A

B

C

8:1muxZ

A

B2015

ZDMCA

2:1

mux:

Z

=

A'

I0

+

A

I1

4:1

mux:

Z

=

A'

B'

I0

+

A'

B

I1

+

A

B'

I2

+

A

B

I3

8:1

mux:

Z

=

A'B'C'I0

+

A'B'CI1

+

A'BC'I2

+

A'BCI3

+

AB'C'I4

+

AB'CI5

+

ABC'I6

+

ABCI7

k=0

in

minterm

shorthand

form

for

a

2n:1

Mux

I0

I1

I2

I3

I0

I4

I1

4:1

I5I0

2:1

I2

I6I1

mux

I3

I7Multiplexers/Selectors

(cont'd)I04:1I12:1mux4:12:135ZI0I1I2I3I4I5I6I7

alternative

implementation

2:1

8:1mux

mux

2:1mux

muxmux

2:1mux

C

A

B

Cascading

Multiplexers

Large

multiplexers

implemented

by

cascading

smaller

ones

8:1

mux

I2

mux

I3

Z

I4

I5

4:1

I6

mux

I7

B

C

Acontrol

signals

B

and

C

simultaneously

chooseone

of

I0,

I1,

I2,

I3

and

one

of

I4,

I5,

I6,

I7

control

signal

A

chooses

which

of

the

upper

or

lower

mux's

output

to

gate

to

Z

數(shù)字系統(tǒng)設(shè)計

2015

ZDMC數(shù)字系統(tǒng)設(shè)計362015

ZDMCCAB0121010001134

8:1

MUX567

S2

S1

S0F

Multiplexers

as

Lookup

Tables

(LUTs)

2n:1

multiplexer

implements

any

function

of

n

variables

With

the

variables

used

as

control

inputs

and

Data

inputs

tied

to

0

or

1

In

essence,

a

lookup

table

Example:

F(A,B,C)

=

m0

+

m2

+

m6

+

m7=

A'B'C'

+

A'BC'

+

ABC'

+

ABC=

A'B'(C')

+

A'B(C')

+

AB'(0)

+

AB(1)S1

S0372015

ZDMCA00001111B00110011C01010101F10100011C'C'01F01

4:1

MUX23

A

BC'C'01FCA數(shù)字系統(tǒng)設(shè)計B1010001101234

8:1

MUX567

S2

S1

S0Multiplexers

as

LUTs

(cont’d)

2n-1:1

mux

can

implement

any

function

of

n

variables

With

n-1

variables

used

as

control

inputs

and

Data

inputs

tied

to

the

last

variable

or

its

complementExample:

F(A,B,C)

=

m0

+

m2

+

m6

+

m7

=

A'B'C'

+

A'BC'

+

ABC'

+

ABC

=

A'B'(C')

+

A'B(C')

+

AB'(0)

+

AB(1)1011100011010110數(shù)字系統(tǒng)設(shè)計382015

ZDMC

Example:

F(A,B,C,D)

implemented

by

an

8:1

MUXn-1

mux

control

variables

single

mux

data

variablefour

possibleconfigurationsof

truth

table

rowscan

be

expressedas

a

function

of

Inchoose

A,B,C

as

control

variables

multiplexer

implementationGeneralization

I0I1.

.

.

In-1

InF........0100001In10In'111CAB0121D01D’DD’D’34

8:1

MUX567

S2

S1

S0DABCMultiplexers

as

LUTs

(cont’d)數(shù)字系統(tǒng)設(shè)計392015

ZDMC

1:2Decoder:

O0

=

G

?

S’

O1

=

G

?

S

2:4

Decoder:O0

=

G

?

S1’

?O1

=

G

?

S1’

?O2

=

G

?

S1

?O3

=

G

?

S1

?S0’S0

S0’

S0O0O1O2O3O4O5O6O7

3:8

Decoder:=

G

?

S2’

?

S1’

?

S0’=

G

?

S2’

?

S1’

?

S0=

G

?

S2’

?

S1

?

S0’=

G

?

S2’

?

S1

?

S0=

G

?

S2

?

S1’

?

S0’=

G

?

S2

?

S1’

?

S0=

G

?

S2

?

S1

?

S0’=

G

?

S2

?

S1

?

S0Demultiplexers

/

Decoders

Decoders

/

demultiplexers:

general

concept

Single

data

input,

n

control

inputs,

2n

outputs

Control

inputs

(called

“selects”

(S))

represent

binary

index

of

output

to

which

the

input

is

connected

Data

input

usually

called

“enable”

(G)數(shù)字系統(tǒng)設(shè)計402015

ZDMCdemultiplexer

generates

appropriate

Min-term

based

on

control

signals

(it

"decodes"

control

signals)Demultiplexers

as

General-Purpose

Logic

n:2n

decoder

implements

any

function

of

n

variables

With

the

variables

used

as

control

inputs

Enable

inputs

tied

to

1

and

Appropriate

min-terms

summed

to

form

the

functionA'B'C'A'B'CA'BC'A'BCAB'C'AB'CABC'ABC

0

1

2

33:8

DEC

4

5

6

7S2

S1

S0A

B

C“1”數(shù)字系統(tǒng)設(shè)計41

F1F2F3Demultiplexers

as

General-Purpose

Logic

(cont’d)

F1

=

A'

B

C'

D

+

A'

B'

C

D

+

A

B

C

D

A'B'C'D'A'B'C'DA'B'CD'A'B'CDA'BC'D'A'BC'DA'BCD'A'BCDAB'C'D'AB'C'DAB'CD'AB'CDABC'D'ABC'DABCD'ABCD

0

1

2

3

4

5

64:16

7DEC

8

9

10

11

12

13

14

15F2

=

A

B

C'

D’

+

A

B

CF3

=

(A'

+

B'

+

C'

+

D')

Enable

A

B

C

D2015

ZDMC2:4

DECF3:8

DEC3S2

S1

S03:8

DEC3S2

S1

S03:8

DEC33:8

DEC

3S2

S1

S0數(shù)字系統(tǒng)設(shè)計422015

ZDMC7ECD

0

1

2

4

5

6S2

S1

S0

0

1

2

4

5

6

7A'BC'DE'

AB'C'D'E'

AB'CDECascading

Decoders

5:32

decoder

1x2:4

decoder

4x3:8

decoders

0

1

2

S1

S0

3

A

B01245670124567A'B'C'D'E'ABCDEECD2

-1數(shù)字系統(tǒng)設(shè)計decoder

0

n-1

Address2015

ZDMCn1111word[i]

=

0011word[j]

=

1010bit

lines

(normally

pulled

to

1

throughresistor

–

selectively

connected

to

0by

word

line

controlled

switches)

43ij0internal

organizationword

lines

(only

oneis

active

–

decoder

isjust

right

for

this)

Read-only

MemoriesTwo

dimensional

array

of

1s

and

0s

Entry

(row)

is

called

a

"word"

Width

of

row

=

word-sizeIndex

is

called

an

"address"

Address

is

inputSelected

word

is

output數(shù)字系統(tǒng)設(shè)計442015