TW9912-FN7945.1完整版本資料

Techwell

NTSC/PAL/SECAMVideoDecoderwithComponentInputandProgressiveOutputSupport

TW9912

Features

VideoDecoder

NTSC(M,4.43)andPAL(B,D,G,H,I,M,N,N

combination),PAL(60),SECAMsupportwithautomaticformatdetection

SoftwareselectableanaloginputcontrolBuilt-inanaloganti-aliasfilter

FullyprogrammablestaticgainorautomaticgaincontrolfortheYchannel

ProgrammablewhitepeakcontrolfortheYchannel4-HadaptivecombfilterY/Cseparation

PALdelaylineforcolorphaseerrorcorrectionImageenhancementwithpeakingandCTI

Digitalsub-carrierPLLforaccuratecolordecoding

DigitalHorizontalPLLforsynchronizationprocessingandpixelsampling

Advancedsynchronizationprocessingandsyncdetectionforhandlingnon-standardandweaksignal

Programmablehue,brightness,saturation,contrast,andsharpness

AutomaticcolorcontrolandcolorkillerChromaIFcompensation

VBIslicersupportingCCandWSSdataservicesProgrammableoutputcontrol

AnalogVideoInput

Triple10-bitADCswithindependentclampingandgaincontrol

Supports480i/480p/576i/576panalogcomponentinputwithSOG

DigitalOutput

ITU-R656compatibleYCbCr(4:2:2)outputformat

ProgressiveITU-R656outputformatsupportforbothinterlacedandprogressiveinputs

Miscellaneous

TwowireMPUserialbusinterfacePowersaveandPowerdownmodeLowpowerconsumption

Single27MHzcrystalforalloperations

3.3VtolerantI/O

1.8V/3.3Vpowersupply48pinQFNpackage

1

FN7945.1

September27,2012

CAUTION:Thesedevicesaresensitivetoelectrostaticdischarge;followproperICHandlingProcedures.1-888-INTERSILor1-888-468-3774|CopyrightIntersilAmericasInc.2012.AllRightsReservedIntersil(anddesign)isatrademarkownedbyIntersilCorporationoroneofitssubsidiaries.

Allothertrademarksmentionedarethepropertyoftheirrespectiveowners.

TW9912

2

SyncProcessor

4HAdaptiveCombFilter

Line-lockclockGenerator

Clock

Luma/Chromaprocessing

ChromaDemodulation

VideoInterface

VBISlicer

PLL

AnalogVideoIn

Triple10-bitAFE

FunctionalDescription

SOG

VD[7:0]

VIN0

CIN1-0

U

YIN3-0

V

HSO

Y

VSO

CLKO

27Mhz

MPOUT

PDN

RSTB

SCLK

SDAT

2WireSerialBus

ComponentProcessing

FIGURE1.TW9912BLOCKDIAGRAM

OrderingInformation

PARTNUMBER

PARTMARKING

PACKAGE

(Pb-free)

PKG.DWG.#

TW9912-NA3-CR

(Note

1

)

TW9912NA3-CR

48LdQFN

L48.7X7L

NOTE:

TheseIntersilPb-freeplasticpackagedproductsemployspecialPb-freematerialsets,moldingcompounds/dieattachmaterials,and100%mattetinplateplusanneal(e3terminationfinish,whichisRoHScompliantandcompatiblewithbothSnPbandPb-freesolderingoperations).IntersilPb-freeproductsareMSLclassifiedatPb-freepeakreflowtemperaturesthatmeetorexceedthePb-freerequirementsofIPC/JEDECJSTD-020.

TW9912

PAGE

3

TableofContents

OrderingInformation 2

FunctionalDescription 2

Introduction 5

AnalogFrontEnd 5

SyncProcessor 5

Y/CSeparation 5

ColorDemodulation 5

AutomaticChromaGainControl 6

ColorKiller 6

Automaticstandarddetection 6

ComponentProcessing 7

Sharpness 7

ColorTransientImprovement 7

PowerManagement 7

HostInterface 7

Cropping 8

OutputInterface 9

ITU-RBT.656 9

ControlSignals 9

Verticaltimingdiagram 9

HSYNC 12

VSYNC 12

FIELD 12

ClosedCaptioningandExtendedDataServices 12

TwoWireSerialBusInterface 14

FilterCurves 16

Anti-aliasfilter 16

Decimationfilter 16

ChromaBandPassFilterCurves 17

LumaNotchFilterCurveforNTSCandPAL/SECAM 17

ChrominanceLow-PassFilterCurve 18

PeakingFilterCurves 19

PinDiagram 20

48PinQFN 20

PinDescriptions 21

PowerandGroundPins 22

ParametricInformation 23

AC/DCElectricalParameters 23

OutputTiming 26

SerialHostInterfaceTiming 27

SerialHostInterfaceTimingDiagram 27

PackageOutlineDrawing 28

ApplicationSchematics 29

PCBLayoutConsiderations 30

ThermalPadConsideration 31

TW9912RegisterSummary 32

ADC/LLPLL 34

0x01–ChipStatusRegister(CSTATUS) 36

0x02–InputFormat(INFORM) 36

0x03–OutputControlRegister(OPFORM) 37

0x04–ColorKillerHysteresisandHSYNCDelayControl38

0x05–OutputControlRegisterII 38

0x06–AnalogControlRegister(ACNTL) 39

0x07–CroppingRegister,High(CROP_HI) 40

0x08–VerticalDelayRegister,Low(VDELAY_LO) 40

0x09–VerticalActiveRegister,Low(VACTIVE_LO) 40

0x0A–HorizontalDelayRegister,Low(HDELAY_LO) 40

0x0B–HorizontalActiveRegister,Low(HACTIVE_LO)41

0x0C–ControlRegisterI(CNTRL1) 41

0x0D–CC/WSSControl 41

0x10–BRIGHTNESSControlRegister(BRIGHT) 42

0x11–CONTRASTControlRegister(CONTRAST) 42

0x12–SHARPNESSControlRegisterI(SHARPNESS)42

0x13–Chroma(U)GainRegister(SAT_U) 43

0x14–Chroma(V)GainRegister(SAT_V) 43

0x15–HueControlRegister(HUE) 43

0x16–Reserved 43

0x17–VerticalPeakingControlI 44

0x18–CoringControlRegister(CORING) 44

0x19–Reserved 44

0x1A–CC/EDSStatusRegister(CC_STATUS) 45

0x1B–CC/EDSDataRegister(CC_DATA) 45

0x1C–StandardSelection(SDT) 46

0x1D–StandardRecognition(SDTR) 46

0x1E–ComponentVideoFormat(CVFMT) 47

0x1F–Reserved 47

0x20–ClampingGain(CLMPG) 47

0x21–IndividualAGCGain(IAGC) 47

0x22–AGCGain(AGCGAIN) 48

0x23–WhitePeakThreshold(PEAKWT) 48

0x24–Clamplevel(CLMPL) 48

0x25–SyncAmplitude(SYNCT) 48

0x26–SyncMissCountRegister(MISSCNT) 48

0x27–ClampPositionRegister(PCLAMP) 49

0x28–VerticalControlI 49

0x29–VerticalControlII 49

0x2A–ColorKillerLevelControl 50

0x2B–CombFilterControl 50

0x2C–LumaDelayandHFilterControl 50

0x2D–MiscellaneousControlRegisterI(MISC1) 50

0x2E–MiscellaneousControlRegisterII(MISC2) 51

0x2F–MiscellaneousControlIII(MISC3) 52

0x30–CopyProtectionDetection 52

0x31–ChipSTATUSII(CSTATUS2) 53

0x32–HMonitor(HFREF) 53

0x33–CLAMPMODE(CLMD) 54

0x34–IDDetectionControl(NSEN/SSEN/PSEN/WKTH)54

0x35–ClampControl(CLCNTL) 55

0x36–De-interlacerControl 55

0x37–De-interlacerHDelayControl 55

0x38–De-interlacerSyncGeneration 56

0x40–WSS0 56

0x41–WSS1 56

0x42–WSS2 56

0x43–CCEVENLINE 56

ADC/PLLConfigurationRegisters 57

0xC0–LLPLLInputControlRegister 57

0xC1–LLPLLInputDetectionRegister 57

0xC2–LLPLLControlRegister 58

0xC3–LLPLLDividerHighRegister 58

0xC4–LLPLLDividerLowRegister 58

0xC5–LLPLLClockPhaseRegister 58

0xC6–LLPLLLoopControlRegister 59

0xC7–LLPLLVCOControlRegister 59

0xC8–LLPLLVCOControlRegister 59

0xC9–LLPLLPreCoastRegister 59

0xCA–LLPLLPostCoastRegister 59

0xCB–SOGThresholdRegister 60

0xCC–ScalerSyncSelectionRegister 60

0xCD–PLLInitializationRegister 61

0xD0–GainControlRegister 61

0xD1–YChannelGainAdjustRegister 61

0xD2–CChannelGainAdjustRegister 61

0xD3–VChannelGainAdjustRegister 61

0xD4–ClampModeControlRegister 62

0xD5–ClampStartPositionRegister 62

0xD6–ClampStopPositionRegister 62

0xD7–ClampMasterLocationRegister 62

0xD8–ADCTESTRegister 63

0xD9–YClampReferenceRegister 63

0xDA–CClampReferenceRegister 63

0xDB–VClampReferenceRegister 63

0xDC–HSOWidth 63

0xE0–LLPLLControlRegister 64

0xE1–GPLLControlRegister 64

0xE2–ADCControlI 65

0xE6–ADCControlV 65

0xE7–ADCControlVI 66

0xE8–ADCControlVII 66

0xE9–ClockControl 67

LifeSupportPolicy 68

DatasheetRevisionHistory 68

Introduction

TheTW9912isalowpowerNTSC/PAL/SECAMvideodecoderchipthatalsosupportsanalogcomponentvideoasaninput.Thevideodecoderdecodesthebase-bandanalogCVBSorS-videosignalsintodigitalan8-bit4:2:2YCbCrformat.Theanalogcomponentvideoisdigitizedintoan8-bitYCbCrformat.ThedigitaloutputsupportsstandardBT.656formatforinterlacedvideo.ItcanalsooutputprogressiveBT.656formatwhenreceivingaprogressivecomponentinputorbyconvertinginterlacedvideointoprogressiveformatviaaninternalde-interlacingengine.TW9912usesthe1.8Vforbothanaloganddigitalsupplyvoltageand3.3VforI/Opower.Asingle27MHzcrystalisallthatneededtodecodeallanalogvideostandards.

Thischipconsistsofananalogfront-endwithinputsourceselection,avariablegainamplifier,analog-to-digitalconverters,aY/Cseparationcircuit,amulti-standardcolordecoder(PALBGHI,PALM,PALN,combinationPALN,NTSCM,NTSC4.43andSECAM)andsynchronizationcircuitry.Y/Cseparationisdonewithahighqualityadaptive4Hcombfilterforreducedcrosscolorandcrossluminance.Theadvancedsynchronizationprocessingcircuitrycanproducestablepicturesfornon-standardandweaksignals.Theoutputofthedecoderisline-lockedtoitsinputs.

TW9912alsoincludescircuitstodetectandprocessverticalblankinginterval(VBI)signals,includingclosedcaptionandWSS.ItslicesandprocessVBIdataforoutputbyregisterreadoutthroughthehostinterface.Italsodetectsanalogcopy-protectedsignalsthatcontainsAGCandcolorstripepulses.

A2-wireserialhostinterfaceisusedtosimplifysystemintegration.Allthefunctionscanbecontrolledthroughthisinterface.

AnalogFrontEnd

Theanalogfront-endpre-processesanddigitizestheACcoupledanalogsignalforfurtherprocessing.Allchannelshavebuilt-inanti-aliasingfiltersand10-bithighspeedADCs.Thecharacteristicsofthefilterisavailableinthefiltercurvesectionofthisdatasheet.Allchannelshavebuilt-invariablegainamplifierthatcanbeprogrammed.TheYchannelgaincanbeautomaticallycontrolledinthedecodermodeifenabled.Itcansupportamaximuminputvoltagerangeof1.4Vwithoutattenuation.AllchannelsalsohaveaclampingcircuitthatrestorestheproperDClevelthroughmanualorautomaticcontrol.

SyncProcessor

ThesyncprocessorofTW9912detectshorizontalsynchronizationandverticalsynchronizationsignalsinthecompositevideoorintheYsignalofanS-videoorcomponentinput.Theprocessorcontainsadigitalphase-locked-loopanddecisionlogictoachievereliablesyncdetectioninastablesignalaswellasinanunstablesignal,suchasthosefromVCRfastforwardorrewind.Itallowsthesamplingofthevideosignalinline-lockedfashion.Inthecaseofprogressivecomponentinput,theSOGinputisusedtocontrolthesyncprocessorPLLforsamplingtheinputvideo.

Y/CSeparation

ForNTSCandPALstandardsignalsindecodermode,theluma/chromaseparationcanbedoneeitherbyadaptivecombfilteringornotch/band-passfiltercombination.ForSECAMstandardsignals,onlynotch/band-passfilterisavailable.ThedefaultselectionforNTSC/PALiscombfilter.Thecharacteristicsoftheband-passfilterareshowninthefiltercurvesection.

TW9912employshighquality4-Hadaptivecombfiltertoreduceartifactslikehangingdotsandcrawlingdots.Duetothelinebufferusedinthecombfilter,thereisalwaysatwolineprocessingdelayintheoutputimagesnomatterwhatstandardorfilteroptionischosen.

ColorDemodulation

ThecolordemodulationofNTSCandPALsignalisdonebyfirstquadraturedownmixingandthenlow-passfiltering.Thelow-passfiltercharacteristiccanbeselectedforoptimizedtransientcolorperformance.ForthePALsystem,thePALIDortheburstphaseswitchingisidentifiedtoaidthePALcolordemodulation.

TheSECAMdecodingprocessconsistsofFMdemodulatorandde-emphasisfiltering.DuringtheFMdemodulation,thechromacarrierfrequencyisidentifiedandusedtocontroltheSECAMcolordemodulation.

Thesub-carriersignalforuseinthecolordemodulatorisgeneratedbydirectdigitalsynthesisPLLthatlocksontotheinputsub-carrierreference(colorburst).Thisarrangementallowsanysub-standardofNTSCandPALtobedemodulatedeasilywithsinglecrystalfrequency.

AUTOMATICCHROMAGAINCONTROL

TheAutomaticChromaGainControl(ACC)compensatesforreducedamplitudescausedbyhigh-frequencylossinvideosignal.TherangeofACCcontrolis–6dbto+26db.

COLORKILLER

Forlowcoloramplitudesignals,blackandwhitevideo,orverynoisysignals,thecolorwillbe―killed‖.TW9912‘scolorkillerusestheburstamplitudemeasurementaswellassub-carrierPLLstatustoswitch-offthecolor.

AUTOMATICSTANDARDDETECTION

TheTW9912hasbuild-inautomaticstandarddiscriminationcircuitry.Thecircuitusesburst-phase,burst-frequencyandframeratetoidentifyNTSC,PALorSECAMcolorsignals.ThestandardsthatcanbeidentifiedareNTSC(M),NTSC(4.43),PAL(B,D,G,H,I),PAL(M),PAL(N),PAL(60)andSECAM(M).Eachstandardcan

beincludedorexcludedinthestandardrecognitionprocessbysoftwarecontrol.TheidentifiedstandardisindicatedbytheStandardSelection(SDT)register.Automaticstandarddetectioncanbeoverriddenbysoftwarecontrolledstandardselection.

TW9912supportsallcommonvideoformatsasshownin

Table1.

Thevideodecoderneedstobeprogrammedappropriatelyforeachofthecompositevideoinputformats.

TABLE1.VIDEOINPUTFORMATSSUPPORTEDBYTHETW9912

FORMAT

LINES

FIELDS

FSC

COUNTRY

NTSC-M

525

60

3.579545MHz

U.S.,manyothers

NTSC-Japan(Note

1)

525

60

3.579545MHz

Japan

PAL-B,G,N

625

50

4.433619MHz

Many

PAL-D

625

50

4.433619MHz

China

PAL-H

625

50

4.433619MHz

Belgium

PAL-I

625

50

4.433619MHz

GreatBritain,others

PAL-M

525

60

3.575612MHz

Brazil

PAL-CN

625

50

3.582056MHz

Argentina

SECAM

625

50

4.406MHz

4.250MHz

France,EasternEurope,MiddleEast,Russia

PAL-60

525

60

4.433619MHz

China

NTSC(4.43)

525

60

4.433619MHz

Transcoding

NTSC50

625

50

3.579545MHz

NOTE:

1. NTSC-Japanhas0IREsetup.

ComponentProcessing

TheTW9912supportsthebrightness,contrast,colorsaturationandHueadjustmentforchangingvideocharacteristics.CbandCrgaincanbeadjustedindependentlyforflexibility.

SHARPNESS

TheTW9912alsoprovidesasharpnesscontrolfunctionthroughcontrolregisters.Itprovidesthecontrolupto

+9db.Thecenterfrequencyoftheenhancementcurveisselectable.Acoringfunctionisprovidedtopreventnoiseenhancement.

COLORTRANSIENTIMPROVEMENT

AprogrammableColorTransientImprovementcircuitisprovidedtoenhancethecolorbandwidth.Lowlevelnoiseenhancementcanbesuppressedbyaprogrammablecoringlogic.Overshootandundershootarealsoremovedbyspecialcircuittopreventfalsecolorgenerationatthecoloredge.

PowerManagement

TheTW9912canbeputintopower-downmodethroughbothsoftwareandhardwarecontrol.TheYandCpathcanbeseparatelypowereddown.

HostInterface

TheTW9912registersareaccessedvia2-WIRESERIALMPUinterface.Itoperatesasaslavedevice.Serialclockanddatalines,SCLKandSDAT,transferdatafromthebusmasteratarateof400Kbits/s.TheTW9912hasoneserialinterfaceaddressselectpinSIADtoprogramuptotwouniqueserialaddressesTW9912.ThisallowsasmanyastwoTW9912tosharethesameserialbus.Resetsignalsarealsoavailabletoresetthecontrolregisterstotheirdefaultvalues.

Cropping

Croppingallowsonlysubsectionofavideoimagetobeoutput.TheVACTIVEsignalcanbeprogrammedtoindicatethenumberofactivelinestobedisplayedinavideofield,andtheHACTIVEsignalcanbeprogrammedtoindicatethenumberofactivepixelstobedisplayedinavideoline.ThestartofthefieldorframeintheverticaldirectionisindicatedbytheleadingedgeofVSYNC.ThestartofthelineinthehorizontaldirectionisindicatedbytheleadingedgeoftheHSYNC.ThestartoftheactivelinesfromtheverticalsyncedgeisindicatedbytheVDELAYregister.ThestartoftheactivepixelsfromthehorizontaledgeisindicatedbytheHDELAYregister.ThesizesandlocationsoftheactivevideoaredeterminedbyHDELAY,HACTIVE,VDELAY,andVACTIVEregisters.Theseregistersare8-bitwide,thelower8-bitsare,respectively,inHDELAY_LO,HACTIVE_LO,VDELAY_LO,andVACTIVE_LO.Theirupper2-bitsharesthesameregisterCROP_HI.

Inorderforthecroppingtoworkproperly,thefollowingequationshouldbesatisfied.

HDELAY+HACTIVE<Totalnumberofpixelsperline.VDELAY+VACTIVE<Totalnumberoflinesperfield

Table2

showssomepopularvideoformatsandtherecommendedregistersettingsforeachformat.TheCCIR601formatreferstothesamplingrateof13.5MHz.TheSQformatfor60Hzsystemreferstothesamplingrateof12.27MHz,andtheSQformatfor50Hzsystemreferstotheuseofsamplingrateof14.75MHz.

TABLE2.SOMEPOPULARVIDEOFORMATS

SCALINGRATIO

FORMAT

TOTALRESOLUTION

OUTPUTRESOLUTION

1:1

NTSCSQNTSCCCIR601

PALSQ

PALCCIR601

780x525

858x525

944x625

864x625

640x480

720x480

768x576

720x576

OutputInterface

ITU-RBT.656

ITU-RBT.656definesstrictEAV/SAVCode,videodataoutputtiming,Hblankingtiming,andVBlankingtiming.Inthismode,VD[7:0]pinsareonlyeffectiveandCLKOpinshouldbeusedfordataclocksignal.EAV/SAVCodeformatisshownasfollows.Bit7offorthbyteinEAV/SAVcodemustbe―1‖inITU-RBT.656standard.

TABLE3.ITU-RBT.656SAVANDEAVCODESEQUENCE

VD7

VD6

VD5

VD4

VD3

VD2

VD1

VD0

1STBYTE

1

1

1

1

1

1

1

1

2NDBYTE

0

0

0

0

0

0

0

0

3RDBYTE

0

0

0

0

0

0

0

0

4THBYTE

1

F

V

H

VXORH

FXORH

FXORV

FXORVXORH

.

ForcompleteITU-RBT.656standard,thefollowingsettingisrecommended.

TABLE4.ITU-RBT.656REGISTERSETUP

REGISTER

525LINESYSTEM

625LINESYSTEM

VDELAY

0x012

0x018

VACTIVE

0x0F4

0x120

HACTIVE

0x2D0

0x2D0

NTSC656

1

0

ITU-RBT.656for525-linesystemhas244videoactivelinesinoddfieldand243videactivelinesinevenfield.NTSC656registerbitcontrolsthisvideoactivelinelength.

CONTROLSIGNALS

TW9912outputsseveralcontrolsignals.VSYNCisverticaltimingcontrolsignals.HSYNCishorizontaltimingcontrolsignals.

VERTICALTIMINGDIAGRAM

Figure2

showstypicalverticaltimingfor60Hz/525linessystem.

Figure3

showstypicalverticaltimingfor50Hz/625linessystem.In

Figure2,

VDELAYregisteris19decimal(0x13)andVACTIVEregisteris241decimal(0x0F1).

Figure3

showstypicalNTSC-Msetting.In

Figure3,

VDEALYregisteris24decimal(0x18)andVACTIVEregisteris286decimal(0x11E).

Figure2

showstypicalPAL-Bsetting.TheleadingedgeofVACTIVEiscontrolledbyVDELAYregistervalue.ThelengthofvideoactivelinesiscontrolledbyVACTIVEregistervalue.Asshownin

Figure2

and

Figure3,

outputvideodatastreamhas2linesverticaldelaycomparedtoinputVIDEOlinetiming.

622

623

624

625

1

2

3

4

5

6

7

8

9

10

11

20

21

22

23

24

25

26

INPUTVIDEO

HSYNC

HACTIVE

FIGURE2.VERTICALTIMINGDIAGRAMFOR50HZ/625LINESYSTEM

VSYNC

624

623

622

FIELD

VACTIVE

621

620

OUTPUTVIDEO

VDELAY

625

1

2

3

4

5

6

7

8

9

...

18

19

20

21

22

23

24

-Oddfield-

1

2

3

4

5

6

7

8

9

10

11

...

20

21

22

23

24

25

26

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

...

333

334

335

336

337

338

339

INPUTVIDEO

HSYNC

VDELAY

1

HACTIVEVSYNCFIELDVACTIVE

OUTPUTVIDEO

308 309 310 311 312 313

314

315

3

2

316

4

317

5

318

6

319

7

320

8

321

9

322

...

...

18

331

19

332

20

333

21

334

22

335

23

336

24

337

TW9912

10

-Evenfield-

525

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

INPUTVIDEO

HSYNCHACTIVE

VSYNC

FIELDVACTIVE

VDELAY

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

525

524

523

OUTPUTVIDEO

-Oddfield-

1 2 3 4 5 6

7 8 9

10 11 12

13 14 15 16

17 18 19

20 21 22

23 24

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

INPUTVIDEO

HSYNCHACTIVE

VSYNC

14

13

12

11

10

9

8

7

6

5

4

3

2

1

FIELDVACTIVE

VDELAY

OUTPUTVIDEO

261 262 263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

16

15

279

17

280

18

281

19

282

20

283

21

284

22

285

TW9912

FIGURE3.VERTICALTIMINGDIAGRAMFOR60HZ/525LINESYSTEM

11

-Evenfield-

TW9912

PAGE

12

HSYNC

TheleadingedgeofHSYNCsignalissynchronizedtoinputVideohorizontalsynctiming.

VSYNC

TheleadingedgeofVSYNCsignalissynchronizedtoverticalsyncpulseofinputVideo.

FIELD

TheFIELDsignalcanbeoutputontheMPOUTpiniftheRTSELregisterselectstheFIELDoutput.

Figure2

and

Figure3

showfieldsignaloutputasdefault.

ClosedCaptioningandExtendedDataServices

2-bytecharacterdata

Clockrun-in

Framecode

FIGURE4.TYPICALCC/EDSSCANLINEWAVEFORM

Line21ClosedCaptioningandline284ExtendedDataServiceof525-linevideosystemisata0.5035MHzbitrate.Line22,line335ClosedCaptioningof625-linevideosystemisatabout0.500MHz.Itcontains14bitsClockRun-inbydoublebitrate,3bitsStartBits,and2bytesdata.Eachofthese2bytesisa7bit+oddparityASCIIcharacterwhichrepresentstextorcontrolcharactersforpositioningordisplaycontrol.ForthepurposesofCCorEDS,onlytheYcomponentofthevideosignalisused.TheTW9912canbeprogrammedtodecodeCCorEDSdatabysettingregister0x1A.SincetheCCandEDSareindependent,therecouldbeoneorbothinaparticularframe.Atypicalwaveformisshownin

Figure4.

CC/EDSdecoderusestheinternallowpassfilteredVBIdatawithADCsamplingrate.CC/EDSBitratefrequencyisgeneratedinternally.

IntheCC/EDSdecodemode,thedecodermonitorstheappropriatescanlineslookingfortheclockrun-inandstartbitspattern.Ifit‘sfound,itstartstrackingClockRun-inFrequencyandchecksthestatusofClockRun-inandstartbits.Someprogrammingmayusethesescanlinesforotherpurpose.Thecaptiondataissampledandloadedintoshiftregisters,andthedataisthentransferredtothecaptiondataFIFO.TheTW9912providesa16x10locationFIFOforstoringCC/EDSdata.OncethevideodecoderdetectsthecorrectstatusofClockRun-in,StartBitsintheCC/EDSsignal,itcapturesthelowbyteofCC/EDSdataatfirstandhighbytenext.DataisstoredintheFIFOlowbytefirstandhighbytenextsequentially.CaptioneddataisavailabletotheuserthroughtheCC_DATAregister(0x1B).Uponbeingplacedinthe10-bitFIFO,twoadditionalbitsareattachedtotheCC/EDSdatabytebyTW9912‘sCC/EDSdecoder.ThesetwobitsindicatewhetherthegivenbytestoredintheFIFOcorrespondstoCCorEDSdataandwhetheritisthehighorlowbyteofCC/EDS.ThesetwobitsareavailabletotheuserthroughtheCC_STATUSregisterbitsCC_EDSandLO_HI(0x1A[1:0]),respectively.AsstoredintheFIFO,LO_HIisbit8andCC_EDSisbit9.Additionally,theTW9912reportsthe

resultsoftheparitycheckinthePARITYbitintheCC_STATUSregister.FIFOcanhold17data.InitiallywhentheFIFOisempty,bitFF_EMPintheCC_STATUSregister(0x1A[2])issetlowindicatingthatnodataisavailableintheFIFO.Subsequently,whendatahasbeenstoredintheFIFO,theFF_EMPbitissettologicalhigh.IftheFIFOreadcycletimeislong,thenFIFOoverflowconditionmayhappen.After17dataarestoredinFIFO,FF_OVFbitinCC_STATUSregister(0x1A[3])becomeshigh.AfterFF_OVFbecomeshigh,anyincomingdatacausesonly17thlocationdatatobeoverwritten.AfterFIFOisreadandFIFOhaslessthan16data,FF_OVFbitbecomeslow.However,onceFF_OVFbitbecomeshighsomedatalossmayhappen.Inthiscase,FIFOmustberesetbythefollowingway(a)or(b).Method(b)ismostoftenused.

ExecuteSoftwareReset(Write0x06[7]=1)

WriteCC_STATUSregisterbits0x1A[6:5]=00

16timesreadCC_DATAregister0x1Bcontinuously

WriteCC_STATUSRegisterbits0x1A[6:5]fortheapplicationagain

TherewillroutinelybeasynchronousreadsandwritestotheCC/EDSFIFO.ThewriteswillbefromtheCC/EDScircuitryandthereadswilloccurasthesystemcontrollerreadstheCC/EDSdatafromTW9912.ThesereadsandwriteswillnotoccuruntilFIFOisinoverflowcondition.TheaverageFIFOReadcycletimemustbeshorterthanClosedCaptioningbytetransmittercycletime.IfeitheroddfieldCloseCaptioningorevenfieldClosedCaptioningisenabled,theaverageFIFOreadcycletimemustbeshorterthan2timeswriteper1framecycle.IfbothoddfieldClosedCaptioningandevenfieldClosedCaptioningareenabled,itmustbeshorterthan4timeswriteper1framecycle.Otherwise,FIFOwillbeinoverflowconditiontheoretically.

TypicalFIFOReadflowsareasfollows.ThisflowiswrittensimilartoClanguagetype.Case:typicalTwo-wireSerialBusMasterwithnormalreadcyclespeed

CONT1: WriteCC_STATUSregisterbits0x1A[6:5]=00Read16timesCC_DATAregister0x1B

WriteCC_STATUSregisterbits0x1A[6:5]fortheapplicationCONT2:ReadCC_STATUSregister0x1A

If(FF_OVFbit==1)gotoCONT1

elseif(FF_EMPbit==0)gotoCONT2orgotoCONT3else{

if(PARITYbit==1){

readCC_DATAregister0x1BAbandonthisCC_DATA

gotoCONT2orgotoCONT3

}

else{

CheckCC_EDSbitandstorefieldinformationreadCC_DATAregister0x1B(store1data)

}

}

CONT3:executeanotherprogramroutinegotoCONT2

TwoWireSerialBusInterface

StartCondition

StopCondition

SDAT

SCLK

FIGURE5.DEFINITIONOFTHESERIALBUSINTERFACEBUSSTARTANDSTOP

DeviceID(1-7)

R/W

Index(1-8)

SDAT

SCLK

StartCondition

Ack

StopCondition

Nack

Ack

Re-start

Condition

R/W

DeviceID(1-7)

Data(1-8)

Ack

FIGURE6.ONECOMPLETEREGISTERREADSEQUENCEVIATHESERIALBUSINTERFACE

DeviceID(1-7)

R/W

Index(1-8)

Data(1-8)

SDAT

SCLK

StartCondition

Ack

Ack

Ack StopCondition

FIGURE7.ONECOMPLETEREGISTERWRITESEQUENCEVIATHESERIALBUSINTERFACE

Thetwowireserialbusinterfaceisusedtoallowanexternalmicro-controllertowritecontroldatato,andreadcontrolorotherinformationfromtheTW9912registers.SCLKistheserialclockandSDATisthedataline.BothlinesarepulledhighbyresistorsconnectedtoVDD33.ICscommunicateonthebusbypullingSCLKandSDATlowthroughopendrainoutputs.Innormaloperation,themastergeneratesallclockpulses,butcontrol