mb2mb2l schematic circuit

1、54321MB2XBlock DiagramSYSTEM DC/DCTPS51120INPUTSOUTPUTSProject PCB P/Ncode :91.4V101.0015V_S53V_S5DCBATOUTCLK GENICS9543053DRevision:-1DSYSTEMDC/DCMAX8743RGB CRTCRT13INPUTSOUTPUTSHost BUS 533/667MHz1D05V_S01D8V_S3LVDSDCBATOUTDDRII 533/667Slot 011DDRII 667 Channel ACalistogaSVIDEOTVOUT 13MAXIM CHARGE

2、RMAX8725GMDDR II 667 Channel BPCIE x 166,7,8,9,10INPUTSOUTPUTSBT+18V 3.0AC1394Ricoh R5C832DMI I/F 100MHzCDCBATOUT5V 100mARF ModuleSD/SDIO/MMCPCI30CardReader22,23MS/MS Pro/xDWebCam3023CPU DC/DCMAX8736AUSB 2.0USB x 3 21INPUTSOUTPUTSICH7-MPCIEVCC_CORE0.8441.3V44ASATADCBATOUTPATAODD20PCB LAYERBBAZALIALP

3、C BusL1:L2:L3:L4:Signal 1 GNDSignal 2Signal 316,17,18,19RealtekLINE INALC883AUDIO CODEC27MIC INKBCL5:L6:VCCSignal 4ENE KB3910SFInternal MIC arrayRicoh R55382629Flash ROM1MBOP AMPOP AMPThermal & Fan31Mini-Card802.11 b/g 24Launch Button15Lux Pad 30Int. KB30G1432G1411New Card2828AA26G792202CHWistron Co

4、rporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,SPEAKERLINE OUTTaipei Hsien 221, R.O.C.TitleBlock DiagramSPDIFSize A3Document NumberRev-1MB2XDate: Tuesday, February 06, 2007Sheet 1of3954321PCIE+USB 2.0PCIE+USB 2.0MDC MODEM24RJ11 CONNHDD 2010/100RTL8101E 25RJ45 CONN 26139423DDRIISlot 1533/66711LCD

5、14Intel CPUYonah/Merom4,5ACalistoga Strapping ConfigurationBCSpectrumDICH7M Integrated Pull-up and Pull-down ResistorsESignalsandpage 7125CVSpreadSelectpage 3ICH6-M EDS 143080.8V144ICH7M IDE Integrated Series33TerminationResistorsPCI RoutingNOTE: All strap signals are sampled with respect to the lea

6、ding edge of the Alviso GMCH PWORK In signal.ITPDebugConn.1D05V_S0For BOM1)SPR(2,4,7) 34.49Q01.0022)H16,H21 34.4Q102.0013)U16 CS.4R671.0014)U24 CS.4R671.011History11.18.2004: mini card not ready22R40 54D9R2F-L1-GPR34 39D2R2R3654D9R2F-L1-GPPCN12914 XDP_TDI24 XDP_TMS4 XDP_TRST#3454 XDP_TCKDY R37 122D6

7、R2F-L1-GP67TDO_FLEX#24 XDP_TDO3 CLK_XDP#3 CLK_XDPCLK_XDP#8CLK_XDP910XDP_TCKDY11RESET_FLEX#12124,6 H_CPURST#R3922D6R2F-L1-GP134 XDP_BPM#514154 XDP_BPM#4R35 680R2J-3-GPR3827D4R2F-L1-GP163D3V_S0174 XDP_BPM#018194 XDP_BPM#120R41220R2J-L2-GP214 XDP_BPM#22212314 XDP_BPM#32425Wistron Corporation21F, 88, Se

8、c.1, Hsin Tai Wu Rd., Hsichih,4,17 XDP_DBRESET#26271D05V_S028Taipei Hsien 221, R.O.C.DY30DYC40TitleSCD1U16V2ZY-2GP ITPMLX-CON28-URev-1Size A3Document NumberMB2XDate: Tuesday, February 06, 2007Sheet 2of39ABCDE212121 21212 121IDSELIRQREQ/GNTR5C832250DD15:0, DIOW#, DIOR#, DREQ, DDACK#, IORDY, DA2:0, DC

9、S1#, DCS3#, IDEIRQapproximately 33 ohmACZ_BIT_CLK, DPRSLP#, EE_DIN, EE_DOUT, GNT5#/GPO17, GNT6#/GPO16, LDRQ1/GPI41,LAD3:0#/FB3:0#, LDRQ0, PME#, PWRBTN#, TP3ICH6 internal 20K pull-upsLAN_RXD2:0ICH6 internal 10K pull-upsACZ_RST#, ACZ_SDIN2:0, ACZ_SYNC, ACZ_SDOUT, ACZ_BITCLK, DPRSLPVR, SPKR, EE_CS,ICH6

10、 internal 20K pull-downsUSB7:0P,NICH6 internal 15K pull-downsDD7, SDDREQICH6 internal 11.5K pull-downsLAN_CLKICH6 internal 100K pull-downsSS3SS2SS1SS0Spread Amount%0000-0.80001-1.00010-1.250011-1.50100-1.750101-2.00110-2.50111-3.01000+-0.31001+-0.41010+-0.51011+-0.61100+-0.81101+-1.01110+-1.251111+-

11、1.5Pin NameStrap DescriptionConfigurationCFG2:0FSB Frequency Select001 = FSB533011 = FSB667others = ReservedCFG4:3ReservedCFG5DMI x2 Select0 = DMI x21 = DMI x4 (Default)CFG60=Moby Dick 1=CalistogaCFG7CPU Strap0 = Reserved1 =Mobile CPU(Default)CFG8ReservedCFG9PCI Express Graphics Lane Reversal0 = Rev

12、erse Lanes,15-0,14-1 ect.1= Normal operation(Default):Lane Numbered in orderCFG11:10ReservedCFG13:12ReservedCFG15:14ReservedCFG16FSB Dynamic ODT0 = Dynamic ODT Disabled1 = Dynamic ODT Enabled (Default)CFG17Global R-comp Disable (All R-comps)0 = All R-comp Disable1 = Normal Operation (Default)CFG18VC

13、C Select0 = 1.05V (Default) 1 = 1.5VCFG19DMI Lane Reversal0 = Normal operation (Default):lane Numbered in order1 =Reverse Lane,4-0,3-1 ect.CFG20SDVO/PCIEConcurrent0 = Only SDVO or PCIE x1 is operational (Default)1 =SDVO and PCIE x1 are operating simultaneously via the PEG portSDVOCRTL_DATASDVO Prese

14、nt0 = No SDVO device present (Default) 1= SDVO device presentABCDE3D3V_S03D3V_S03D3V_S02 3D3V_APWR_S02 3D3V_48MPWR_S03D3V_CLKGEN_S01 R3871 R1451R14620R3-0-U-GPC401C221SC4D7U10V5ZY-3GPC220C218C219 SCD1U16V2ZY-2GPC238C400C199C403C201C402C399 SCD1U16V2ZY-2GPSCD1U16V2ZY-2GP SC4D7U10V5ZY-3GPSC10U10V5ZY-1

15、GPSCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP3D3V_S044H/L : CPU_ITP/SRC10R12310KR2J-3-GPDYPCLK_FWH_2 33R2J-2-GP 2 1 R383 PCLK_FWH 3133R2J-2-GP 233R2J-2-GP 2 1 R382 1 R380R12010KR2J-3-GPPCLK_PCM_1 PCLK_KBC_1 SS_SELPCLK_PCM 22PCLK_KBC 293D3V_48MPWR_S

16、03D3V_APWR_S0FSA3D3V_CLKGEN_S0CPU_SEL2_11 2CPU_SEL26MHzCPU_SEL1R5462K2R2J-2-GPPM_STPCPU# 17CLK_EN# 33R124 10KR2J-3-GPDYR122 10KR2J-3-GPCLK_CPU_BCLK 4CLK_CPU_BCLK# 4SRN33J-5-GP-UU21CLK_MCH_BCLK 6CLK_MCH_BCLK# 6 CPU_SEL0 212K2R2J-2-GPR375SRN33J-5-GP-UFSAR373 21 33R2J-2-GP17 CLK48_ICH3D3V_S0 CLK_PCIE_N

17、EW_1 2 CLK_PCIE_NEW_1# 1 RN234SRN33J-5 GP-UCLK_PCIE_NEW 26CLK_PCIE_NEW# 261 DY2 1KR2J-1-GP2 1KR2J-1-GPCLKREQ1#R3784650CLKREQ1#SRCT1R143 10KR2J-3-GPR1441 DYCLKREQ2#CLK_PCIE_NEW_12652CLKREQ2#SRCT23R1261 DY2 1KR2J-1-GPCLKREQ3#2855CLK_MCH_3GPLL_1CLK_MCH_3GPLL_1 2343CLK_MCH_3GPLL 7CLK_MCH_3GPLL# 7CLKREQ3

18、#SRCT31 DY2 1KR2J-1-GPCLKREQ4#CLK_PCIE_SATA_1CLK_MCH_3GPLL_1# 1R3795758CLKREQ4#SRCT4SBR1271 DY2 1KR2J-1-GPCLKREQ5#CLK_PCIE_ICH_1RN3SRN33J-5 GP-U2960CLKREQ5#SRCT51 2CLKREQ2#R3811 DY2 1KR2J-1-GPCLKREQ6#6263CLK_PCIE_SATA_1 234SRN33 -5-GP-U 3426 CONN_CLKREQ#CLK_PCIE_SATA 16CLK_PCIE_SATA# 16CLKREQ6#SRCT6

19、2 1KR2J-1-GPCLK_PCIE_LAN_1CLK_PCIE_SATA_1# 1R142 0R2J-2-GPR1211 CLKREQ7#3866CLKREQ7#SRCT7R3851 DY2 1KR2J-1-GPCLKREQ8#CLK_PCIE_MINI_1RN37170CLKREQ8#SRCT8CLK_PCIE_ICH_1R1651 DY2 1KR2J-1-GPCLKREQ9#7223CLK_PCIE_ICH 17CLK_PCIE_ICH# 17CLKREQ9#SRCT9UMA ONLY CLK_PCIE_ICH_1#1RN3SRN33J-5-GP-UDREFSSCLK_1 DREFS

20、SCLK_1#SRN33J-5-GP-U51537 DREFSSCLK7 DREFSSCLK#4748LCD100/96/SRC0_T LCD100/96/SRCO_CSRCC1 SRCC2 SRCC3 SRCC4 SRCC5 SRCC6 SRCC7 SRCC8 SRCC9CLK_PCIE_NEW_1#CLK_MCH_3GPLL_1#56 CLK_PCIE_LAN_1 59CLK_PCIE_SATA_1#23CLK_PCIE_LAN 25CLK_PCIE_LAN# 25CLK_PCIE_LAN_1#DREFCLK_1 DREFCLK#_1 SRN33J-5-GP-U434461CLK_PCIE

21、_ICH_1# 1 47DREFCLKDOTT_96MHZ/27MHZ_NONSPREAD DOTC_96MHZ/27MHZ_SPREADRN35SRN33 -5-GP-U64677 DREFCLK#C200CLK_PCIE_LAN_1#CLK_PCIE_MINI 24CLK_PCIE_MINI# 2469CLK_PCIE_MINI_1#GEN_XTAL_INSRN33J-5-GP-U1 220192X1 X2GEN_XTAL_OUT_R1 2 GEN_XTAL_OUTP50V2JN-2-GPR1300R2J-2-GPX1162511,19 SMBC_ICH11,19 SMBD_ICHPM_S

22、TPPCI# 17CLK_ICHPCI 17SMBCLK SMBDATPCI_SRC_STOP# ITP_EN/PCICLK_F031818M-30GPITP_EN21173733R2J-2-GPR1252 C202SC39P50V2JN-1GP22ICS954305EKLF-GPCLK_MCH_BCLK_1CLK_CPU_BCLK_1GEN_REF 21CLK_ICH14 1733R2J-2-GPR384CLK_MCH_BCLK_1#GEN_IREF2 1CLK_CPU_BCLK_1#475R2F-L1-GPR386CLK_XDP_1234SRN33J-5-GP-UCLK_XDP 2CLK_

23、XDP# 21D05V_S0CLK_XDP_1#1RN28DYDREFCLK#23DREFCLK14R3771KR2J-1-GPRN10SRN49D9F-GPR374R128 CLK_PCIE_NEW23 CLK_CPU_BCLK14 CLK_PCIE_NEW#1RN48 CLK_CPU_BCLK#2DY43 DREFSSCLK#23SRN49D9F-GPRN30SRN49D9F-GPDREFSSCLKDUMMY-R2DUMMY-R214RN8SRN49D9F-GPCPU_SEL0 4,7CLK_PCIE_LAN CLK_PCIE_LAN#CLK_MCH_BCLK CLK_MCH_BCLK#2

24、3141243CPU_SEL1 4,7RN55SRN49D9F-GPRN49SRN49D9F-GPCPU_SEL2 4,7 CLK_PCIE_SATA2 CLK_PCIE_SATA#1RN533411FS_C FS_B FS_AR376DUMMY-R2R372R1291KR2J-1-GP 1KR2J-1-GPDYDYCPUSRN49D9F-GP000001266M133M CLK_PCIE_ICH2 CLK_PCIE_ICH#1RN543 CLK_MCH_3GPLL2 CLK_MCH_3GPLL#1344001111110011010101200M166M333M100M400MReserve

25、dSRN49D9F-GPRN52SRN49D9F-GPCLK_PCIE_MINI CLK_PCIE_MINI#14CLK_XDP CLK_XDP#2323RN56SRN49D9F-GP14RN50SRN49D9F-GPDYABCDE2121212121121212121 2 1212121212111146554491CPUCLKT1 CPUCLKT0VDDSRC VDDSRC VDDSRC VDDSRC1013CPUCLKC1 CPUCLKC0213036VDDPCI VDDPCI65CPUT_ITP/SRCT10 CPUC_ITP/SRCC107401812VDDA VDD48 VDDRE

26、F VDDCPU922IREF REF12732333421PCICLK1 PCICLK2 PCICLK3PCICLK4/FCTSEL173842GND GNDA GND481521GNDCPU GNDREF412345USB_48MHZ/FSLA REF0/FSLC/TEST_SEL FSLB/TEST_MODE3135GNDPCI GNDPCI21684 24CPU_STOP# 39GNDSRC GNDSRCVTT_PWRGD#/PD2121212121Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei H

27、sien 221, R.O.C.TitleClock Generator (ICS954305EKLF)Size A3Document NumberMB2XRev-1Date: Tuesday, February 06, 2007Sheet 3of39SC27 X-14D1CLK_PCIE_MINI_114CLK_PCIE_MINI_1# 23RN363241RN253241RN24CLK_CPU_BCLK_11CLK_CPU_BCLK_1#2RN29 CLK_MCH_BCLK_11 CLK_MCH_BCLK_1#2RN272 ITP_ENSS_SELH/L: 100/IN (3D3V_S0)

28、EN (6218_PGOOD)OUT (VTT_PWRGD#)HLHXHHi - Z0R3-0-U-GP0R3-0-U-GPABCDETP7 TPAD301 U49A1D05V_S0H_A#3J4H1 E2H_ADS# H_BNR# H_BPRI#6666 H_A#31.3A3#A4#A5#A6#A7#A8#A9#A10#A11#A12#A13#A14#A15#A16# ADSTB0#ADS# BNR# BPRI#H_A#44L44H_A#5M3G5H_A#6K5H_A#7R9456R2J-4-GPM1H5 F21 E1 H_DEFER# 6H_DRDY# 6H_DBSY# 6DEFER# D

29、RDY# DBSY#H_A#8N2H_A#9J1H_A#10N3H_DINV#3.0 6H_DSTBN#3.0 6H_DSTBP#3.0 6H_A#11P5F1BR0#H_BREQ#0 6H_IERR#H_A#12P2H_A#13L1D20IERR# INIT#H_A#14P4B3H_INIT# 16H_A#15P1H_A#16R1H4H_LOCK# 6H_CPURST# 2,6H_RS#2.0 6H_D#63.0 6LOCK#U49BL26 H_ADSTB#0 6 H_REQ#4.0B1 F3 H_RS#0 F4 H_RS#1 G3 H_RS#2 G2 H_D#0E22AA23H_D#32R

30、ESET# RS0#RS1#RS2# TRDY#D0#D1#D2#D3#D4#D5#D6#D7#D8#D9#D10#D11#D12#D13#D14#D15# DSTBN0# DSTBP0# DINV0#D32#D33#D34#D35#D36#D37#D38#D39#D40#D41#D42#D43#D44#D45#D46#D47# DSTBN2# DSTBP2# DINV2#H_D#1H_D#33 H_REQ#0 K3 H_REQ#1 H2 H_REQ#2 K2 H_REQ#3 J3 H_REQ#4 L5F24AB24REQ0# REQ1# REQ2# REQ3# REQ4#H_D#2 H_D#

31、3H_D#34 H_D#35E26V24H22V26H_D#4H_D#36 H_D#37F23W25H_TRDY# 6 H_D#5 G25U23G6 E4 H_D#6 H_D#7E25U25H_D#38 H_D#39H_HIT#6H_HITM#6HIT# HITM#H_A#17Y2E23U22A17#A18#A19#A20#A21#A22#A23#A24#A25#A26#A27#A28#A29#A30#A31#H_A#18H_D#8H_D#40U5K24AB25H_A#19R3AD4XDP_BPM#0H_D#9G24W22H_D#41XDP_BPM#0 2XDP_BPM#1 2XDP_BPM#

32、2 2XDP_BPM#3 2XDP_BPM#4 2XDP_BPM#5 2XDP_TCK 2XDP_TDI 2XDP_TDO 2XDP_TMS 2XDP_TRST# 2BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#H_A#20XDP_BPM#1H_D#10H_D#42W6AD3J24Y23H_A#21XDP_BPM#2H_D#11H_D#43U4AD1J23AA26H_A#22Y5AC4XDP_BPM#3H_D#12H26Y26H_D#44H_A#23XDP_BPM#4H_D#13H_D#45U2AC2F26Y221D

33、05V_S0H_A#24XDP_BPM#5H_D#14 H_D#15H_D#46 H_D#47R4AC1K22AC263H_A#25T5 T3AC5 XDP_TCK H25AA243H_A#26AA6 XDP_TDIH23W246 H_DSTBN#06 H_DSTBP#0 6 H_DINV#0H_DSTBN#2 6H_DSTBP#2 6H_DINV#2 6H_A#27 XDP_TDOR95 68R2-GPW3 W5AB3G22Y25H_A#28AB5 XDP_TMS J26V23H_A#29Y4AB6XDP_TRST#H_A#30XDP_DBRESET#W2C20XDP_DBRESET# 2,

34、17H_A#31Y1H_D#16N22AC22H_D#48D16#D17#D18#D19#D20#D21#D22#D23#D24#D25#D26#D27#D28#D29#D30#D31# DSTBN1# DSTBP1# DINV1#D48#D49#D50#D51#D52#D53#D54#D55#D56#D57#D58#D59#D60#D61#D62#D63# DSTBN3# DSTBP3# DINV3#CPU_PROCHOT#_1V4D2112H_D#17K25AC23H_D#496 H_ADSTB#116 H_A20M#16 H_FERR#16 H_IGNNE#CPU_PROCHOT# 33

35、ADSTB1#PROCHOT#R101 DY 0R2J-2-GPH_D#18H_D#50A24P26AB22THERMDA THERMDCH_THERMDA 20H_THERMDC 20PM_THRMTRIP-A# 7H_D#19H_D#51A6A25R23AA21A20M#A5H_D#20L25AB21H_D#52FERR#H_D#21H_D#53C4C7L22AC25IGNNE#THERMTRIP#2H_D#22 H_D#23H_D#54 H_D#551PM_THRMTRIP-I# 16L23AD20D5R77 0R0402-PADM23AE2216 H_STPCLK#16 H_INTR1

36、6 H_NMI16 H_SMI#STPCLK#H_D#24H_D#56C6P25AF23LINT0 LINT1 SMI# H_D#25H_D#57B4A22 A21CLK_CPU_BCLK 3CLK_CPU_BCLK# 3P22AD24BCLK0 BCLK1A3H_D#26P23AE21H_D#58H_D#27H_D#59T24AD21TPAD30 TP12 TPAD30 TP15 TPAD30 TP13 TPAD30 TP14 TPAD30 TP8 TPAD30 TP9 TPAD30 TP10 TPAD30 TP11 TPAD30 TP1 TPAD30 TP2H_D#28H_D#601AA1

37、R24AE25RSVD01 RSVD02 RSVD03 RSVD04 RSVD05 RSVD06 RSVD07 RSVD08 RSVD09 RSVD101AA4T221TP21 TPAD30H_D#29L26AF25H_D#61RSVD121D05V_S0H_D#30 H_D#31H_D#62 H_D#631AB2T25AF221AA3N24AF261M4D21TP5 TPAD30M24AD23H_DSTBN#3 6H_DSTBP#3 6H_DINV#3 62RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD206 H_DSTBN#1TP

38、6 TPAD30TP4 TPAD30TP3 TPAD30 TP16 TPAD30 TP20 TPAD30 TP19 TPAD30 TP18 TPAD30R1051N5F6 1 D3 1 C1 1 AF1 1 D22N25AE246 H_DSTBP#11KR2F-3-GP 6 H_DINV#11T2M26AC201V3CPU_GTLREF0R26 COMP01B2AD261GTLREFMISCCOMP0 COMP1 COMP2 COMP3U26 COMP1R102 12 27D4R2F-L1-GP1C31C231U1COMP2R103 12 54D9R2F-L1-GP22TPAD30 TP17R

39、104 2KR2F-3-GP1TEST1COMP3R80 2 27D4R2F-L1-GP1B25C2412R356DY 1 R357C26V11 TEST1RSVD111KR2J-1-GP2TEST2 D25R8154D9R2F-L1-GPBGA479-SKT6-GPU2E5 B5 D24 D6H_DPRSTP# 16H_DPSLP# 16H_DPWR# 6H_PWRGD 16H_CPUSLP# 6,16TEST2DPRSTP# DPSLP# DPWR# PWRGOOD SLP#PSI#51R2J-2-GPB223,7 CPU_SEL062.10079.001BSEL0 BSEL1 BSEL2

40、B23D73,73,7CPU_SEL1 CPU_SEL2C21AE6PSI#33BGA479-SKT6-GPU262.10079.0011D05V_S01D05V_S0R89XDP_TDI12H_PWRGD12200R2J-L1-GP150R2J-L1-GP-UR7911Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, R.O.C.TitleCPU (1 of 2)Rev-1Size A3Document NumberMB2XDate: Tuesday, February 06, 2007

41、Sheet 4of39ABCDEDATA GRP 0DATA GRP 1ADDR GROUP 0ADDR GROUP 1RESERVEDH CLKTHERM XDP/ITP SIGNALSCONTROL212 121 2 1DATA GRP 3DATA GRP 2Layout Note: 0.5 max length.Layout Note:Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5 .Comp1, 3 connect with Zo=55 ohm, make trace length shorte

42、r than 0.5 .Place testpoint on H_IERR# with a GND 0.1 awayABCDEVCC_CORE_S0U49DA4P6VSS001 VSS002 VSS003 VSS004 VSS005 VSS006 VSS007 VSS008 VSS009 VSS010 VSS011 VSS012 VSS013 VSS014 VSS015 VSS016 VSS017 VSS018 VSS019 VSS020 VSS021 VSS022 VSS023 VSS024 VSS025 VSS026 VSS027 VSS028 VSS029 VSS030 VSS031 VSS032 VSS033 VSS034 VSS035 VSS036 VSS037 VSS038 VSS039 VSS040 V