自動(dòng)洗衣機(jī)控制器ddpp課程設(shè)計(jì).doc

電子科技大學(xué)數(shù)字設(shè)計(jì)原理與實(shí)踐課程設(shè)計(jì)報(bào)告題目：自動(dòng)洗衣機(jī)控制器姓名：魏玉峰學(xué)號(hào)：20121710100091、 任務(wù)與要求設(shè)計(jì)內(nèi)容：1）進(jìn)行需求分析，確定總體框架； 2）畫出邏輯電路圖； 3）對(duì)設(shè)計(jì)電路進(jìn)行仿真；設(shè)計(jì)要求：假設(shè)自動(dòng)洗衣機(jī)的定時(shí)操作順序是，洗衣10min，排水2min，脫水3min，然后停止。設(shè)計(jì)出這個(gè)自動(dòng)洗衣機(jī)的控制器。設(shè)計(jì)提示：本設(shè)計(jì)有4個(gè)狀態(tài)，分別為初始狀、洗衣系統(tǒng)、排水系統(tǒng)、和脫水狀態(tài)。當(dāng)有復(fù)位信號(hào)時(shí)，系統(tǒng)進(jìn)入循環(huán)控制狀態(tài)，依次執(zhí)行操作，可從信號(hào)燈觀察到所處狀態(tài)。2、 設(shè)計(jì)思路的介紹 分析：洗衣機(jī)開機(jī)后，自動(dòng)進(jìn)入循環(huán)狀態(tài)，分別進(jìn)行洗衣10min，排水2min，脫水3min的操作，然后回到待機(jī)狀態(tài)。任意期間輸入復(fù)位信號(hào)都會(huì)重新開始進(jìn)入循環(huán)控制狀態(tài)。LED指示燈與當(dāng)前操作對(duì)應(yīng)，處于發(fā)光狀態(tài)。 由以上要求可知，所有狀態(tài)共4種，分別為初始狀態(tài)、洗衣狀態(tài)、排水狀態(tài)、和脫水狀態(tài)，即用1個(gè)74163計(jì)時(shí)器，輸出的狀態(tài)與上面一一對(duì)應(yīng)，具體見下表：0000待機(jī)0001洗衣狀態(tài)0010洗衣狀態(tài)0011洗衣狀態(tài)0100洗衣狀態(tài)0101洗衣狀態(tài)0110洗衣狀態(tài)0111洗衣狀態(tài)1000洗衣狀態(tài)1001洗衣狀態(tài)1010洗衣狀態(tài)1011排水狀態(tài)1100排水狀態(tài)1101脫水狀態(tài)1110脫水狀態(tài)1111脫水狀態(tài)故可根據(jù)上表分別選擇輸出時(shí)的74163對(duì)應(yīng)輸出接口。三、總體方案的選擇 經(jīng)過(guò)多次選擇與比較最終選擇74163,7400來(lái)完成電路實(shí)現(xiàn)計(jì)時(shí)功能。將時(shí)鐘信號(hào)設(shè)為1/60hz，即每分鐘一個(gè)上升沿。電路中采用16個(gè)4輸入與非門，1個(gè)12輸入與非門，1個(gè)2輸入與非門，1個(gè)3輸入與非門。把每一個(gè)4輸入與非門的四個(gè)角分別于74163的Qd、Qc、Qb、Qa相連，而每一個(gè)4輸入與非門分別對(duì)應(yīng)一個(gè)74163的輸出狀態(tài)。當(dāng)所輸出狀態(tài)對(duì)應(yīng)了洗衣機(jī)狀態(tài)時(shí)，總輸出狀態(tài)將產(chǎn)生變化，從而進(jìn)行當(dāng)前操作，具體電路圖設(shè)計(jì)如下： Clk為時(shí)鐘信號(hào)1/60hzInput為開關(guān)按鈕Clr為復(fù)位按鈕Standby代表當(dāng)前為待機(jī)狀態(tài)Washing代表當(dāng)前為洗衣狀態(tài)Drainage代表當(dāng)前為排水狀態(tài)Dehydration代表當(dāng)前為洗衣狀態(tài)四、Verilog HDL 代碼module try3(clk,input,clr,Standby,Washing,Drainage,Dehydration);inputclk;inputinput;inputclr;outputStandby;outputWashing;outputDrainage;outputDehydration;wireSYNTHESIZED_WIRE_114;wireSYNTHESIZED_WIRE_115;wireSYNTHESIZED_WIRE_2;wireSYNTHESIZED_WIRE_116;wireSYNTHESIZED_WIRE_117;wireSYNTHESIZED_WIRE_5;wireSYNTHESIZED_WIRE_6;wireSYNTHESIZED_WIRE_7;wireSYNTHESIZED_WIRE_8;wireSYNTHESIZED_WIRE_9;wireSYNTHESIZED_WIRE_10;wireSYNTHESIZED_WIRE_12;wireSYNTHESIZED_WIRE_13;wireSYNTHESIZED_WIRE_16;wireSYNTHESIZED_WIRE_17;wireSYNTHESIZED_WIRE_18;wireSYNTHESIZED_WIRE_23;wireSYNTHESIZED_WIRE_24;wireSYNTHESIZED_WIRE_25;wireSYNTHESIZED_WIRE_34;wireSYNTHESIZED_WIRE_36;wireSYNTHESIZED_WIRE_38;wireSYNTHESIZED_WIRE_39;wireSYNTHESIZED_WIRE_42;wireSYNTHESIZED_WIRE_43;wireSYNTHESIZED_WIRE_44;wireSYNTHESIZED_WIRE_51;wireSYNTHESIZED_WIRE_53;wireSYNTHESIZED_WIRE_78;wireSYNTHESIZED_WIRE_84;wireSYNTHESIZED_WIRE_85;wireSYNTHESIZED_WIRE_86;wireSYNTHESIZED_WIRE_88;wireSYNTHESIZED_WIRE_90;wireSYNTHESIZED_WIRE_91;wireSYNTHESIZED_WIRE_118;wireSYNTHESIZED_WIRE_95;wireSYNTHESIZED_WIRE_96;wireSYNTHESIZED_WIRE_97;wireSYNTHESIZED_WIRE_98;wireSYNTHESIZED_WIRE_99;wireSYNTHESIZED_WIRE_100;wireSYNTHESIZED_WIRE_101;wireSYNTHESIZED_WIRE_102;wireSYNTHESIZED_WIRE_103;wireSYNTHESIZED_WIRE_104;wireSYNTHESIZED_WIRE_105;wireSYNTHESIZED_WIRE_106;wireSYNTHESIZED_WIRE_107;wireSYNTHESIZED_WIRE_108;wireSYNTHESIZED_WIRE_112;wireSYNTHESIZED_WIRE_113;74163 b2v_inst(.ENT(input),.CLRN(clr),.CLK(clk),.ENP(input),.LDN(input),.QA(SYNTHESIZED_WIRE_115),.QB(SYNTHESIZED_WIRE_116),.QC(SYNTHESIZED_WIRE_117),.QD(SYNTHESIZED_WIRE_114);assignSYNTHESIZED_WIRE_105 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_2 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_113 = (SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6 & SYNTHESIZED_WIRE_7 & SYNTHESIZED_WIRE_8);assignSYNTHESIZED_WIRE_100 = (SYNTHESIZED_WIRE_9 & SYNTHESIZED_WIRE_10 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_12);assignSYNTHESIZED_WIRE_102 = (SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_16);assignSYNTHESIZED_WIRE_101 = (SYNTHESIZED_WIRE_17 & SYNTHESIZED_WIRE_18 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_118 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_23 & SYNTHESIZED_WIRE_24);assignSYNTHESIZED_WIRE_103 = (SYNTHESIZED_WIRE_25 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_108 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_104 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_36);assignSYNTHESIZED_WIRE_96 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_38 & SYNTHESIZED_WIRE_39 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_95 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44);assignSYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_7 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_6 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_90 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_91 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_97 = (SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_88 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_84 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_86 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_85 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_51 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_53 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_12 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_18 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_114;assignSYNTHESIZED_WIRE_43 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_42 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_112 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_117;assignSYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_107 = (SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_78 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_116;assignSYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_78 = SYNTHESIZED_WIRE_115;assignSYNTHESIZED_WIRE_98 = (SYNTHESIZED_WIRE_84 & SYNTHESIZED_WIRE_85 & SYNTHESIZED_WIRE_86 & SYNTHESIZED_WIRE_116);assignSYNTHESIZED_WIRE_99 = (SYNTHESIZED_WIRE_88 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_90 & SYNTHESIZED_WIRE_91);assignWashing = (SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_95 & SYNTHESIZED_WIRE_96 & SYNTHESIZED_WIRE_97 & SYNTHESIZED_WIRE_98 & SYNTHESIZED_WIRE_99 & SYNTHESIZED_WIRE_100 & SYNTHESIZED_WIRE_101 & SYNTHESIZED_WIRE_102 & SYNTHESIZED_WIRE_103);assignDrainage = (SYNTHESIZED_WIRE_104 & SYNTHESIZED_WIRE_105);assignDehydration =