DM9000單片機(jī)驅(qū)動(dòng)代碼.doc

標(biāo)題：DM9000單片機(jī)驅(qū)動(dòng)代碼2010-09-12 10:16:07/*dm9000.c writer zxw 2010.3.26*/#includedm9000.h#include def.h#include ARP.h/*/*函數(shù)宏定義*/#define XIO_In16(InputPtr) (*(volatile unsigned int*)(InputPtr)#define XIO_In8(InputPtr) (*(volatile unsigned char*)(InputPtr)#define XIO_In32(InputPtr) (*(volatile unsigned long*)(InputPtr)#define XIO_Out16(OutputPtr,Value) (*(volatile unsigned int *)(OutputPtr)=(Value)#define DM_ADD (*(volatile U16*)0x20000300)#define DM_CMD (*(volatile U16*)0x20000304)/*/*函數(shù)申明*/unsigned int ior(unsigned long BaseAddress,unsigned int reg);unsigned int Dm9000_Read(unsigned long BaseAddress,int type);void Dm9000_Write(unsigned long BaseAddress,int type,unsigned int Value);void iow(unsigned long BaseAddress,unsigned int reg,unsigned int data);void delay(unsigned int t);void Dm9000_reset(void);void clear_interrupts(void);void phy_write(unsigned long BaseAddress,unsigned int reg,unsigned int value);void Dm9000_init(unsigned long BaseAddress);void TransmitPacket(unsigned char *data_ptr,unsigned short tx_len);unsigned char ReceivePacket(unsigned char *data_ptr);/*定義接受數(shù)組和發(fā)送數(shù)組*/unsigned char data_ptrRMAX_PACKET_SIZE;/unsigned char data_ptrTMAX_PACKET_SIZE;unsigned char ether_addr06=8,90,90,90,90,90;/unsigned char ether_addr16=8,90,90,90,90,90;/*函數(shù)實(shí)體*/void dm9000_reg_write(U8 reg, U8 data)delay(1000);/之前定義的微妙級(jí)延時(shí)函數(shù)，這里延時(shí)20usDM_ADD = reg;/將寄存器地址寫(xiě)到INDEX端口delay(1000);DM_CMD = data;/將數(shù)據(jù)寫(xiě)到DATA端口，即寫(xiě)進(jìn)寄存器/*/U8 dm9000_reg_read(U8 reg)delay(1000);DM_ADD = reg;delay(1000);return DM_CMD;/將數(shù)據(jù)從寄存器中讀出unsigned int ior(unsigned long BaseAddress,unsigned int reg) delay(100);Dm9000_Write(BaseAddress,IO_addr,reg); delay(100);return Dm9000_Read(BaseAddress,IO_data);unsigned int Dm9000_Read(unsigned long BaseAddress,int type)return XIO_In16(BaseAddress+type);void iow(unsigned long BaseAddress,unsigned int reg,unsigned int data)delay(100);Dm9000_Write(BaseAddress,IO_addr,reg);delay(100);Dm9000_Write(BaseAddress,IO_data,data);void Dm9000_Write(unsigned long BaseAddress,int type,unsigned int value)XIO_Out16(BaseAddress+type,value);void Dm9000_reset(void)iow(BaseAddress1,DM9000_NCR,0x03);delay(100);iow(BaseAddress1,DM9000_NCR,0x00);iow(BaseAddress1,DM9000_NCR,0x03);delay(100);iow(BaseAddress1,DM9000_NCR,0x00);void delay(unsigned int t)while(t-);void clear_interrupts(void)iow(BaseAddress1,DM9000_IMR,0x80);void phy_write(unsigned long BaseAddress,unsigned int reg,unsigned int value)/*set phy register address into EPAR REG.0CH*/iow(BaseAddress,0x0c,reg|0x40);/*phy register address setting,and Dm9000_phy 0ffset=0x40*/*fill phy write data into EPDR REG.0xEH®.0DH*/*phy data hign_byte*/iow(BaseAddress,0x0E,(value8)&0xff);/*phy data low_byte*/iow(BaseAddress,0x0D,value&0xff);/*issue phy+write commmand=0x0a into EPCR REG.0BH*/*clear phy commmand first*/iow(BaseAddress,0x0B,0x08);/*issue phy+write command*/Dm9000_Write(BaseAddress,IO_data,0x0A);delay(25);/*clear phy command again*/Dm9000_Write(BaseAddress,IO_data,0x08);/*wait 130us(20us)for phy+write completion*/delay(25);/*DM9000初始化*/void Dm9000_init(unsigned long BaseAddress)/*initialize Dm9000 LAN chip*/unsigned int i;/*set the internal phy power_on(GPIOs normal setting)*/iow(BaseAddress,0x1E,0x01);iow(BaseAddress,DM9000_GPCR,0x01);delay(100);/*GPCR REG.1E=1 selected GPIO0output port for internal phy*/ iow(BaseAddress,0x1F,0x00);iow(BaseAddress,DM9000_GPR,0x00);delay(100);/*GPR REG.1F GPIO0 Bit0=0 to active interal phy*/*wait 2ms for phy powner_up ready*/*software-reset */Dm9000_reset();delay(100);/*set GPIO0=1 then GPIO=0 to turn off and on the internal phy*/*GPR Bit0=1 turn-off phy*/ iow(BaseAddress,0x1f,0x01);/*GPR Bit0=0 to active phy*/ iow(BaseAddress,0x1f,0x00);/*wait 4ms for phy powner-up*/ delay(10000);/*set phy operation mode*/*reset phy:registers back to the default states */ phy_write(BaseAddress,0,phy_reset);/*wait30us for phy software-reset ok*/ delay(350);/*turn off phy reduce -powner-down mode only*/ phy_write(BaseAddress,16,0x404);/ phy_write(BaseAddress,4,phy_txab);/*set phy TX ability:ALL+Flow_control*/ phy_write(BaseAddress,0,0x1200);/*phy auto-NEGO re-start enable(RESTART_AUTO_NEGOTIATION+AUTO_NEGOTIATION_ENABLE)to auto sense and recovery phy registers*/*wait2ms for phy auto-sense linking to partner*/iow(BaseAddress,DM9000_NSR,0x2C);delay(100);iow(BaseAddress,DM9000_ISR,0x3f);delay(100);iow(BaseAddress,DM9000_RCR,0x38);delay(100);iow(BaseAddress,DM9000_TCR,0x00);delay(100);iow(BaseAddress,DM9000_BPTR,0x3f);delay(100);iow(BaseAddress,DM9000_FCTR,0x3a);delay(100);iow(BaseAddress,DM9000_FCR,0xff);delay(100);iow(BaseAddress,DM9000_SMCR,0x00);delay(100);for(i=0;i6;i+)iow(ETH_Port_0,0x16+i,ether_addr0i);delay(100);iow(BaseAddress,DM9000_NSR,0x2C);delay(100);iow(BaseAddress,DM9000_ISR,0x3f);delay(100);iow(BaseAddress,DM9000_IMR,0x81);delay(100);/*store MAC address into NIC*/* if(Num=0)for(i=0;i6;i+)iow(ETH_Port_0,16+i,ether_addr0i);else if(Num=1)for(i=0;i6;i+)iow(ETH_Port_1,16+i,ether_addr1i);/*clear any pending interrupt*/* clear_interrupts();iow(BaseAddress,DM9000_NSR,0x2C);/*clear the TX status:TX1END,TX2END,WAKEUP 3bits,by RW/C1*/*program operating registers*/* iow(BaseAddress,DM9000_NCR,NCR_set);/*NCR REG.00 enable the chip functions(and disable this MAC loopback mode back to normal)*/* iow(BaseAddress,0x08,BPTR_set);/*BPTR REG.08(if necessary)RX Back Pressure Threshold in Half duplex moe only:High Water 3KB,600us*/* iow(BaseAddress,0x09,FCTR_set);/*FCTR REG.09(if necessary)Flow Control Threshold setting High/Low Water Overflow 5KB/10KB*/* iow(BaseAddress,0x0A,RTFCR_set);/*RTFCR REG.0AH (if necessary)RX/TX Flow Control Register enable TXPEN,BKPM(TX_Half),FLCE(RX)*/* iow(BaseAddress,0x0f,0x00);/*clear the all Event*/iow(BaseAddress,0x2D,0x80);/*Switch LED to mode 1*/*set other registers depending on applications*/iow(BaseAddress,ETXCSR,ETXCSR_set);/*enable interrupts to active DM9000 on*/* iow(BaseAddress,DM9000_IMR,INTR_set);/*enable RX(Broadcast/ALL_MULTICAST)*/* iow(BaseAddress,DM9000_RCR,0x39);*/*/void DM9000_init1(void)U8 i;dm9000_reg_write(DM9000_NCR, dm9000_reg_read(DM9000_NCR)&(17);dm9000_reg_write(DM9000_GPCR, 0x01);/設(shè)置 GPCR(1EH) bit0=1，使DM9000的GPIO3為輸出。dm9000_reg_write(DM9000_GPR, 0x00);/GPR bit0=0 使DM9000的GPIO3輸出為低以激活內(nèi)部PHY。/ delay(50000);/延時(shí)2ms以上等待PHY上電。/ delay(50000);/ delay(50000);while(!(dm9000_reg_read(DM9000_NSR)&0x40);/延時(shí)2ms以上dm9000_reg_write(DM9000_NCR, 0x03);/軟件復(fù)位do delay(1000);/延時(shí)20us以上等待軟件復(fù)位完成 while (dm9000_reg_read(DM9000_NCR) & 1);dm9000_reg_write(DM9000_NCR, 0x00);/復(fù)位完成，設(shè)置正常工作模式。dm9000_reg_write(DM9000_NCR, 0x03);/第二次軟件復(fù)位，為了確保軟件復(fù)位完全成功。此步驟是必要的。do delay(1000);/延時(shí)20us以上等待軟件復(fù)位完成 while (dm9000_reg_read(DM9000_NCR) & 1);dm9000_reg_write(DM9000_NCR, 0x00);/*以上完成了DM9000的復(fù)位操作*/dm9000_reg_write(DM9000_NSR, 0x2c);/清除各種狀態(tài)標(biāo)志位dm9000_reg_write(DM9000_ISR, 0x3f);/清除所有中斷標(biāo)志位/*以上清除標(biāo)志位*/dm9000_reg_write(DM9000_RCR, 0x6f);/接收控制dm9000_reg_write(DM9000_TCR, 0x00);/發(fā)送控制dm9000_reg_write(DM9000_BPTR, 0x3f);dm9000_reg_write(DM9000_FCTR, 0x3a);dm9000_reg_write(DM9000_FCR, 0xff);dm9000_reg_write(DM9000_SMCR, 0x00);/*以上是功能控制，具體功能參考參考數(shù)據(jù)手冊(cè)的介紹*/for(i=0; i8)&0x0ff);/*TXPLL low_byte length*/delay(1000);dm9000_reg_write(DM9000_TXPLL,len&0x0FF);/*write transmit data to chip SRAM*/*set MWCMD REG.F8H TX I/O port ready*/delay(1000);DM_ADD=DM9000_MWCMD;delay(1000);for(i=0;itx_len;i+=2)/Uart_SendByte(data_ptri); /delay(20000);/delay(20000);Uart_SendByte(data_ptri+1);DM_CMD=(data_ptri+18)|data_ptri;/ DM_CMD=data_ptri;delay(50000);delay(50000);delay(50000);/*issue TX polling commmand activated*/*TXCR Bit0 TXREQ auto clear after TX completed*/dm9000_reg_write(DM9000_TCR,0x01);/*wait TX transmit done*/while(!(dm9000_reg_read(DM9000_NSR)&0x0C);/*clear the NSR Register*/dm9000_reg_write(DM9000_NSR,0x2c);/*ren-enable NIC interrupts*/dm9000_reg_write(DM9000_RCR,0x39);/ dm9000_reg_write(DM9000_IMR,INTR_set);dm9000_reg_write(DM9000_IMR,0x81);/*數(shù)據(jù)包接收函數(shù)*/unsigned char ReceivePacket(unsigned char *data_ptr) unsigned int rx_len;unsigned char rx_READY;unsigned int Tmp,RxStatus,i;RxStatus=rx_len=0;/ dm9000_reg_write(DM9000_RCR, 0x38);/接收控制/ dm9000_reg_write(DM9000_IMR, 0x80);/* mask NIC interrupts IMR:PAR only*/ iow(BaseAddress,DM9000_IMR,PAR_set);/* if(dm9000_reg_read(DM9000_ISR)&0x01)dm9000_reg_write(DM9000_ISR,0x01) ;*/* dummy read a byte from MRCMDX REG.F0H*/rx_READY=dm9000_reg_read(D