《基于Quartus II的FPGACPLD數(shù)字系統(tǒng)設(shè)計與應(yīng)用》范例的源程序

1、.2-28module adder_4(cout,sum,ina,inb,cin,clk);output3:0 sum;output cout;input3:0 I na,inb; /tempa，tempb中間變量聲明input cin,clk;reg3:0 tempa,tempb,sum; reg cout;reg tempc; /tempc中間變量聲明always (posedge clk) /always clk上升沿觸發(fā)begin /阻塞語句tempa=ina;tempb=inb;tempc=cin;endalways (posedge clk) /always clk上升沿觸發(fā)beg

2、incout,sum=tempa+tempb+tempc;endendmodule2-40 timescale 1ns/10ps module adder4_testbench; reg 3:0 ina,inb;reg cin; reg clk=0;wire 3:0 sum;wire cout;always #10 clk=clk;initial begin ina=0; repeat(20) #20 ina =$random; /隨機數(shù)ina產(chǎn)生 endinitial begin inb=0; repeat(10) #40 inb =$random; /隨機數(shù)inb產(chǎn)生 endinitial

3、 begin cin=0; repeat(2) #200 cin =$random%16;/ 隨機數(shù)inc產(chǎn)生#200 $stop； endadder4 adder4_te( .clk (clk ), .sum ( sum ), .cout ( cout), .ina ( ina ), .inb ( inb ), .cin ( cin ) ); initial endmodule2-73LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SEG_7 ISPORT (SEG: IN STD

4、_LOGIC_VECTOR(3 DOWNTO 0 ); /-四位二進(jìn)制碼輸入 Q3: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );/-輸出LED七段碼END SEG_7;ARCHITECTURE ART OF SEG_7 ISBEGINPROCESS(SEG) BEGINCASE SEG ISWHEN 0000 = Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q3 Q3=1111111;END CASE;END PROCESS; END ART;3-1timescale 1ns/1nsmodule Decoder2x4(A,B,EN,Z) ;input A,

5、B,EN;output 0:3 Z;wire Abar, Bbar;assign #1 Abar=A; / 語句1assign #1 Bbar=B; / 語句2assign #2 Z0=(Abar &Bbar&EN ) ; / 語句3assign #2 Z1=(Abar & B&EN) ; / 語句4assign #2 Z2=(A&Bbar&EN) ; / 語句5assign #2 Z3=(A&B&EN) ; / 語句6endmodule3-3module FASeq(A, B, Cin, Sum, Cout) ;input A, B, Cin ;output Sum, Cout;reg Su

6、m, Cout;reg T1, T2, T3;always(A or B or Cin) begin Sum=(AB)Cin;T1=A&Cin;T2=B&Cin;T3=A&B;Cout = (T1|T2)|T3;endendmodule3-4timescale 1ns/1nsmodule Test(Pop,Pid);output Pop,Pid;reg Pop,Pid;initialbeginPop = 0; / 語句1Pid = 0; / 語句2Pop = #5 1; / 語句3Pid = #3 1; / 語句4Pop = #6 0; / 語句5Pid = #2 0; / 語句6endend

7、module3-5Module FourBitFA (FA,FB,FCin,FSum,FCout);parameter SIZE = 4;input SIZE:1 FA, FB;output SIZE:1 FS uminput FCin;input FCout;wire 1: SIZE-1 FTemp;FAStrFA1( .A(FA1), .B(FB1), .Cin(FCin) , .Sum(FSum1), .Cout(FTemp1 ) ),FA2( .A(FA2), .B(FB2), .Cin(FTemp1),.Sum(FSum2),.Cout(FTemp2) ,FA3( .A(FA3),

8、.B(FB3), .Cin(FTemp2) , .Sum(FSum3), .Cout(FTemp3 ) ),FA4( .A(FA4), .B(FB4), .Cin(FTemp3),.Sum(FSum4),.Cout(FCout) ;endmodule3.1 beginArt = 0; Art = 1;end3.2initialbeginCbn = 0;Cbn=1;end3.3reg 0:2 Q State;initialbeginQ State = 3b011;Q State end_wave; /觸發(fā)事件end_wave Join例3.6 case ( select1:2 )result =

9、 0;2 b01: result = flaga; 2 b0x: result = flagb;2 b0z: result = flaga? bx : 0; 2 b10: result = flagb;2 bx0, result = flagb;2 bz0: result = flagb? bx : 0; default: result = bx; endcase例3.7 case(sig) :1 bz: $display(signal is floating);1 bx: $display(signal is unknown); default:$display(signal is %b,

10、sig); endcase例3.8reg7:0 ir; casez(ir) 8 b1?: instruction1(ir); 8 b01?: instruction2(ir);8 b00010?: instruction3(ir);8 b000001?: instruction4(ir); endcase 例3.9reg7:0 r, mask; mask = 8bx0x0x0x0;casex(rmask)8 b001100xx: stat1; 8 b1100xx00: stat2; 8 b00xx0011: stat3; 8 bxx001100: stat4; ;endcase 例3.10be

11、gin: init_memreg7:0 tempi;for(tempi=0;tempimemsize;tempi=tempi+1)memorytempi=0;end例3.11parameter size = 8, longsize = 16;regsize:1 opa, opb;reglongsize:1 result;begin:multinteger bindex;result=0;for( bindex=1; bindex=size; bindex=bindex+1 )if(opbbindex)result = result + (opa(bindex-1);end例3.12 initi

12、al begin areg=0; /初始化寄存器areg for(index=0;indexsize;index=index+1) memoryindex=0; /初始化一個memory end例3.13always areg = areg;例3.14always # half_period areg = areg;4-2（1）代碼一：module and_2(y,a,b);output y;input a,b;and(y,a,b);endmodule（2）代碼二：module and_2(y,a,b);output y;input a,b;reg y;always(a,b) begin ca

13、se(a,b) 2b00:y=0; 2b01:y=0; 2b10:y=0; 2b11:y=1; default:y=bx; endcase endendmodule4-6(1) 代碼一：module or_2(y,a,b);output y;input a,b;or(y,a,b);endmodule(2) 代碼二：module or_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2b00:y=0; 2b01:y=1; 2b10:y=1; 2b11:y=1; default:y=bx; endcase endendmo

14、dule4-10(1) 代碼一：module notput(y,a);output y;input a;not(y,a);endmodule(2) 代碼二：module notput(y,a);output y;input a;reg y;always(a) begin case(a) 1b0:y=1; 1b1:y=0; default:y=bx; endcase endendmodule4-14（1）代碼一：module nand_2(y,a,b);output y;input a,b;nand(y,a,b);endmodule（2）代碼二：module nand_2(y,a,b);outp

15、ut y;input a,b;reg y;always(a,b) begin case(a,b) 2b00:y=1; 2b01:y=1; 2b10:y=1; 2b11:y=0; default:y=bx; endcase endendmodule4-18(1) 代碼一：module nor_2(y,a,b);output y;input a,b;nor(y,a,b);endmodule(2) 代碼二：module nor_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2b00:y=1; 2b01:y=0; 2b10:

16、y=0; 2b11:y=0; default:y=bx; endcase endendmodule4-22module nora(y,a,b,c,d);output y;input a,b,c,d;assign y=(a&b|c&d);endmodule4-26(1) 代碼一：module xor_2(y,a,b);output y;input a,b;xor(y,a,b);endmodule(2) 代碼二：module xor_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2b00:y=0; 2b01:y=1; 2

17、b10:y=1; 2b11:y=0; default:y=bx; endcase endendmodule4-30(1) 代碼一：module xnor_2(y,a,b);output y;input a,b;xnor(y,a,b);endmodule(2) 代碼二：module xnor_2(y,a,b);output y;input a,b;reg y;always(a,b) begin case(a,b) 2b00:y=1; 2b01:y=0; 2b10:y=0; 2b11:y=1; default:y=bx; endcase endendmodule4-33(1)代碼一：module

18、tri_gate(dout,din,en);output dout; /信號輸入端input din,en; /信號輸入端，使能端assign dout=en?din:dz;endmodule(2)代碼二：module tri_gate(dout,din,en);output dout;input din,en;reg dout;always if(en) dout=din; else dout=bz;endmodule4-36module tri_buffer(dout,din,en);output7:0 dout; /數(shù)據(jù)輸入端input7:0 din; /數(shù)據(jù)輸出端input en; r

19、eg7:0 dout;always if(en) dout=din; else dout=8b z;endmodule4-39module tri_bibuffer(en,dr,a,b);inout7:0 a,b; /雙向數(shù)據(jù)端口input en,dr; /使能端，數(shù)據(jù)方向控制端wire 7:0 a,b; /inout類型雙向端口必須定義為wire類型的變量reg7:0 a_reg,b_reg;/在always、initial語句中的賦值語句被賦值變量必須是寄存器變量，在此定義a_reg,b_reg為雙向端口a,b的緩存器always(*)begin if(dr) begin if(en) b

20、egin b_reg=a; end else begin b_reg=bz; end end else begin if(en) begin a_reg=b; end else begin a_reg=bz; end endendassign a=a_reg;assign b=b_reg;endmodule測試程序如下。timescale 1ns/1nsmodule tri_bibuffer_testbench;wire 7:0 a,b;reg en;reg dr;tri_bibuffer tri_bibuffer(en,dr,a,b);initial begin #10 dr=1;en=1;

21、 force a=b11110000;/ 強制a作為輸入端口 #30 en=0; #30 release a; / 釋放輸入端口a #10 dr=0;en=1; force b=b00001111;/ 強制b作為輸入端口 #30 en=0; #30 release b; / 釋放輸入端口b end endmodule5-1module encoded8_3(x,y);input7:0 x; / 信號輸入端output2:0 y; / 信號輸出端reg 2:0 y;always (x)begincase (x7:0)8b00000001:y2:0=3b000;8b00000010:y2:0=3b

22、001;8b00000100:y2:0=3b010;8b00001000:y2:0=3b011;8b00010000:y2:0=3b100;8b00100000:y2:0=3b101;8b01000000:y2:0=3b110;8b10000000:y2:0=3b111;endcaseendendmodule5-6module youxianencoder(y,eo,gs,i,ei);input7:0 i; /信號輸入端input ei; /輸入使能端output 2:0 y;output eo, gs;reg2:0 y;reg eo, gs;always(i,ei)begin if(ei=1

23、) begin y2:0=3b111; gs=1; eo=1;end else begin if(i7=0)beginy2:0=3b000; gs=0; eo=1;endelse if(i6=0)beginy2:0=3b001; gs=0; eo=1;endelse if(i5=0)beginy2:0=3b010; gs=0; eo=1;endelse if(i4=0)beginy2:0=3b011; gs=0; eo=1;endelse if(i3=0)beginy2:0=3b100; gs=0; eo=1;endelse if(i2=0)beginy2:0=3b101; gs=0; eo=

24、1;endelse if(i1=0)beginy2:0=3b110; gs=0; eo=1;endelse if(i0=0)beginy2:0=3b111; gs=0; eo=1;endelse if(i7:0=b11111111)beginy2:0=3b111; gs=1; eo=0;endendendendmodule5-11module decoder3_8(y,i,g1,g2,g3);output7:0 y;input2:0 i;input g1, g2, g3;reg7:0 y;always(i or g1 or g2 or g3)begin if(g1=0) y=8b1111111

25、1; else if(g2=1) y=8b11111111; else if(g3=1) y=8b11111111;else begin y=8b00000001b)beginy1=1;y2=0;y3=0;endelse if(a=b)beginy1=0;y2=1;y3=0;endelse if(ab)beginy1=0;y2=0;y3=1;endendendmodule5-32代碼一：采用行為描述的1位半加器。module adder(sum,cout,a,b);output sum, cout;input a,b;reg sum, cout;always(a or b)beginsum=a

26、b;cout=a&b;endendmodule代碼二：采用行為描述的1位半加器。module adder(sum, cout,a,b);output sum,cout;input a,b;reg sum,cout;always(a or b)begincout,sum=a+b;endendmodule代碼三：采用門元件實現(xiàn)的1位半加器。module adder(sum, cout,a,b);output sum,cout;input a,b;and(cout,a,b);xor(sum,a,b);endmodule代碼四：數(shù)據(jù)流方式描述的1位半加器。module adder(sum, cout,

27、a,b);output sum, cout;input a,b;assign sum=ab;assign cout=a&b;endmodule 代碼五：采用行為描述的1位半加器。module adder(sum,cout,a,b);output sum,cout;input a,b;reg sum,cout;always(a or b)begincase(a,b)/真值表描述2b00:begin sum=0;cout=0;end2b01:begin sum=1;cout=0;end2b10:begin sum=1;cout=0;end2b11:begin sum=0;cout=1;endend

28、caseendendmodule5-35代碼一：行為描述的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位reg sum,cout;always (a,b,dcout)begincout,sum=a+b+dcout;endendmodule代碼二：行為描述的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位reg sum

29、,cout;always (a,b,dcout)beginsum=(ab)dcout;cout=(a&b)|(a&dcout)|(b&dcout);endendmodule代碼三：調(diào)用門元件實現(xiàn)的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位wire s1,m1,m2,m3;and(m1,a,b), (m2,b,dcout), (m3,a,dcout);xor(s1,a,b),(s, s1,dcout);or(cout,m1,m2,m3);endmodu

30、le代碼四：數(shù)據(jù)流描述的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位assign sum=abdcout;assign cout=(a&b)|(b&dcout)|(dcout&a);endmodule代碼五：數(shù)據(jù)流描述的1位全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位assign cout,sum=a+b+dcou

31、t;endmodule代碼六：混合描述的1為全加器。module full_adder(sum,cout,a,b,dcout);output sum,cout;/和數(shù)、進(jìn)位input a,b,dcout;/被加數(shù)、加數(shù)、低位進(jìn)位reg cout,m1,m2,m3;wire s1;xor x1(s1,a,b);/調(diào)用門元件always (a or b or dcout)beginm1=a&b;m2=dcout&b;m3=a&dcout;cout=(m1|m2)|m3;endassign sum=s1dcout;endmodule5-38module full_adder4(sum,cout,a,

32、b,dcout);output3:0 sum;/和數(shù)output cout;/進(jìn)位標(biāo)志input 3:0 a,b;/加數(shù)和被加數(shù)input dcout;/低位進(jìn)位reg cout;reg3:0 sum;always (*)begincout,sum=a+b+dcout;endendmodule5-41module full_adder16(cout,sum,a,b,cin);output cout;parameter my_size=16;outputmy_size-1:0 sum;inputmy_size-1:0 a, b;input cin;adder my_adder(cout,sum,

33、a,b,cin);/調(diào)用adder模塊endmodule/下面為adder模塊的代碼module adder(cout,sum,a,b,cin);parameter size=16;output cout;outputsize-1:0 sum;inputsize-1:0 a, b;input cin;assigncout,sum=a+b+cin;endmodule5-44代碼一： module half_sub(dout,cout,a,b);output dout,cout;/差位、借位input a,b;/被減數(shù)、減數(shù)reg dout,cout;always (*)begindout=ab;

34、cout=(a)&b;endendmodule代碼二： module half_sub(dout,cout,a,b);output dout,cout;/差位、借位input a,b;/被減數(shù)、減數(shù)reg dout,cout;always (*)begincout,dout=a-b;endendmodule5-47module sub(dout,cout,a,b,ci);output dout,cout;/差位、借位input a,b,ci;/被減數(shù)、減數(shù)、低位借位reg dout,cout;always (*)begincout,dout=a-b-ci;endendmodule5-50mod

35、ule sub4(dout,cout,a,b,ci);output 3:0 dout;/差值output cout;/借位input3:0 a,b;/被減數(shù)、減數(shù)input ci;reg 3:0 dout;reg cout;always (*)begincout,dout=a-b-ci;endendmodule5-53方法一：用for語句實現(xiàn)2個8位數(shù)相乘。 module mult_for(outcome,a,b);parameter size=8;input size:1 a,b;/兩個操作數(shù)output 2*size:1 outcome;/結(jié)果reg 2*size:1 outcome;in

36、teger i;always(a or b)beginoutcome=0;for(i=1;i=size;i=i+1)/for語句if(bi) outcome=outcome+(a(i-1);endendmodule方法二：用repeat實現(xiàn)8位二進(jìn)制數(shù)的乘法。 module mult_for(outcome,a,b);parameter size=8;input size:1 a,b;/兩個操作數(shù)output 2*size:1 outcome;/結(jié)果reg 2*size:1 temp_a, outcome;regsize:1 temp_b;always(a or b)beginoutcome=

37、0;temp_a=a;temp_b=b;repeat(size)/repeat語句，size為循環(huán)次數(shù)beginif(temp_b1)/如果temp_b的最低位為1，就執(zhí)行下面的加法 outcome=outcome+ temp_a; temp_a= temp_a1;/ 操作數(shù)b右移一位endendendmodule5-56module voter7(pass,vote);output pass;input6:0 vote;reg2:0 sum;integer i;reg pass;always(vote)beginsum=0;for (i=0;i=6;i=i+1)if(votei)sum=sum+1;if(sum2) pass=1;/若超過三人贊成，則pass輸出為1else pass=0;endendmodule6-2 module RS(q,qn,s,r); output q,qn; input s,r; reg q,qn; reg q1,qn1; always (*) begin q1=(s&qn1); qn1=(r&q1); q=q1; qn=qn1; end endmodule6-5