DTGAL絕熱電路

1、2021-10-201DTGAL絕熱電路絕熱電路DTGAL邏輯nDTGALpDTGAL2N-2N2P邏輯 與nDTGAL配套使用BufferFull adderBufferFull adderBuffer2P-2P2N邏輯 與pDTGAL配套使用2021-10-2022N-2N2P絕熱邏輯 P1 P2 Ni N2 N1 Nib 1 1 2 3 4 CL 2 3 4 N N N N OUT OUTb IN INb IN OUT4 OUT1 a) b) Buffer/inv結(jié)構(gòu)邏輯賦值（Ni、Nib）驅(qū)動(dòng)(N1、N2、P1、P2)時(shí)鐘依次延遲1/4個(gè)周期功率時(shí)鐘通過P1和P2對(duì)接點(diǎn)OUTb和OUT

2、充放電。2021-10-203如何工作（以梯形波為例）2）IN為高電平時(shí)，Ni被打開，Nib關(guān)閉,OUTb被鉗制為低電平。通過一個(gè)反相器將OUT與功率時(shí)鐘連通。功率時(shí)鐘開始通過P2對(duì)OUT準(zhǔn)備進(jìn)行充電，OUT波形開始尾隨功率時(shí)鐘變化。5）IN到低電平后， CLK開始下降，OUT通過P2向功率時(shí)鐘放電，進(jìn)行能量回收。1）IN逐漸由低電平上升到高電平。3）IN上升到高電平后，開始維持，P2已打開，CLK開始從低電平上升，OUT也隨著CLK上升至高電平。4）IN開始從高電平下降至低電平，CLK維持高電平不變OUT也維持高電平。2021-10-204時(shí)序波形Time0s100ns200ns300ns4

3、00ns500ns600ns700ns800nsV(clk1)0V1.0V2.0VV(in)0V1.0V2.0VSELV(out1)0V1.0V2.0V2N2N-2P五級(jí)反相器非絕熱損耗2021-10-205程序*4.2N2N2P緩沖器程序*.subckt inv1 in inb clk vdd out outb mpmos1 outb out clk vdd pmos w=0.81u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mpmos2 out outb clk vdd pmos w=0.81u l=0.18u ad=0.1539p a

4、s=0.1539p pd=1.35u ps=1.35u mnmos1 outb in 0 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos2 outb out 0 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos3 out outb 0 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos4 out inb 0 0 nmos w=0.27

5、u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u.ends inv1*2N2N2P緩沖器定義完畢*襯底接工作電壓而不是CLK2021-10-206能耗分析2TPL2DDLLP2N2P-2N)2(VCVCTCRE（1）該結(jié)構(gòu)采用兩個(gè)交叉相連的PMOS管進(jìn)行充放電，每周期的能耗表達(dá)式如式（1）所示。Cl是負(fù)載電容，Rp是PMOS管的導(dǎo)通電阻，T是功率時(shí)鐘的傳輸時(shí)間，VDD是功率時(shí)鐘的峰值電壓。公式中第一項(xiàng)表示全絕熱損失，可通過降低工作頻率來減小全絕熱損耗。公式中第二項(xiàng)表示非絕熱損失，只與負(fù)載電容有關(guān)，與頻率無關(guān)。放電至功率時(shí)鐘的路徑關(guān)斷，電壓從閾值

6、突降引起非絕熱損耗2021-10-2072P-2P2N絕熱邏輯 N1 N2 Pi P2 P1 Pib VDD 1 1 2 3 4 CL 2 3 4 P P P P IN OUT4 OUT1 b) a) OUT INb IN OUTb 2P-2P2N結(jié)構(gòu)上與2N-2N2P結(jié)構(gòu)互補(bǔ)，賦值邏輯采用PMOS管構(gòu)建。PMOS接VDD，而NMOS管接功率時(shí)鐘。2021-10-2082TNL2DDLLn2P2N-2P)2(VCVCTCRE（2）該結(jié)構(gòu)采用兩個(gè)交叉相連的NMOS管進(jìn)行充放電，每周期的能耗表達(dá)式如式（2）所示。CL是負(fù)載電容，Rn是NMOS管的導(dǎo)通電阻，T是功率時(shí)鐘的傳輸時(shí)間，VDD是功率時(shí)鐘的

7、峰值電壓。公式中第一項(xiàng)表示全絕熱損失，可通過降低工作頻率來減小全絕熱損耗。公式中第二項(xiàng)表示非絕熱損失，與負(fù)載電容有關(guān)，與頻率無關(guān)。能耗分析放電至功率時(shí)鐘的路徑關(guān)斷，電壓從閾值突變引起非絕熱損耗2021-10-209仿真波形Time0s0.2us0.4us0.6us0.8us1.0us1.2us1.4us1.6usV(in)0V1.0V2.0VV(clk1)0V1.0V2.0VV(inb)0V1.0V2.0VV(out1)0V2.0VSELV(out1b)0V1.0V2.0V2P2P-2N五級(jí)反相器T1T2T3T42021-10-2010 0 2 1 0 Power-clock OUT 2N-2

8、N2P Power-clock Time ns 10 20 30 40 50 OUT Voltage V 1 0 1 1 0 1 0 1 0 0 2P-2P2N 2 1 0 兩種類型的波形，表示高低電平的區(qū)別低電平高電平低電平高電平2021-10-20112P-2P2NBuffer的程序*5.2p2p2n緩沖器程序*.subckt pbuffer A Ab clk vdd out outb mpmos1 outb A vdd vdd pmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mpmos2 outb out vdd

9、vdd pmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mpmos3 out outb vdd vdd pmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mpmos4 out Ab vdd vdd pmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos1 outb out clk 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd

10、=1.35u ps=1.35u mnmos2 out outb clk 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u.ends pbuffer*2p2p2n緩沖器定義完畢*2021-10-2012nDTGAL反相器FIN N3 Y P1 N2 P2 N1 Nib N4 INFINOUTINOUTNi IN OUT INOUTFIN FIN兩部分組成：邏輯賦值電路和能量恢復(fù)電路。賦值電路由（Ni,P1）和（Nib,P2）組成。能量恢復(fù)型電路由（N1,P1）和（N2,P2）組成。 N3 ，N4將沒有被驅(qū)動(dòng)的輸出節(jié)點(diǎn)鉗制

11、到地。功率時(shí)鐘通過Ni,P1（Nib,P2）對(duì)輸出節(jié)點(diǎn)充電。而輸出節(jié)點(diǎn)的能量有反饋信號(hào)控制(fin finb)通過N1,P1（N2,P2）回收給功率時(shí)鐘。2021-10-2013四相時(shí)鐘控制四相時(shí)鐘依次延遲1/4個(gè)周期五級(jí)nDTGAL級(jí)聯(lián)反相器實(shí)現(xiàn)流水線操作2N-2N2P反相器提供最后一級(jí)的控制信號(hào) 輸入信號(hào)和功率始終均采用梯形（正弦波也可）進(jìn)行分析輸入信號(hào)應(yīng)比功率時(shí)鐘提前1/4TNDIN1OUT4CL FIN42341234NNDNDND1ND2021-10-2014工作原理一個(gè)周期分四個(gè)階段（各占1/4T）（1）（0-1/4T）當(dāng)輸入IN上升到高電平時(shí)，Ni打開，功率時(shí) 鐘通過Ni和P1對(duì)

12、輸出節(jié)點(diǎn)OUT充電，而OUTb則被鉗制 到低電平。（2）（1/4T-1/2T）當(dāng)輸入IN維持在高電平時(shí)，OUT尾隨 時(shí)鐘由低向高變化。 （3）（1/2T-3/4T）當(dāng)輸入IN開始下降時(shí)，輸出OUT仍維 持高電平。 （4）（3/4T-T）當(dāng)輸入IN下降到零后，OUT開始放電，F(xiàn)IN反饋打開NMOS管，隨著功率時(shí)鐘CLK的變化將輸出節(jié)點(diǎn)OUT上的電荷，通 過 N1，P1回收回來，無非絕熱損失。 2021-10-2015仿真時(shí)序圖Time0s100ns200ns300ns400ns500ns600ns700ns800nsV(out5)0V1.0V2.0VV(out2)0V1.0V2.0VV(in)0

13、V1.0V2.0VV(clk1)0V1.0V2.0VV(clk2)0V2.0VSELnDTGAL五級(jí)反相器T1T2T3T4無非絕熱損失2021-10-2016能耗分析2DDLLDTGAL)2(VCTRCE該結(jié)構(gòu)是全絕熱過程，式中的R是（Ni,p1）和（Nib,P2）的導(dǎo)通電阻。CL是負(fù)載電容，T是周期，VDD是工作電壓?？赏ㄟ^減小工作頻率f=1/T來降低其能耗損失。2021-10-2017nDTGAL反相器程序*3.NDTGAL緩沖驅(qū)動(dòng)器程序*.subckt inv2 in inb fin finb clk1 vdd out outb mpmos1 out outb clk1 vdd pmos

14、 w=1.08u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mpmos2 outb out clk1 vdd pmos w=1.08u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos1 outb inb clk1 0 nmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos2 out in clk1 0 nmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u

15、ps=1.35u mnmos3 out fin clk1 0 nmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos4 outb finb clk1 0 nmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos5 out outb 0 0 nmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos6 outb out 0 0 nmos w=0.54u l=0.18u a

16、d=0.1539p as=0.1539p pd=1.35u ps=1.35u .ends inv2*NDTGAL緩沖驅(qū)動(dòng)器定義完畢*2021-10-2018nDTGAL全加器以上結(jié)構(gòu)分別實(shí)現(xiàn)全加器的進(jìn)位和求和邏輯將反相器中的賦值邏輯用上面的電路結(jié)構(gòu)替代反向器中的Ni和Nib，既可實(shí)現(xiàn)全加器的邏輯功能。CiBABACiABBAS)()(ACiABBCiC求和邏輯進(jìn)位邏輯SSbBCbCAbBbAABclkclkCbBbABBCBbAbCCb2021-10-2019Time0s100ns200ns300ns400ns500ns600ns700ns800nsV(s)0V2.0VV(c)0V2.0V-S

17、(V(clk1)*I(vclk1)0V(A)0V2.0VV(B)0V2.0VV(Ci)0V2.0VV(clk1)0V2.0VV(fin)0V2.0VV(fin1)0VSEL全加器仿真波形圖2021-10-2020全加器程序求和電路的程序.subckt sadder a ab b bb ci cib fin finb clk1 vdd out outb mpmos1 out outb clk1 vdd pmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mpmos2 outb out clk1 vdd pmos w=0.54u

18、 l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos1 1 ci clk1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos2 1 b 2 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos3 out a 2 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos4 1 bb 4 0 n

19、mos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos5 outb Ab 2 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos6 3 cib clk1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos7 3 bb 2 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mn

20、mos8 out ab 4 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos9 3 b 4 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos10 outb a 4 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos11 out outb 0 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=

21、1.35u ps=1.35u mnmos12 outb out 0 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos13 out fin clk1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos14 outb finb clk1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u.ends sadder2021-10-2021求進(jìn)位的程序.sub

22、ckt cadder a ab b bb ci cib fin finb clk1 vdd out outb mpmos1 out outb clk1 vdd pmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mpmos2 outb out clk1 vdd pmos w=0.54u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos1 1 ci clk1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps

23、=1.35u mnmos2 out b 1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos3 1 bb 2 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos4 out a 2 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos5 3 cib clk1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.153

24、9p pd=1.35u ps=1.35u mnmos6 3 Bb outb 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos7 3 b 2 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos8 outb ab 2 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos9 out outb 0 0 nmos w=0.27u l=0.18u ad

25、=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos10 outb out 0 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos11 out fin clk1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u mnmos12 outb finb clk1 0 nmos w=0.27u l=0.18u ad=0.1539p as=0.1539p pd=1.35u ps=1.35u.ends cadde

26、r2021-10-2022pDTGAL反相器FIN P3 Y N1 P2 N2 P1 Pib P4 INFINOUTINOUTPi IN OUT FIN VDD P 邏輯賦值與能量恢復(fù)與NDTGAL反相器類似。將nmos換成了pmos.2021-10-2023 1234PDIN1OUT4CLFIN42342PPDPDPD1PD四相時(shí)鐘控制五級(jí)pDTGAL級(jí)聯(lián)反相器實(shí)現(xiàn)流水線操作輸入信號(hào)應(yīng)比功率時(shí)鐘提前1/4T四相時(shí)鐘依次延遲1/4個(gè)周期2P-2P2N反相器提供最后一級(jí)的控制信號(hào) 輸入信號(hào)和功率始終均采用梯形（正弦波也可）進(jìn)行分析2021-10-2024工作原理一個(gè)周期分四個(gè)階段（各占1/4T）

27、（1）（0-1/4T）當(dāng)輸入IN下降到低電平時(shí)，Pi打開，功率時(shí)鐘通過Pi和N1開始對(duì)輸出節(jié)點(diǎn)OUT放電，進(jìn)行能量回收，而OUTb則被拉到高電平。（2）（1/4T-1/2T）當(dāng)輸入IN維持在低電平時(shí)，OUT尾隨時(shí)鐘從高電平下降。 （3）（1/2T-3/4T）當(dāng)輸入IN開始上升時(shí)，輸出OUT仍維持低電平。 （4）（3/4T-T）當(dāng)輸入IN上升為高電平時(shí)，隨著功率時(shí)鐘CLK由低逐漸上升，OUT尾隨CLK上升，充電至高電平。2021-10-2025仿真時(shí)序圖Time0s100ns200ns300ns400ns500ns600ns700ns800nsV(in)0V1.0V2.0VV(clk1)0V1.0V2.0VV(inb)0V1.0V2.0VV(out1)0V1.0V2.0VV(out2)0V2.0VSELpDTGAL五級(jí)反相器T1T2T3T42021-10-2026pDTGAL反相器程序*6.PDTGAL緩沖驅(qū)動(dòng)器程序*.subckt pd