caputer生成網(wǎng)表報錯原因解析#(精選.)

1、(1) Warning "No_connect"#1 Warning ALG0047 "No_connect" property on Pin "P1.8" ignored forPI: SCHEMATIC1, 13)URAT (7.90, 1.20). Connecting pin to net "N16811229".&H)K-hwM$k3D3pd-T$W7heALG0047這個警告基本可以忽略；造成這個問題的原因是，設(shè)計之 初先對器件相關(guān)的管腳上加上'X'(也就是NC符號)，更新設(shè)計的

2、過 程又對管腳做了連接處理；但是后面的連接處理沒有去掉管腳的NC屬性，不信的話把那個管腳上的net刪掉看看。RG9f 解決辦法很簡單，對這些管腳再做一次NC(2) Warning Part Name#5 Warning ALG0016 Part Name "CAP PN_C100UP-6.3V-SMT- S_100UF/6.3V" is renamed to "CAP PN_C100UP-6.3V-SMT- S_100UF/"這個警告不可避免，allegro對相關(guān)的屬性名稱進(jìn)行合并，超過一定數(shù)量的字符就截掉；在命名規(guī)范的前提下就不考慮這個警告了。無法根治

3、 這個 #2 Warning ALG0016 Part Name "?j#w?rm之類的錯誤在于你建立元件原理圖的時候你的原件Value值太長了超過32個字符,從而使系統(tǒng)在進(jìn)行命名規(guī)范的時候溢出，而出錯,很 簡單的，只寫關(guān)鍵元件名，比如A2541P10_HDR2X5-100MIL_2X5 HEADER" is renamed to "A2541P10_HDR2X5-100MIL_2X5 HEAD1誤 只需要把2X5 HEADE哽改為A2541P10,去除中間的空格即可 二Allegro對一些字符例如"空格","小數(shù)點"等等很

4、在意，可以參閱 相關(guān)文檔的描述.(3) Error Illegal character "Dot(.)" found in "PCB Footprint"#1 Error ALG0081 Illegal character "Dot(.)" found in "PCB Footprint" property for component instance C255: PG16_AC97, PG16_AC97 (226.06, 132.08).封裝命名不能包含“.”(4) Error Illegal character

5、 "Forward Slash(/)" found in "PCB Footprint" property# 1 Error ALG0081 Illegal character "Forward Slash(/)” found in "PCB Footprint" property for component instance C255: PG16_AC97, PG16_AC97 (226.06, 132.08).# 2 Error ALG0081 Illegal character "Forward Slash(

6、/)” found in "PCB Footprint" property for component instance D3: PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp (93.98, 33.02).# 3 Error ALG0081 Illegal character "Forward Slash(/)” found in "PCB Footprint" property for component instance C245

7、: PG16_AC97, PG16_AC97 (205.74, 35.56). 封裝命名不能包含“ /”(5)比較隱藏的排除法Loading. E:FPGASCHallegroestchip.dat#34 WARNING(SPCODD-34Expected '' character on line 5308.Check the name and value syntax for invalid characters in the primitive definition before the line number.ERROR(SPCODD-47): File ./allegr

8、o/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causing this situation and package the design again.#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have b

9、een saved correctly. Save the schematic and rerun packaging.#187 Error ALG0036 Unable to read logical netlist data.Exiting. "D:CadenceSPB_16.2toolscapturepstswp.exe" - pst -d "E:FPGASCHmotherboard.dsn" -n "E:FPGASCHallegro" -c "D:CadenceSPB_16.2toolscaptureallegro.

10、cfg" -v 3 -j "PCB Footprint"*Done*掌握排錯方法，查找文件pstchip.dat ，第 on line 5308 看看錯誤，便可以解決（6）封裝命名中不能包含“小數(shù)點”、“/ ”、“空格”，把空格換成下劃線或刪除，可以解決* Netlisting the design*Design Name:E:FPGASCHbasicboard.dsnNetlist Directory:E:FPGASCHallegroConfiguration File:D:CadenceSPB_16.2toolscaptureallegro.cfgSpawni

11、ng. "D:CadenceSPB_16.2toolscapturepstswp.exe-pst -d "E:FPGASCHbasicboard.dsn" -n"E:FPGASCHallegro" -c "D:CadenceSPB_16.2toolscaptureallegro.cfg" -v 3 -j "PCB Footprint" 1） Error ALG0081 Illegal character "White space" found in "PCB Footprin

12、t" property for component instance MG2: Basic, PG06_Stepmotor (180.34, 83.82). 2） Error ALG0081 Illegal character "White space" found in "PCB Footprint" property for component instance ISO1: Basic, PG05_DC Motor (134.62, 40.64). 3） Info: PCB Editor does not support Dots(.),

13、Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-). 4） Aborting Netlisting. Please correct the above errors and retry.Exiting. "D:CadenceSPB_16.2toolscapturepstswp.exe"- pst -d "E:FPGASCHbasicboard.dsn

14、" -n "E:FPGASCHallegro" -c "D:CadenceSPB_16.2toolscaptureallegro.cfg" -v 3 -j "PCB Footprint"*Done *封裝命名中不能包含“小數(shù)點”、 劃線或刪除，可以解決/"、“空格”，把空格換成下 7） Warning#11 Warning ALG0051 Pin "GND" is renamed to "GND#A6" after substituting illegal character

15、s in Package XC3S1400A- 4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).#12 Warning ALG0051 Pin "GND" is renamed to "GND#A11" after substituting illegal characters in Package XC3S1400A- 4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).#13 Warning ALG0051

16、Pin "GND" is renamed to "GND#A1" after substituting illegal characters in Package XC3S1400A- 4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).#14 Warning ALG0051 Pin "GND" is renamed to "GND#W8" after substituting illegal characters in Package XC3S

17、1400A- 4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40, 3.10).這條警告信息，在命名規(guī)范的前提下就不考慮這個警告了。 無法根治，除非去除檢測 8）# 60 Warning ALG0016 Part Name"COM_17 2_SIP17X2_COM_1>72" is renamed to "COM_172_SIP17X2_COM_172".# 61 Warning ALG0060 No pins are present in J53. Ignoring this compone

18、nt in netlist.# 62 Warning ALG0016 Part Name “1X3P,MALE,DIP_2.0_SIP3_1X3P_2.54MM" is renamed to “1X3P,MALE,DIP_2.0_SIP3_1X3P_2.5”.器件管腳不存在，有的器件做了但沒放管腳，正常 9） error: Same Pin Number connected to more than one net.請檢查 這個器件的位號是否有重復(fù)。一般是重復(fù)了才會出現(xiàn)這種情況。Checking Pins and Pin ConnectionsERROR: DRC0031 Same

19、Pin Number connected to more than one net . LED&Switch&7- Segment Disp/U17/3 Nets: '3V3' and '485_RE/DE'.PG01_LED&Switch&7-Segment Disp,PG01_LED&Switch&7S-egmentDisp （101.85, 73.66）上面的問題是器件位號重復(fù) 10） 10）WARNING: DRC0008 Two nets in same schematic have the same n

20、ame, but there is no off-page connector這個問題是信號同名，到?jīng)]有用OFF-PAG連接起來生成網(wǎng)表會自動重新命名一個名字 11） 11） 1. Unable to open c:CadencePSD_14.2toolscaptureallegro.cfg for reading.Please correct the above error（s） to proceed錯誤解釋：allegro.cfg 文件找不到或allegro.cfg 文件不能打開，這個問題的根源是，有可能每臺電腦上安裝Allegro 的的位置不一樣，allegro.cfg 文件找不到是理所

21、當(dāng)然的。處理辦法：點生成 netlist ，點 setup ，修改路徑為captureallegro.cfg 所在路徑，把allegro.cfg 文件的位置選擇你現(xiàn)在安裝目錄的文件位置。 12） 12） Spawning."C:CadencePSD_15.1toolscapturepstswp.exe" -pst -d "F:gchtCC2430Projectsmysch.dsn" -n"C:CADENCEPSD_15.1TOOLSPROJECTS" -c"C:CadencePSD_15.1toolscapturealleg

22、ro.cfg" -v 3 -j "CC2430_DEMO"# 1 Error ALG0012 Property "PCB Footprint" missing from instance U3: SCHEMATIC1, PAGE1 (2.00, 2.10).# 2 Error ALG0012 Property "PCB Footprint" missing from instance C2: SCHEMATIC1, PAGE1 (2.30, 0.30).# 17 Aborting Netlisting. Please cor

23、rect the above errors and retry.錯誤解釋：Error ALG0012 Property "PCB Footprint" missing from part <Part Reference>: <Schematic> , <Page> (<LocationX> , <LocationY)>A PCB Footprint (JEDEC_TYPE in Allegro) is required for all parts in Allegro. Therefore all parts wi

24、thout this property are listed before aborting the netlisting. You can add the PCB Footprint property by selecting the part listed, then choosing Edit Properties from the pop-up menu and placing a value, such as dip14_3, on the part.在Allegro中，每個器件都需要一個PC的裝。所以在取消列出網(wǎng) 表之前，軟件會列出所有沒有此項的器件。你可以選擇列出的器件添加PCB

25、寸裝，然后選擇Edit Properties 來編輯器件的值。處理辦法：在導(dǎo)出 Netlist 之前，只需要保證每個器件都是有封裝的，且器件PCB Footprint 值與對應(yīng)的.dra 封裝文件名一致。( 13) . DRC0011 Reference is invalid for this partThe reference for the part is invalid. For example, this occurs when a part reference like U?A has not been updated. Update the part reference 。Refe

26、rence 項不可隨意修改。( 14) Pin numbers do not match. Check device file.原因：原理圖中的晶振給了兩個管腳，而其封裝卻是四個管腳。原理圖與PC的裝對應(yīng)原則：除了 PCB Footprint 的名字要寫對以外，還有一點，就是原理圖的元件的管腳數(shù)目一定要和封裝的管腳數(shù)目必須一樣。這里說的管腳，包括了原理圖中可能沒有現(xiàn)實的Power Pins, 不包括封裝中的machanical pins ；另外，原理圖和封裝的對應(yīng)關(guān)系是依靠pinnumber來建立的，所以兩者的相應(yīng)的 pin number 一定要一樣，而 pin number 是不是數(shù)字并沒有

27、關(guān)系。( 15) . ERROR(SPMHNI-191): Device/Symbol check error detected.WARNING(SPMHNI-337): Unable to load symbol 'HDR1X2' for device'B2S_HDR1X2_B2S': WARNING(SPMHUT-127): Could not find padstack 57S40DP.due to ERROR(SPMHDB-274): Unable to load flash symbol THS79X59X45X4X15 (Check PSMPATH setting for this symbol)."原因：花焊盤Flash 沒有創(chuàng)建 .fsm 的 symbol 文件，或是該文件保存路徑與 .psm 文件不一致。二、 Allegro 導(dǎo)入 netlist 的時候報錯can not find symbol ：出現(xiàn) Netrev succeeded 即可，說明已沒有error 了，可以直接打開自動生成的.brd 文件了。但此時Updating Allegro PCB EditorBoard 仍然會有紅叉，貌似還有問