Aug_28_2-1. SHARC

1、High Performance SHARC core Supports both Floating and fixed th Floating and fixed pointpointOverall SHARC architecture2I/O Processor with 31 DMA ChannelsCore TimerTimers (3)JTAG & Control400MHzSIMDSHARC CORESports (8)Interrupts (10)8 Channel Sample Rate Conversion(-128dB) New/Enhanced Periphera

2、ls for SHARC LX3UARTs (2)I2CGPIO (20) 6MbitROM2MbitSRAMOn-chip MemoryGPIO/Flags/IRQ Digital Audio Interface Digital Peripheral InterfaceSPI (2)32-Bit External Memory InterfaceS/PDIF Tx/RxPrecision Clock Generators (4)Input Data Port /PDAPSingle Instruction Single Data (SISD) Core3DAG 2 8 x 4 x 24DAG

3、 1 8 x 4 x 32CACHE MEMORY 32 x 48PROGRAM SEQUENCERPMD BUSDMD BUS24PMA BUSPMDDMDPMA32DMA BUSDMA4840MULTIPLIER BARREL SHIFTERALUREGISTER FILE 16 x 40PX RegisterSingle Instruction Multiple Data (SIMD) Core 4DAG 2 8 x 4 x 32DAG 1 8 x 4 x 32CACHEMEMORY PROGRAM SEQUENCERPMD BUSDMD BUS32PMA BUSPMDDMDPMA32D

4、MA BUSDMA6464BUS CONNECTBARRELSHIFTER ALU REGISTERFILE MULTIPLIER/MAC Processing Element XMULTIPLIER/MAC REGISTER REGISTERFILE BARRELSHIFTER ALU Processing Element YRegister groups3-5System Registers (SREG)Register File (DREG)Data Address GeneratorBus Exchange (Px)TimerProgram SequencerMultiplier Re

5、sults - MRComputation Unit RegistersUniversal Registers (UREG)Complementary Register (CREG)System Control Registers (SC)DMA Address Registers (DA)DMA buffer Registers (DB)Link & Serial Port (LSP)SPI PortI/O Processor Registers(memory mapped)Universal registers: exampleuUniversal registers are ac

6、cessible to other universal registers as well as to data memoryLocationRegister(s)FunctionDREG R15 - R0Data registers in register file (PEx)CUREG of DREGS15 - S0Complimentary data registers (PEy)Program SequencerPCProgram counter (read only)Address GeneratorsI7 - I0DAG1 index registersTimerTPERIODTi

7、mer periodSystem RegistersMODE1Mode control & status(SREG)USTAT1User status register 1USTAT4User status register 46I/O Processor registersuMemory mapped registersuCycle effect latency when writing IOP registerslAccessed at memory addresses using the:uDSP coreuPM busuDM busuI/O bus7Complimentary

8、Registers UREG-CUREGu There are certain registers within UREG which have complimentary registers. Complimentary registers are primarily used in SIMD mode.lDREGuR0/F0 S0 uR1/F1 S1uR15/F15 S15lSREGuUSTAT1 - USTAT2uUSTAT3 - USTAT4uASTATx - ASTATyuSTKYx - STKYyuPX1 - PX28Processing Element Block Diagram

9、10ALUSHIFTERPMD BUSDMD BUS16 x 2 registers x 40 bitsr0 or f0r1 or f1r2 or f2r3 or f3r4 or f4r5 or f5r6 or f6r7 or f7r8 or f8r9 or f9r10 or f10r11 or f11r12 or f12r13 or f13r14 or f14r15 or f15 MULTIPLIER2 x 80 bitMAC Result Register(MR)MRFMRBMRF2MRF1 MRF0Register FileuOne register file for each proc

10、essing elementuTransfers data between the data buses and the computational units.u16 primary registers and 16 alternate (shadow) registers.uEach register is 40 bit wide.uTransfers 9 words per cycle:l2 memory transfersl4 register reads, 3 register writes with Computation UnitsuR0.R15/F0.F15lUsed for

11、data move or fixed/floating point arithmetic. lRefer to register file of PEx in SISD mode and to both PEx and PEy in SIMD mode.uS0.S15lUsed for data move only.lRefer to register file of PEy in SIMD mode.11Data alignment1239 32 31 24 23 16 15 8 7 0 |xxxxxxx|xxxxxxx|xxxxxxx|xxxxxxx|00000000| 39 32 31

12、24 23 16 15 8 7 0 |xxxxxxx|xxxxxxx|xxxxxxx|xxxxxxx|xxxxxxx|32 bit data40 bit dataRegisterFile32 bit fixed point formats13 Bit 31 30 29 2 1 0Weight -231 230 229 22 21 20Sign Signed Integer bit Bit 31 30 29 2 1 0Weight 231 230 229 22 21 20 Unsigned Integer Bit 31 30 29 2 1 0Weight -20 2-1 2-2 2-29 2-3

13、0 2-31Sign Signed Fractional bit Bit 31 30 29 2 1 0Weight 2-1 2-2 2-3 2-30 2-31 2-32 Unsigned Fractional examples -3 = 0 xfffffffd 3 = 0 x00000003231 = 0 x80000000 3 = 0 x00000003 .25 = 0 x20000000 .75 = 0 x60000000 .25 = 0 x40000000 .75 = 0 xc0000000 Floating-Point Formats14 39 832-bit: s e7 e0 1.f

14、22 f0 39 040-bit: s e7 e0 1.f30 f8 f7 f0hidden bittype exponent fraction value example representation Normal 1 e254 any 0 x3f800000 1 . 0 Zero 0 0 zero 0 x00000000 0 . 0 Infinity 255 0 infinity 0 x7f800000 1.# I N F NAN 255 non-zero undefined 0 x7f800001 1.# N A N Denormal 0 any zero 0 x00000001 1.#

15、 I N D (-1)s(1.f)2(e-127)Floating-point Conversion Example150 x4040000=|0|100 0000 0|100 0000 0000 0000 0000 0000sign bit=0exponent=128fractional field=1.5(1. is assumed)(-1)s(1.f)2e-127(-1 )x(1.5)x(2 ) =1.5 x(2 )=3.0128-12701Convert 0 x4040000 to an IEEE floating point numberFormula:Arithmetic Logi

16、c Unit (ALU)uArithmetic operations on fixed/floating point data.uLogical operations on fixed point data.uFixed point instructionslOperate on 32-bit fixed-point operands and output 32-bit fixed-point results.uFloating point instructionslOperate on 32-bit or 40-bit floating-point operands and output 3

17、2-bit or 40-bit floating- point results.16ALU instructions includeuFloating-point addition, subtraction, add/subtract, averageuFixed-point addition, subtraction, add/subtract, averageuFloating-point manipulation: binary log, scale, mantissauFixed-point add with carry, subtract with borrow, increment

18、,decrementuLogical And, OR, XOR, NOTuFunctions: ABS, PASS, MIN, MAX, CLIP, COMPAREuFormat conversionuReciprocal and reciprocal square root primitives17ALU instructions: Fixed PointRn=Rx+Ry;Rn=-Rx;Rn=Rx+CI-1;Rn=Rx-Ry;Rn=ABS Rx;Rn=Rx+1;Rn=Rx+Ry,Rm=Rx-Ry;Rn=PASS Rx;Rn=Rx-1;Rn=Rx+Ry+CI;Rn=MIN(Rx,Ry);Rn=

19、Rx AND Ry;Rn=Rx-Ry+CI-1;Rn=MAX(Rx,Ry);Rn=Rx OR Ry;Rn=(Rx+Ry)/2;Rn=CLIP Rx by Ry;Rn=Rx XOR Ry;COMP(Rx,Ry);Rn=Rx+CI;Rn=NOT Rx; Rn, Rm,Rx,RyR15-R0; register file location, fixed point18ALU instructions: Floating PointFn=Fx+Fy; Fn=ABS Fx;Rn=LOGB Fx;Fn=Fx-Fy; Fn=PASS Fx ;Rn=FIX Fx BY Ry;Fn=Fx+Fy,Fm=Fx-Fy

20、; Fn=MIN(Fx,Fy); Rn=FIX Fx;Fn=ABS(Fx+Fy); Fn=MAX(Fx,Fy); Fn=FLOAT Rx BY Ry;Fn=ABS(Fx-Fy); Fn=CLIP Fx by Fy; Fn=FLOAT Rx;Fn=(Fx+Fy)/2; Fn=RND Fx; Rn=RECIPS Fx;COMP(Fx,Fy); Fn=SCALB Fx BY Ry; Fn=RSQRTS Fx;Fn=-Fx; Rn=MANT Fx; Fn=Fx COPYSIGN Fy; Rn,Rm,Rx,RyR15-R0; register file location, fixed point Fn,

21、Fm,Fx,FyF15-F0; register file location, floating point19ALU Status Flags20ASTATx/yBitName Definition 0AZ ALU result zero or floating-point underflow 1AV ALU overflow 2AN ALU result negative 3AC ALU fixed-point carry 4AS ALU X input sign (ABS and MANT operations 5AI ALU floating-point invalid operati

22、on10AF Last ALU operation was a floating-point operation31-24CACC Compare Accumulation register (results of last eight compare operations)STKYx/yBitName Definition0AUS ALU floating-point underflow1AVS ALU floating-point overflow2AOS ALU fixed-point overflow5AIS ALU floating-point invalid operationMu

23、ltiplieruFloating point multiplicationlOperands- 32-bit or 40-bit floating-point.lOutput-32-bit or 40-bit floating-point. lParallel operation of Multiplier and ALU supported.uFixed point multiplicationlOperands-32-bit fixed-point(fractional/integer/signed/unsigned).lOutput-80 bit accumulatorlOptiona

24、l rounding.uMultiplier result register operationslRounding lSaturationlClearing the MR register.2122 MAC: Fixed vs. Floating-PointF4F3F12R1R2 MRF=MRF+R1*R2(SSF);R5=MR1F;F12=F3*F4,F8=F8+F12;MultiplierMR2F16bitMR1F32bitMR0F32bitALUF8F8F12MultiplicationADDMRF(80 bit)32/40bit Float32bit Fixed40 bitMulti

25、plier instructions: Fixed Point3-23ADSP-21161 WorkshopMRF = 0 ;MRBRn = Rx * Ry ( S S F ) ; MRF U U I MRB FR Rn = MRF + Rx * Ry ( S S F ) ; Rn = MRB U U I MRF = MRF FR MRB = MRB Rn = MRF Rx * Ry ( S S F ); Rn = MRB U U I MRF = MRF FR MRB = MRB Rn = SAT MRF Rn = SAT MRB MRF = SAT MRF MRB = SAT MRBRn =

26、 RND MRF Rn = RND MRB MRF = RND MRF MRB = RND MRB MRxF = Rn ;MRxB Rn = MRxF MRxB (SI) ;(UI); (SF); (UF);(SF) ;(UF);Multiplier instruction: Floating Point24Fn = Fx * Fy;Multiplier Status FlagsASTATx/yBitNameDefinition6MNMultiplier result negative7MVMultiplier overflow8MUMultiplier underflow9MIMultipl

27、ier floating-point invalid operationSTKYx/yBitNameDefinition6MOSMultiplier fixed-point overflow7MVSMultiplier floating-point overflow8MUSMultiplier underflow9MISMultiplier floating-point invalid operation25Barrel Shifter (Shifter)uShifter operationslShifts and rotates.lBit manipulation operationsubi

28、t set, clear, toggle, and test.lBit field manipulation operationsuextract and deposit.lFixed-point/floating-point conversion operationsuexponent extract, number of leading 1s or 0s.26Shifter: Logical and Arithmetic Shifts27Before:07152331390000000000000000000000001111111100000000FF00000000R007152331

29、390000000011111000111111111111111111111111FFFFFFF800R1R2 = LSHIFT R0 BY -8 or R2 = LSHIFT R0 BY R1After:0715233139000000000000000000000000111111110000000000FF000000R2Logical ShiftR2 = ASHIFT R0 BY -8 or R2 = ASHIFT R0 BY R1After:Arithmetic ShiftR2071523313900000000000000000000000011111111FFFF0000001

30、1111111Shifter: Bit Field Extract28Rn = Rn OR FEXT Rx BY Ry (SE); Rn = Rn OR FEXT Rx BY :(SE);Example:R0 = FEXT R1 BY 16:8;R10715233139000000000000000011111111000000000 x00FF000007152331390000000011111111000000000000000000000000R0reference point0 x000000FF0000000000000000bit6len6len6Shifter: Bit Operations29Rn = BCLR Rx BY Ry Rn = BCLR Rx BY Rn = BSET Rx BY Ry Rn = BSET Rx BY Rn = BTGL Rx BY Ry Rn = BTGL Rx BY BTST Rx BY Ry BTST Rx BY Example:0715233139