計(jì)數(shù)計(jì)時(shí)器的VHDL設(shè)計(jì)課件

1、/VHDL設(shè)計(jì)本課要解決的問(wèn)題：n一般計(jì)時(shí)器的VHDL描述；n六十進(jìn)制計(jì)數(shù)器和計(jì)時(shí)器的VHDL設(shè)計(jì)；n二十四進(jìn)制計(jì)時(shí)器的VHDL設(shè)計(jì)；n數(shù)字鐘的VHDL設(shè)計(jì)。一、 計(jì)數(shù)器的作用n在時(shí)鐘的驅(qū)動(dòng)下，對(duì)輸入脈沖進(jìn)行計(jì)數(shù)；如果輸入的脈沖為時(shí)鐘脈沖，就成為計(jì)時(shí)器。n當(dāng)計(jì)數(shù)值達(dá)到一定數(shù)值，計(jì)數(shù)器產(chǎn)生進(jìn)位輸出，并復(fù)位。 二、計(jì)數(shù)器的設(shè)計(jì)(P63-67)n簡(jiǎn)單計(jì)時(shí)器的設(shè)計(jì)；n六十進(jìn)制計(jì)數(shù)器和計(jì)時(shí)器的設(shè)計(jì)；n二十四進(jìn)制計(jì)時(shí)器的設(shè)計(jì)；n數(shù)字鐘的設(shè)計(jì)。n最簡(jiǎn)單的計(jì)時(shí)器ENTITY CNT4 IS PORT ( CLK : IN BIT ; Q : BUFFER INTEGER RANGE 15 DOWNTO 0 )

2、 ; END ; ARCHITECTURE bhv OF CNT4 IS BEGIN PROCESS (CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN Q = Q + 1 ; END IF; END PROCESS ;END bhv; BUFFER模式才可以讀取在時(shí)鐘CLK信號(hào)的驅(qū)動(dòng)下Q對(duì)時(shí)鐘信號(hào)CLK進(jìn)行計(jì)數(shù)；由于Q為BUFFER模式，所以可以讀取Q的值【例3-19】表式表式Q = Q + 1Q = Q + 1的右項(xiàng)與左項(xiàng)并非處于相同的時(shí)刻內(nèi)，對(duì)于時(shí)序電的右項(xiàng)與左項(xiàng)并非處于相同的時(shí)刻內(nèi)，對(duì)于時(shí)序電路，除了傳輸延時(shí)外，前者的結(jié)果出現(xiàn)于當(dāng)前時(shí)鐘周期；后者，即路，除

3、了傳輸延時(shí)外，前者的結(jié)果出現(xiàn)于當(dāng)前時(shí)鐘周期；后者，即左項(xiàng)要獲得當(dāng)前的左項(xiàng)要獲得當(dāng)前的Q + 1Q + 1，需等待下一個(gè)時(shí)鐘周期。，需等待下一個(gè)時(shí)鐘周期。 時(shí)鐘信號(hào)到來(lái)？時(shí)鐘信號(hào)到來(lái)？Q計(jì)數(shù)加計(jì)數(shù)加1結(jié)束結(jié)束 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY CNT4 IS PORT ( CLK : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END ; ARCHITECTURE bhv OF CNT4 IS

4、SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS (CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN Q1 = Q1 + 1 ; END IF; END PROCESS ; Q 0) ; ELSIF CLKEVENT AND CLK=1 THEN IF EN = 1 THEN IF CQI 0); END IF; END IF; END IF; IF CQI = 9 THEN COUT = 1; ELSE COUT = 0; END IF; CQ 0) 為省略賦值方式，對(duì)CQI清零檢測(cè)是否允許計(jì)數(shù)允許計(jì)

5、數(shù)允許計(jì)數(shù), 檢測(cè)是否小于檢測(cè)是否小于9大于大于9，計(jì)數(shù)值清零，計(jì)數(shù)值清零計(jì)數(shù)大于等于9，輸出進(jìn)位信號(hào)將計(jì)數(shù)值向端口輸出LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_unsigned.ALL;ENTITY bcd60count ISPORT(clk, bcd1wr, bcd10wr, cin: IN STD_LOGIC; co: OUT STD_LOGIC; datain: IN STD_LOGIC_VECTOR(3 DOWNTO 0); bcd10n: BUFFER STD_LOGIC_VECTOR(2 DOWNTO

6、0); bcd1n: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END bcd60count;【六十進(jìn)制計(jì)數(shù)器】|實(shí)體n 六十進(jìn)制計(jì)數(shù)器的設(shè)計(jì)clk: 時(shí)鐘端；bcd1wr, bcd10wr: 計(jì)數(shù)初值的個(gè)位和十位允許寫(xiě)入端；datain: 計(jì)數(shù)初值輸入端；bcd1n, bcd10n: 計(jì)數(shù)值的個(gè)位輸出和十位輸出；co: 計(jì)數(shù)值進(jìn)位輸出。|結(jié)構(gòu)體ARCHITECTURE behave OF bcd60count ISBEGINEND behave;PROCESS(clk, bcd1wr)BEGINIF(bcd1wr=1) THEN bcd1n=datain;ELS

7、IF(clkEVENT AND clk=1) THEN IF(cin=1) THEN IF(bcd1n=“1001”) THEN bcd1n=0000; ELSE bcd1n=bcd1n+1; END IF; END IF;END IF;END PROCESS;PROCESS (bcd10n, bcd1n, cin)BEGINIF(cin=1 AND bcd1n=“1001” AND bcd10n=“101”) THEN co=1;ELSE co=0;END IF;END PROCESS;PROCESS(clk, bcd10wr)BEGINIF(bcd10wr=1) THEN bcd10n=d

8、atain(2 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THEN IF(cin=1 AND bcd1n=“1001”) THEN IF(bcd10n=“101”) THEN bcd10n=000; ELSE bcd10n=bcd10n+1; END IF; END IF;END IF;END PROCESS;PROCESS(clk, bcd1wr)BEGINIF(bcd1wr=1) THEN bcd1n=datain;ELSIF(clkEVENT AND clk=1) THEN IF(cin=1) THEN IF(bcd1n=“1001”) THEN bcd1n

9、=0000; ELSE bcd1n=bcd1n+1; END IF; END IF;END IF;END PROCESS;進(jìn)程處理個(gè)位計(jì)數(shù)bcd1wr為1時(shí),對(duì)個(gè)位bcd1n進(jìn)行置位在時(shí)鐘信號(hào)驅(qū)動(dòng)下,當(dāng)進(jìn)位輸入cin為1時(shí),若bcd1n為9則歸零;否則bcd1n加1計(jì)數(shù)PROCESS(clk, bcd10wr)BEGINIF(bcd10wr=1) THEN bcd10n=datain(2 DOWNTO 0);ELSIF(clkEVENT AND clk=1) THEN IF(cin=1 AND bcd1n=“1001”) THEN IF(bcd10n=“101”) THEN bcd10n=00

10、0; ELSE bcd10n=bcd10n+1; END IF; END IF;END IF;END PROCESS;進(jìn)程處理十位計(jì)數(shù)bcd10wr為1時(shí),對(duì)十位bcd10n進(jìn)行置位在時(shí)鐘信號(hào)驅(qū)動(dòng)下,當(dāng)進(jìn)位輸入cin為1時(shí), 個(gè)位bcd1n為9，若十位bcd10n為5, 則bcd10n歸零;否則bcd1n加1計(jì)數(shù)PROCESS (bcd10n, bcd1n, cin)BEGINIF (cin=1 AND bcd1n=“1001” AND bcd10n=“101”) THEN co=1;ELSE co=0;END IF;END PROCESS;進(jìn)程處理進(jìn)位輸出當(dāng)個(gè)位bcd1n為9, 十位bcd1

11、0為5, 即計(jì)數(shù)值為59時(shí),若cin為1表示再來(lái)一個(gè)進(jìn)位輸入需要計(jì)數(shù),則計(jì)數(shù)器有進(jìn)位要輸出六十進(jìn)制計(jì)時(shí)器六十進(jìn)制計(jì)時(shí)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY clk_s ISPORT(clk: IN STD_LOGIC; q1: BUFFER INTEGER RANGE 0 TO 9; qt: BUFFER INTEGER RANGE 0 TO 6; co: OUT STD_LOGIC);END clk_s;ARCHITECTURE behav OF clk_s ISBEGINPROCESS(clk)BEGINIF(clkEVENT AN

12、D clk=1) THEN IF(q1=9) THEN q1=0; ELSE q1=q1+1; END IF;END IF;END PROCESS;PROCESS(clk,q1)BEGINIF(clkEVENT AND clk=1) THEN IF(q1=9) THEN IF(qt=5) THEN qt=0; ELSE qt=qt+1; END IF; END IF;END IF;END PROCESS;PROCESS(clk, q1, qt)BEGINIF(clkEVENT AND clk=1) THEN IF(qt=5 AND q1=9) THEN co=1; ELSE co=0; END

13、 IF;END IF;END PROCESS;END behav;二十四進(jìn)制計(jì)數(shù)器ENTITY clk_h ISPORT(clk: IN BIT; q1: BUFFER INTEGER RANGE 0 TO 9; qt: BUFFER INTEGER RANGE 0 TO 2; co: OUT BIT);END clk_h;n二十四進(jìn)制計(jì)數(shù)器的設(shè)計(jì)ARCHITECTURE a_clk_h OF clk_h ISBEGINPROCESS(clk, qt)BEGINIF (clkEVENT AND clk=1) THEN IF (qt=2 and q1=3) THEN q1=0; ELSIF (q

14、1=9) THEN q1=0; ELSE q1=q1+1; END IF;END IF;END PROCESS;PROCESS(q1, clk)BEGINIF (clkEVENT AND clk=1) THEN IF(q1=3) THEN IF (qt=2) THEN qt=0; END IF; ELSIF (q1=9) THEN qt=qt+1; END IF;END IF;END PROCESS;PROCESS(q1, qt, clk)BEGINIF (clkEVENT AND clk=1) THEN IF (q1=3 AND qt=2) THEN co=1; ELSE co=0; END

15、 IF;END IF;END PROCESS;END a_clk_h;n實(shí)驗(yàn): 數(shù)字鐘的設(shè)計(jì)六十進(jìn)制計(jì)數(shù)器 (秒)六十進(jìn)制計(jì)數(shù)器 (分)二十四進(jìn)制計(jì)數(shù)器 (小時(shí))基準(zhǔn)脈沖秒進(jìn)位分進(jìn)位秒顯示分顯示小時(shí)顯示三、分頻器n 分頻器以計(jì)數(shù)器為基礎(chǔ)實(shí)現(xiàn)；n 對(duì)輸入脈沖進(jìn)行計(jì)數(shù)，輸入為N個(gè)脈沖時(shí)，輸出為1個(gè)脈沖，輸出信號(hào)即對(duì)輸入信號(hào)進(jìn)行N分頻。輸入N個(gè)脈沖輸出1個(gè)脈沖ENTITY CNT4 IS PORT ( CLK : IN BIT ; Q : BUFFER INTEGER RANGE 15 DOWNTO 0 ； COUT: OUT BIT ) ; END ; ARCHITECTURE bhv OF CN

16、T4 IS BEGIN PROCESS (CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN IF Q=4 THEN Q=0; ELSE Q = Q + 1 ; END IF; END IF; IF Q =4 THEN COUT = 1; ELSE COUT =4 THEN Q:=0; ELSE Q := Q + 1 ; END IF; END IF; IF QP THEN COUT = 1; ELSE COUT = 0; END IF; END PROCESS ;END bhv; n占空比為50%的偶數(shù)倍分頻器：n方案一：當(dāng)計(jì)數(shù)器計(jì)數(shù)到N/2-1時(shí)，輸出信號(hào)翻轉(zhuǎn)，

17、同時(shí)計(jì)數(shù)器復(fù)位；n方案二：計(jì)數(shù)器為0N/2-1時(shí)，輸出信號(hào)為0；計(jì)數(shù)器為N/2N-1時(shí)，輸出信號(hào)為1。50%占空比的6分頻器Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity clk_div1 isport(clk_in:in std_logic; clk_out:out std_logic);end clk_div1;第一種方案：architecture a of clk_div1 issignal clk_outQ: std_

18、logic:=0;signal countQ:std_logic_vector(2 downto 0):=“000”；begin process(clk_in) begin if(clk_inevent and clk_in=1) then if(countQ/=2)then countQ=countQ+1; else clk_outQ=not clk_outQ; countQ0); end if; end if; end process;clk_out=clk_outQ;end a;第二種方案：architecture b of clk_div1 issignal countQ:std_lo

19、gic_vector(2 downto 0);begin process(clk_in) begin if(clk_inevent and clk_in=1) then if(countQ5) then countQ=countQ+1; else countQ0); end if; end if; end process; process(countQ) begin if (countQ3) then clk_out=0; else clk_out=1; end if; end process;end b;n占空比50%的奇數(shù)倍分頻器： 欲實(shí)現(xiàn)占空比為50%的2N+1分頻器，則需要對(duì)待分頻時(shí)鐘上升沿和下降沿分別進(jìn)行N分頻，然后將兩個(gè)分頻所得的時(shí)鐘信號(hào)相或得到占空比為50%的2N+1分頻器。library ieee;use