0811120933+劉世偉VHDL第二次作業(yè)

1、計(jì)數(shù)顯示電路設(shè)計(jì)課 程： VHDL數(shù)字系統(tǒng)設(shè)計(jì)與測(cè)試?yán)?師： 學(xué) 號(hào)： 姓 名： 推薦精選計(jì)數(shù)顯示電路設(shè)計(jì)一 設(shè)計(jì)要求設(shè)計(jì)輸出為3位BCD碼的計(jì)數(shù)顯示電路。由三個(gè)模塊構(gòu)成：十進(jìn)制計(jì)數(shù)器（BCD_CNT）、分時(shí)總線切換電路（SCAN）和七段顯示譯碼器電路（DEC_LED）。BCD碼計(jì)數(shù)電路從0計(jì)到9然后返回到0從新計(jì)數(shù)。3位BCD碼計(jì)數(shù)器可以實(shí)現(xiàn)從0到999的十進(jìn)制計(jì)數(shù)。要將計(jì)數(shù)過(guò)程用七段顯示LED數(shù)碼管顯示出來(lái)，這里采用動(dòng)態(tài)分時(shí)總線切換電路對(duì)數(shù)碼管進(jìn)行掃描，對(duì)數(shù)碼管依次分時(shí)選中進(jìn)行輸出計(jì)數(shù)的個(gè)、十、百位的數(shù)據(jù)。框圖如圖1：圖1二 設(shè)計(jì)原理圖2是源程序的RTL級(jí)電路圖（RTL Viewer ）。

2、整個(gè)設(shè)計(jì)分十進(jìn)制計(jì)數(shù)器模塊（BCD_CNT）、分時(shí)總線切換電路模塊（SCAN）和七段顯示譯碼器電路模塊（DEC_LED）構(gòu)成?？偟妮斎霝槭M(jìn)制計(jì)數(shù)器時(shí)鐘clk，異步復(fù)位清零信號(hào)reset，分時(shí)總線切換電路時(shí)鐘CL。在reset信號(hào)為0期間，在每個(gè)clk的上升沿計(jì)數(shù)器將加1。在每個(gè)cl的上升沿將會(huì)改變對(duì)三個(gè)數(shù)碼管的掃描選通?？偟妮敵鰹閿?shù)碼管選通信號(hào)sel（三位），輸出到七段數(shù)碼管的數(shù)據(jù)信號(hào)ledout（七位）。圖2為了檢驗(yàn)系統(tǒng)的正確與否，這里還添加了四個(gè)輸出：十進(jìn)制計(jì)數(shù)器輸出c1（四位）、c2（四位）、c3（四位），分時(shí)總線切換電路一個(gè)輸出q（四位），它是對(duì)計(jì)數(shù)器輸出c1、c2、c3進(jìn)行分時(shí)輸出

3、。分時(shí)選通個(gè)、十、百位的數(shù)碼管并將相應(yīng)要顯示的數(shù)據(jù)輸出到七段顯示譯碼器電路（DEC_LED），由此實(shí)現(xiàn)數(shù)碼管的動(dòng)態(tài)掃描顯示。推薦精選三 VHDL實(shí)現(xiàn)（1）頂層模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity top is -定義了一個(gè)頂層的模塊topport(clk,reset:in std_logic; CL:in std_logic; c1,c2,c3:out std_logic_vector(3 downto 0);

4、 ledout:out std_logic_vector(6 downto 0); q:out std_logic_vector(3 downto 0); sel:out std_logic_vector(2 downto 0);end top;architecture content of top issignal c1_1,c2_1,c3_1:std_logic_vector(3 downto 0);signal q_1:std_logic_vector(3 downto 0);-因?yàn)閏1,c2,c3，q是中間信號(hào)量，也是輸出，故引入c1_1,c2_1,c3_1q_1作為中間變量compo

5、nent BCD_CNT is -定義元件BCD_CNT port(clk,reset:in std_logic; c1,c2,c3:out std_logic_vector(3 downto 0);end component;component SCAN is -定義元件SCANport( c1,c2,c3:in std_logic_vector(3 downto 0); CL:in std_logic; q:out std_logic_vector(3 downto 0); sel:out std_logic_vector(2 downto 0);end component;compone

6、nt DEC_LED is -定義元件DEC_LEDport( q:in std_logic_vector(3 downto 0); ledout:out std_logic_vector(6 downto 0);end component;beginu1: BCD_CNT port map (clk,reset,c1_1,c2_1,c3_1); -調(diào)用元件實(shí)例BCD_CNTu2: SCAN port map(c1_1,c2_1,c3_1,CL,q_1,sel); -調(diào)用元件實(shí)例SCANu3: DEC_LED port map(q_1,ledout); -調(diào)用元件實(shí)例DEC_LED推薦精選c1

7、<=c1_1; -中間變量值賦給輸出c2<=c2_1;c3<=c3_1;q <=q_1; end content;（2）十進(jìn)制計(jì)數(shù)器電路（BCD_CNT）模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity BCD_CNT is port(clk,reset:in std_logic; c1,c2,c3:out std_logic_vector(3 downto 0);end BCD_CNT;archi

8、tecture cnt of BCD_CNT issignal cn1,cn2,cn3:std_logic_vector(3 downto 0); begin cnt1:process(clk,reset) begin if(reset='1') then cn1<="0000" elsif(clk'event and clk='1') then if(cn1<9) then cn1<=cn1+1; else cn1<="0000" end if; end if; end process c

9、nt1; c1<=cn1; -個(gè)位計(jì)數(shù) cnt2:process(cn1(3),reset) -cn1(3)是clk的十分頻 begin if(reset='1') then cn2<="0000" elsif(cn1(3)'event and cn1(3)='0') then if(cn2<9) then cn2<=cn2+1; else cn2<="0000" end if; end if; end process cnt2; c2<=cn2; -十位計(jì)數(shù) cnt3:proc

10、ess(cn2(3),reset) -cn2(3)是clk的一百分頻 begin if(reset='1') then cn3<="0000" elsif(cn2(3)'event and cn2(3)='0') then if(cn3<9) then cn3<=cn3+1;推薦精選 else cn3<="0000" end if; end if; end process cnt3; c3<=cn3; -百位計(jì)數(shù)end cnt;（3）分時(shí)總線切換電路（SCAN）模塊：library i

11、eee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity SCAN is port( c1,c2,c3:in std_logic_vector(3 downto 0); cl:in std_logic; q:out std_logic_vector(3 downto 0); sel:out std_logic_vector(2 downto 0); end SCAN;architecture one of SCAN issignal cnt:std_lo

12、gic_vector(1 downto 0);signal q_temp:std_logic_vector(3 downto 0);signal sel_temp:std_logic_vector(2 downto 0); begin p1:process(cl) -模3計(jì)數(shù)器 begin if(cl'event and cl='1') then if(cnt<2) then cnt<=cnt+1; else cnt<="00" end if; end if; end process p1; p2:process(cnt) begi

13、n case cnt is -產(chǎn)生分時(shí)切換信號(hào)q_temp; when "00" => q_temp<=c1; sel_temp<="001" when "01" => q_temp<=c2; sel_temp<="010" when "10" => q_temp<=c3; sel_temp<="100" when others=> null; end case; end process p2;推薦精選 q<=

14、q_temp; sel<=sel_temp;end one;（4）七段顯示譯碼器電路（DEC_LED）模塊：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity DEC_LED is port( q:in std_logic_vector(3 downto 0); ledout:out std_logic_vector(6 downto 0);end DEC_LED;architecture one of DEC_LED is

15、 begin process(q) -七段譯碼電路 begin case q is when "0000" => ledout<="0111111" when "0001" => ledout<="0000110" when "0010" => ledout<="1011011" when "0011" => ledout<="1001111" when "0100"

16、=> ledout<="1100110" when "0101" => ledout<="1101101" when "0110" => ledout<="1111101" when "0111" => ledout<="0000111" when "1000" => ledout<="1111111" when "1001" =>

17、 ledout<="1101111" when others => null; end case; end process;end one; 四 仿真結(jié)果及分析圖2是電路的總體輸入輸出仿真波形。推薦精選圖3由圖3可以看出，當(dāng)掃描頻率CL很大的時(shí)候，sel從1、2、4變化，即在一個(gè)時(shí)刻，sel只有一位為高，計(jì)數(shù)器的輸出只有一位C1或C2或C3選中，并且正確的輸出。當(dāng)復(fù)位信號(hào)reset先為高的時(shí)候清零，當(dāng)變?yōu)榈偷臅r(shí)候隨著clk上升沿到來(lái)計(jì)數(shù)器開(kāi)始計(jì)數(shù)，從000999，c1為個(gè)位,十位為c2,c3是百位。計(jì)數(shù)器為0時(shí)，ledout輸出為十六進(jìn)制3F（2進(jìn)制0111111），為1時(shí)輸出為為06H，等等，輸出正確。五 仿真結(jié)果的討論由分析可知，掃描時(shí)鐘CL必須要