基于fpga的電子琴說明書

1、3.8程序設(shè)計流程圖 程序設(shè)計的流程圖如圖4所示。 開始選擇播放模式還是彈奏模式？對時鐘信號進行分頻得到4分音符的頻率等待用戶輸入按鍵等待用戶輸入樂曲編號通過對鍵盤的掃描確定按鍵的位置顯示樂曲編號根據(jù)所按鍵盤按鍵的位置，發(fā)出相應(yīng)的頻率根據(jù)樂曲的編號放出相應(yīng)的樂譜的頻率蜂鳴器發(fā)聲圖4 程序設(shè)計流程圖 本設(shè)計所選用的管腳接口如圖6所示： 圖6 管腳借口示意圖4、電子琴設(shè)計4.1樂曲播放功能設(shè)計 根據(jù)樂曲發(fā)聲的基本原理，樂曲播放模塊的設(shè)計思路是通過50MHz時鐘分頻的出1MHz信號，再對1MHz信號分頻，獲得音符節(jié)拍頻率，通過查表方式獲取音符分頻數(shù)作為音符分頻器模塊分頻的依據(jù)，將1MHz時鐘分頻獲得

2、合適的音符頻率，輸出至音頻功放模塊。電路結(jié)構(gòu)框圖如圖7所示。音頻輸出 4Hz時鐘系統(tǒng)頻率節(jié)拍控制分頻模塊音符分頻器樂曲選擇與長度計數(shù)器樂曲存儲 LED顯示模塊圖7 樂曲播放模塊結(jié)構(gòu)圖樂曲播放文件外部引腳及生成的符號如圖8所示。其中clk為 50MHz系統(tǒng)頻率，start為樂曲播放啟動信號，sel為模塊選擇信號，choose為樂曲選擇信號，本設(shè)計設(shè)定檔sel為高電平時，模塊工作，out_sound1為音頻輸出信號，seg6為數(shù)碼管段碼輸出信號.圖8 樂曲播放模塊符號4.1.1節(jié)拍控制分頻模塊 節(jié)拍控制分頻模塊主要用于產(chǎn)生樂曲的節(jié)拍，控制樂曲播放的節(jié)奏。50MHz的系統(tǒng)頻率經(jīng)過50次的分頻得到1M

3、Hz的頻率，再對1MHz信號進行250000次分頻，可以得到4分音符持續(xù)時間的頻率，作為第二個進程的時鐘信號，它的目的是控制每個音階之間的停頓時間，此處便是1/4=0.25s，其外部引腳及生成的符號如圖9所示:圖9 節(jié)拍控制分頻模塊符號其主要VHDL代碼如下所示：process(start,clk)begin if start='0'then clk_1MHz<='0' max_50 <= "000000" elsif clk'event and clk='1' then if max_50>= &q

4、uot;110001"then max_50<="000000" else max_50<=max_50+1; end if; if max_50="000000"then clk_1MHz<='1' else clk_1MHz<='0' end if; end if;end process;process(start,clk_1MHz)begin if start='0'then clk_4Hz<='0' max_250000 <= "

5、;0000000" elsif clk_1MHz'event and clk_1MHz='1' then if max_250000>= "1111111"then max_250000<="0000000" else max_250000<=max_250000+1; end if; if max_250000="0000000"then clk_4Hz<='1' else clk_4Hz<='0' end if; end if;end

6、process;4.1.3樂曲存儲模塊樂曲存儲模塊中存放的是樂曲各個音符的分頻值，假設(shè)系統(tǒng)頻率為1Mhz，根據(jù)表1中音符的頻率值，求得各音符的分頻系數(shù)如表2所示：表2 1MHz下簡譜中音符的分頻系數(shù) 音名 分頻系數(shù) 音名 分頻系數(shù)音名 分頻系數(shù) 低音1 3823 中音11911 高音1956 低音23405 中音21703 高音2851 低音33034 中音31517 高音3758 低音42863 中音41432 高音4716 低音52551 中音51276 高音5638 低音62273 中音61137 高音6568 低音72025 中音71012 高音7506 其中存放的兩首樂曲分別是：第一

7、首揮著翅膀的女孩、第二首歌菊花臺。4.3頂層文件設(shè)計 采用原理圖的輸入方式，將上述樂曲播放和樂曲彈奏兩個文件分別生成符號文件，并在頂層文件中調(diào)用，電路圖如圖16所示。 圖16頂層文件輸入文件其主要VHDL代碼如下：Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity top is port (clk0:in std_logic; start0:in std_logic; sel0:in std_logic; kbcol0:in st

8、d_logic_vector(0 to 3); kbrow0:out std_logic_vector(0 to 3); out_sound0:out std_logic; seg60:out std_logic_vector(0 to 6); choose0:in std_logic_vector(0 to 1) ); end;architecture one of top is component music port(clk:in std_logic; start:in std_logic; out_sound1:out std_logic; sel:in std_logic; choo

9、se:in std_logic_vector(0 to 1); seg6:out std_logic_vector(0 to 6) ); end component; component piano port (clk,start:in std_logic; kbcol:in std_logic_vector(0 to 3); kbrow:out std_logic_vector(0 to 3); out_sound2:out std_logic; sel:in std_logic );end component;component or22 port(a,b:in std_logic; c:

10、out std_logic);end component;signal g,h:std_logic;beginu1:music port map(clk=>clk0,start=>start0,choose=>choose0,sel=>sel0,out_sound1=>g,seg6=>seg60);u2:piano port map(kbcol=>kbcol0,kbrow=>kbrow0,clk=>clk0,sel=>sel0,start=>start0,out_sound2=>h);u3:or22 port map(a=

11、>g,b=>h,c=>out_sound0);end;6、總結(jié)本設(shè)計利用了硬件描述語言VHDL實現(xiàn)了電子琴的自動演奏和鍵盤輸入發(fā)音的簡易功能，經(jīng)過編程，綜合，仿真，下載，調(diào)試，電路板制作，最終做出了成品，測試情況也良好，能夠準確實現(xiàn)音階的發(fā)音功能，可切換到樂曲播放存儲好的樂曲，可根據(jù)需要更改程序從而實現(xiàn)不同樂曲的存儲，也可以通過在4*4鍵盤上的按鍵來彈奏出不同的音調(diào)。在設(shè)計過程，由于對音樂的知識不夠熟悉，所以沒有實現(xiàn)電子琴那么完美的音樂。在本系統(tǒng)設(shè)計調(diào)試過程中，軟件和硬件都出現(xiàn)了一些小錯誤。例如在焊接電路時，由于不夠細心，把共陽極數(shù)碼管的公共端焊接到地端上了；在把外圍電路板上

12、連接芯片時，由于選錯了一兩個管腳，而導(dǎo)致結(jié)果與預(yù)期的不同，浪費了很多時間找原因。在軟硬件結(jié)合調(diào)試時，自動彈奏音樂時出現(xiàn)了噪音現(xiàn)象，經(jīng)過了仔細檢查所有程序，發(fā)現(xiàn)了問題是出現(xiàn)在分頻模塊的編寫上，所用芯片的工作頻率是50MHz，而程序中我的工作頻率卻設(shè)定為1MHz，于是我在播放模塊中增加多一個50分頻的程序，從而把問題解決了。61樂曲播放模塊總結(jié)如果想要播放更多首樂曲的話，只需要增加choose的相應(yīng)位數(shù)，和增加存儲模塊中的樂曲數(shù)。比如要播放8首樂曲，則可以設(shè)置choose：in std_logic_vector(2 downto 0)，其中“000”代表第一首，“001”代表第二首，“010”代表

13、第三首，“011”代表第五首，“100”代表第六首，“101代表第七首，“111”代表第八首。想要設(shè)置更多樂曲，可根據(jù)需要設(shè)定好合適的choose位數(shù)。另外，樂曲播放模塊還可以采用查表方式來播放存儲的樂曲，即在ROM中寫入所要播放音樂的全部頻率，通過編程來一一查找每一個頻率，從而實現(xiàn)樂曲的播放。62樂曲彈奏模塊總結(jié)除了采用4*4鍵盤作為按鍵輸入外，還可以選擇3*7鍵盤，采用3*7鍵盤的話，就可以設(shè)置每一個按鍵代表一個音符，也就是說21個音符都可以有不同的按鍵來彈奏，這樣在彈奏樂曲時，在選擇高、中、低音轉(zhuǎn)換時，就不需要額外的按鍵，而且把按鍵的利用率達到100%,而在4*4鍵盤中，有6個按鍵是沒用

14、的，利用率比3*7鍵盤低。和4*4鍵盤掃描類似，3*7鍵盤可以采用掃描3個列檢測7個行，也可以采用掃描7個列檢測3個行，這兩種只是編程方式不同，道理一樣。如果采用掃描7個列檢測3個行的話，列掃描信號由列引腳“列1列2列3列4列5列6列7”進入鍵盤，以1111110、1111101、1111011、1110111、1101111、1011111、0111111的順序每次掃描其中的一列，然后讀取行引腳的電平信號就可以判斷是哪個按鍵被按下。例如，當(dāng)掃描信號為1111110時表示正在掃描列7，如果該列沒按鍵按下，則由行信號讀出的值為1111111；反之，當(dāng)?shù)诙杏邪存I按下，則由行信號“行1行2行3”讀

15、出的值為101，鍵盤的列選擇信號以及行選擇信號均為低電平有效。附錄一 不工作時 播放一首樂曲時，數(shù)碼管也顯示1 播放第二首樂曲時，數(shù)碼管也顯示2 外圍電路板原理圖附錄二程序：頂層文件：Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity top is port (clk0:in std_logic; start0:in std_logic; sel0:in std_logic; kbcol0:in std_logic_vector(

16、0 to 3); kbrow0:out std_logic_vector(0 to 3); out_sound0:out std_logic; seg60:out std_logic_vector(0 to 6); choose0:in std_logic_vector(0 to 1) ); end;architecture one of top is component music port(clk:in std_logic; start:in std_logic; out_sound1:out std_logic; sel:in std_logic; choose:in std_logic

17、_vector(0 to 1); seg6:out std_logic_vector(0 to 6) ); end component; component piano port (clk,start:in std_logic; kbcol:in std_logic_vector(0 to 3); kbrow:out std_logic_vector(0 to 3); out_sound2:out std_logic; sel:in std_logic );end component;component or22 port(a,b:in std_logic; c:out std_logic);

18、end component;signal g,h:std_logic;beginu1:music port map(clk=>clk0,start=>start0,choose=>choose0,sel=>sel0,out_sound1=>g,seg6=>seg60);u2:piano port map(kbcol=>kbcol0,kbrow=>kbrow0,clk=>clk0,sel=>sel0,start=>start0,out_sound2=>h);u3:or22 port map(a=>g,b=>h,c

19、=>out_sound0);end;樂曲播放模塊：Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity music isgeneric(mid8:integer range 1000 to 4000:= 1911;mid9:integer range 1000 to 4000:= 1703;mid10:integer range 1000 to 4000:= 1517;mid11:integer range 1000 to 4

20、000:= 1432;mid12:integer range 1000 to 4000:= 1276;mid13:integer range 1000 to 4000:= 1137;mid14:integer range 1000 to 4000:= 1012;low1:integer range 1000 to 4000:= 3823;low2:integer range 1000 to 4000:= 3405;low3:integer range 1000 to 4000:= 3034;low4:integer range 1000 to 4000:= 2863;low5:integer

21、range 1000 to 4000:= 2551;low6:integer range 1000 to 4000:= 2273;low7:integer range 1000 to 4000:= 2025;high15:integer range 100 to 4000:= 956;high16:integer range 100 to 4000:= 851;high17:integer range 100 to 4000:= 758;high18:integer range 100 to 4000:= 716;high19:integer range 100 to 4000:= 638;h

22、igh20:integer range 100 to 4000:= 568;high21:integer range 100 to 4000:= 506);port(clk:in std_logic; start:in std_logic; out_sound1:out std_logic; sel:in std_logic; choose:in std_logic_vector(0 to 1) seg6:out std_logic_vector(0 to 6) );end music;architecture behav of music issignal clk_4Hz : std_log

23、ic;signal clk_1MHz : std_logic;signal count : integer range 0 to 4096;signal freq : integer range 0 to 4096;signal counter : integer range 0 to 150;signal max_250000 : std_logic_vector(17 downto 0);signal tmp:integer range 0 to 100;signal rset:std_logic;signal out_sound12:std_logic;signal out_sound1

24、1:std_logic;signal max_50 : std_logic_vector(5 downto 0);beginprocess(start,clk)begin if start='0'then clk_1MHz<='0' max_50 <= "000000" elsif clk'event and clk='1' then if max_50>= "110001"then max_50<="000000" else max_50<=max

25、_50+1; end if; if max_50="000000"then clk_1MHz<='1' else clk_1MHz<='0' end if; end if;end process;process(start,clk_1MHz)begin if start='0'then clk_4Hz<='0' max_250000 <= "0000000" elsif clk_1MHz'event and clk_1MHz='1' then

26、if max_250000>= "1111111"then max_250000<="0000000" else max_250000<=max_250000+1; end if; if max_250000="0000000"then clk_4Hz<='1' else clk_4Hz<='0' end if; end if;end process; process(choose,clk) -選歌信號檢測進程：variable a:std_logic_vector(0 t

27、o 1);variable b:std_logic_vector(0 to 1);variable c:std_logic_vector(0 to 1);beginif clk'event and clk='1' thenb:=a;a:=choose;c:= b - a;end if;if c="00" then rset<='0'else rset<='1'end if;end process; process(clk_4Hz,rset,start,choose) beginif start='0

28、' then tmp<=0;elsif rset='1' then tmp<=0;elsif (clk_4Hz'event and clk_4Hz='1') then if tmp>=56 then tmp<=0;elsetmp<=tmp+1; end if;end if;case choose iswhen "01" => counter<=tmp;seg6<="1111001"when "10" => counter<=tm

29、p+57;seg6<="0100100"when others => counter<=0;seg6<="1000000"end case;end process; process(counter)begin case counter is when 0=>freq<=0; when 1=>freq<=mid10; when 2=>freq<=mid10; when 3=>freq<=mid11; when 4=>freq<=mid12; when 5=>freq&

30、lt;=mid12; when 6=>freq<=mid8; when 7=>freq<=mid9; when 8=>freq<=mid10; when 9=>freq<=mid10; when 10=>freq<=mid10; when 11=>freq<=mid11; when 12=>freq<=mid12; when 13=>freq<=mid12; when 14=>freq<=mid9; when 15=>freq<=mid10; when 16=>freq

31、<=mid11; when 17=>freq<=mid11; when 18=>freq<=mid11; when 19=>freq<=mid10; when 20=>freq<=mid8; when 21=>freq<=mid8; when 22=>freq<=mid11; when 23=>freq<=mid10; when 24=>freq<=mid11; when 25=>freq<=mid11; when 26=>freq<=low6; when 27=>

32、;freq<=mid8; when 28=>freq<=mid9; when 29=>freq<=mid9; when 30=>freq<=mid8; when 31=>freq<=mid9; when 32=>freq<=mid10; when 33=>freq<=mid10; when 34=>freq<=mid10; when 35=>freq<=mid11; when 36=>freq<=mid12; when 37=>freq<=mid12; when 38=

33、>freq<=mid13; when 39=>freq<=mid14; when 40=>freq<=high15; when 41=>freq<=high15; when 42=>freq<=mid10; when 43=>freq<=mid11; when 44=>freq<=mid12; when 45=>freq<=mid12; when 46=>freq<=mid9; when 47=>freq<=mid10; when 48=>freq<=mid11;

34、 when 49=>freq<=mid10; when 50=>freq<=mid11; when 51=>freq<=high15; when 52=>freq<=high15; when 53=>freq<=high15; when 54=>freq<=mid9; when 55=>freq<=mid10; when 56=>freq<=mid11; when 57=>freq<=high15; when 58=>freq<=mid10; when 59=>freq

35、<=mid10; when 60=>freq<=mid10; when 61=>freq<=mid9; when 62=>freq<=mid10; when 63=>freq<=0; when 64=>freq<=0; when 65=>freq<=0; when 66=>freq<=mid10; when 67=>freq<=mid12; when 68=>freq<=mid10; when 69=>freq<=mid9; when 70=>freq<=m

36、id10; when 71=>freq<=mid10; when 72=>freq<=mid10; when 73=>freq<=mid10; when 74=>freq<=mid8; when 75=>freq<=mid8; when 76=>freq<=mid8; when 77=>freq<=mid9; when 78=>freq<=mid10; when 79=>freq<=mid12; when 80=>freq<=mid10; when 81=>freq&l

37、t;=mid10; when 82=>freq<=mid9; when 83=>freq<=mid9; when 84=>freq<=mid9; when 85=>freq<=mid8; when 86=>freq<=mid9; when 87=>freq<=mid9; when 88=>freq<=mid9; when 89=>freq<=mid9; when 90=>freq<=mid10; when 91=>freq<=mid10; when 92=>freq&l

38、t;=mid10; when 93=>freq<=mid12; when 94=>freq<=mid13; when 95=>freq<=mid12; when 96=>freq<=mid12; when 97=>freq<=mid12; when 98=>freq<=mid13; when 99=>freq<=mid12; when 100=>freq<=mid12; when 101=>freq<=mid10; when 102=>freq<=mid12; when 10

39、3=>freq<=mid12; when 104=>freq<=mid12; when 105=>freq<=low5; when 106=>freq<=mid10; when 107=>freq<=mid10; when 108=>freq<=mid9; when 109=>freq<=mid9; when 110=>freq<=mid12; when 111=>freq<=mid12; when 112=>freq<=mid10; when 113=>freq<

40、;=mid9; when others=>freq<=0; end case;end process;process(clk_1MHz,start,sel)begin if sel='0'then out_sound12<='0' else if start='0'then count<=0; out_sound12<='0' elsif clk_1MHz'event and clk_1MHz='1'then if freq=0 then out_sound12<=

41、9;0' elsif count=0 then count<=freq; out_sound12<='1' else count<=count-1; out_sound12<='0' end if; end if; end if;end process;PROCESS(out_sound12) -二分頒，方波輸出BEGIN IF out_sound12 'EVENT AND out_sound12='1' THEN out_sound11 <=NOT out_sound11; END IF; out_

42、sound1<=out_sound11;END PROCESS;end behav; 樂曲彈奏模塊：Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity piano isport (clk,start:in std_logic; kbcol:in std_logic_vector(0 to 3); kbrow:out std_logic_vector(0 to 3); out_sound2:out std_logic; sel

43、:in std_logic );end entity;architecture piano of piano issignal state:std_logic_vector(2 downto 0);signal clk1:std_logic;signal clk_1MHz : std_logic;signal d:std_logic_vector(4 downto 0);signal snote:std_logic_vector(4 downto 0);signal sscal:std_logic_vector(1 downto 0);signal cnt,scnt:std_logic_vec

44、tor(9 downto 0);signal ctrln:std_logic_vector(2 downto 0);signal count,freq:integer range 0 to 4096;signal out_sound22:std_logic;signal out_sound21:std_logic;signal d0,d1,d2,d3,d_reg:std_logic_vector(4 downto 0);signal max_50 : std_logic_vector(5 downto 0);constant low1:integer:=3822; constant low2:

45、integer:=3405;constant low3:integer:=3034;constant low4:integer:=2863;constant low5:integer:=2551;constant low6:integer:=2273;constant low7:integer:=2025;constant mid1:integer:=1911;constant mid2:integer:=1703;constant mid3:integer:=1517;constant mid4:integer:=1432;constant mid5:integer:=1276;consta

46、nt mid6:integer:=1137;constant mid7:integer:=1012;constant high1:integer:=956;constant high2:integer:=851;constant high3:integer:=758;constant high4:integer:=716;constant high5:integer:=638;constant high6:integer:=568;constant high7:integer:=506;constant stop:integer:=0;beginprocess(start,clk)begin

47、if start='0'then clk_1MHz<='0' max_50 <= "000000" elsif clk'event and clk='1' then if max_50>= "110001"then max_50<="000000" else max_50<=max_50+1; end if; if max_50="000000"then clk_1MHz<='1' else clk_1MHz

48、<='0' end if; end if;end process;clk1<=cnt(9);process(clk_1MHz)beginif clk_1MHz'event and clk_1MHz='1'thencnt<=cnt+1;end if;end process;d<=d0 or d1 or d2 or d3;process(clk1)beginif clk1'event and clk1='1'thencase state iswhen "000"=>kbrow<=

49、"1110"state<="001" case kbcol is when"0111"=>d0<="11111" when"1011"=>d0<="11011" when"1101"=>d0<="10111" when"1110"=>d0<="10011" when others=>d0<="00000" end

50、 case;when"001"=>kbrow<="1101"state<="010" case kbcol is when"0111"=>d1<="11110" when"1011"=>d1<="11010" when"1101"=>d1<="10110" when"1110"=>d1<="10010" when

51、 others=>d1<="00000" end case;when"010"=>kbrow<="1011"state<="011" case kbcol is when"0111"=>d2<="11101" when"1011"=>d2<="11001" when"1101"=>d2<="10101" when"1110

52、"=>d2<="10001" when others=>d2<="00000" end case;when"011"=>kbrow<="0111"state<="100" case kbcol is when"0111"=>d3<="11100" when"1011"=>d3<="11000" when"1101"=>

53、;d3<="10100" when"1110"=>d3<="10000" when others=>d3<="00000" end case; when"100"=>state<="000" if d="00000"then d_reg<=d; if scnt=100 then snote<="00000" else scnt<=scnt+1; end if; else scn

54、t<="0000000000" if d /= d_reg then d_reg<=d; if d>="10001"and d<="10111"then snote<=sscal&d(2 downto 0); elsif d="11010"then sscal<="11" elsif d="11011"then sscal<="10" elsif d="11100"then sscal&

55、lt;="01" end if; end if; end if;when others=>state<="000"end case;-end if;end if;end process;process(snote)begin case snote is when"01001"=>freq<=low1; when"01010"=>freq<=low2; when"01011"=>freq<=low3; when"01100"=&g

56、t;freq<=low4; when"01101"=>freq<=low5; when"01110"=>freq<=low6; when"01111"=>freq<=low7; when"10001"=>freq<=mid1; when"10010"=>freq<=mid2; when"10011"=>freq<=mid3; when"10100"=>freq<=mi

57、d4; when"10101"=>freq<=mid5; when"10110"=>freq<=mid6; when"10111"=>freq<=mid7; when"11001"=>freq<=high1; when"11010"=>freq<=high2; when"11011"=>freq<=high3; when"11100"=>freq<=high4; when"11101"=>freq<=high5; when"11110"=>freq<=high6; when"11111&quo