FPGA控制LED漢字滾動顯示器設計方案

1、封面作者： PanHongliang僅供個人學習基于 FPGA 控制的 LED 漢字滾動顯示器設計2 硬件原理圖整個電路由五大部分組成：時鐘計數模塊GEL_CLK,存儲漢字字模的 ROM模塊ROMZI ，數據分配器模塊MUX ，移位模塊YW 及顯示模塊 XIANSH-I 。時鐘計數模塊用于產生整個電路所需要的時鐘及其對時鐘的計數值，例如：移位時鐘CLK YW ，移位計數器CNT YW,字計數器 CNT WORD,顯示掃描計數器 CNT SM。ROMZI模塊是由 Qualtus n 中的LPM 1PORT ROM定制成，用來存儲 8個待顯示的漢字。 MUX模塊用于在掃描時鐘及 掃描計數器的作用下

2、，從ROM 中讀出一個漢字的 8 個行字模信息，送給移位模塊YW ，YW模塊在移位時鐘及移位計數器作用下，根據SELECT信號選擇對讀出的字模信息，進行相應的移位（左移、右移、上移、下移） 后，最后送顯示模塊DISP 驅動 LED 點陣顯示漢字。原理圖如圖 2 所示。3 2 ROMZI 模塊利用LPM參數化模塊庫中單口 ROM,利用 Qualtus n中的 MegaWizard Plug-InManager 定制而成，定制前首先要制作LPM ROM 初始化文件，其中存儲待顯示漢字的字模數據，然后按照 LPM MegaWizardPlug-In Manager 的向導提示，結合設計要求進行定 制

3、。圖 3 為所定制 ROM 中的初始化漢字 “元旦生日開心快樂” 的字型碼。數據分配模塊MUX 要求能在 8 個時鐘作用下，從 ROM 中讀出一行（一個漢字的8 個字型碼 ）分別送到數據分配器中的 WLlWL8輸出端。圖4為數據分配模塊在掃描時鐘作用下讀取的字模數 據，比較圖 3 和圖 4 可知，仿真結果正確，能滿足題目要求。3 3 移位模塊 YW移位模塊 YW 是整個設計的核心，行掃描實現左移，是通過每來一個移位時鐘，將每一行的字模按位左移一位，掃描時鐘到來時送出移位后的新字模。通過8 次移位，可將一個漢字移出點陣平面，按類似的道理，也可以將一個漢字經 8 次移位后移進點陣平面。本例（圖2）

4、中，CNT YW為移位時鐘的計數值，以WLlWL8為欲顯示漢字的原始字模，L10L80為移位后從列上送出的 8行顯示字模信息，LLlLL8為8個原始字模信息未送出 位的暫存信號。設計中需要16個移位時鐘，通過前 8個時鐘將 WLlWL8字模移進LED點陣平面，再經后 8 個時鐘，將漢字又一位一位地移出。移位設計參考文獻中有關移位寄 存器的設計，分計數值為“ 0000"和非"0000" 兩部分處理，對第一行字模的處理為：其他行可按相同方法處理，具體參見如下的程序：library IEEE 。use IEEE.std_logic_1164.all 。use ieee.

5、std_logic_arith.all 。use ieee.std_logic_unsigned.all 。entity memtest isport (rst : in std_logic 。clk : in std_logic 。den : in std_logic 。 -serial input enablerxd : in std_logic 。 -serial input dataouten : in std_logic 。 - output data requestrdmem : out std_logic 。 -read memorywrmem : out std_logic 。

6、 - write memorycsmem : out std_logic 。 - chip enable memorymemdata: inout std_logic_vector(7 downto 0) 。 - memory data interfacememaddr: out std_logic_vector(2 downto 0) 。 - memory addressdataout: out std_logic_vector(7 downto 0) 。 -data outputdataclkout: out std_logic -data output sync clk)。end mem

7、test。architecture behav of memtest isconstant s0 :std_logic_vector(2 downto 0):= "001" 。constant s1 :std_logic_vector(2 downto 0):= "010" 。constant s2 :std_logic_vector(2 downto 0):= "100" 。signal ss: std_logic_vector(2 downto 0) 。signal rdmemaddr,wrmemaddr: std_logic_v

8、ector(2 downto 0) 。signal rxdcnt: std_logic_vector(3 downto 0) 。signal rdmemdata, wrmemdata :std_logic_vector(7 downto 0) 。signal wrmem_s, wrrdy, dataclkout_s :std_logic 。beginprocess(rst,clk)beginif rst = '0' thenwrmemdata <= (others =>'0') 。wrmemdata(7) <= wrmemdata(6) 。wr

9、memdata(6) <= wrmemdata(5) 。wrmemdata(5) <= wrmemdata(4) 。wrmemdata(4) <= wrmemdata(3) 。wrmemdata(3) <= wrmemdata(2) 。wrmemdata(2) <= wrmemdata(1) 。wrmemdata(1) <= wrmemdata(0) 。wrmemdata(0) <= rxd 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thenrxdcnt

10、 <= (others =>'0') 。elsif clk'event and clk = '1' thenif den = '1' thenif rxdcnt = 9 thenrxdcnt <= rxdcnt 。elserxdcnt <= rxdcnt +1 。end if 。elserxdcnt <= (others =>'0') 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thenss

11、 <= s0。elsif clk'event and clk = '1' thencase ss iswhen s0 =>if wrrdy = '1' thenss <= s1。elsif outen = '1' thenss <= s2。end if 。when s1 =>ss <= s0。when s2 =>ss <= s0。when others =>ss <= s0。end case。end if 。end process。process(rst,clk)beginif

12、rst = '0' thenwrrdy <= '0' 。elsif clk'event and clk = '1' thenif ss = s1 thenwrrdy <= '0' 。elseif rxdcnt = 8 thenwrrdy <= '1' 。elsewrrdy <= '0' 。end if 。end if 。end if 。wrmem_s <= '0' when ss = s1 else '1' 。rdmem <

13、= '0' when ss = s2 else '1' 。csmem <= '1' when ss = s1 or ss = s2 else '0'。process(rst,clk)beginif rst = '0' thendataclkout_s <= '0' 。elsif clk'event and clk = '1' thenif ss = s2 thendataclkout_s <= '1' 。elsedataclkout_s &l

14、t;= '0' 。end if 。end if 。end process。process(clk)beginif clk'event and clk = '1' thendataclkout <= dataclkout_s 。end if 。end process。process(rst,clk)beginif rst = '0' thendataout <= (others =>'0') 。elsif clk'event and clk = '1' thenif ss = s2

15、thendataout <= rdmemdata。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thenwrmemaddr <= (others =>'0') 。elsif clk'event and clk = '1' thenif ss = s1 thenwrmemaddr <= wrmemaddr +1 。end if 。end if 。end process。process(rst,clk)beginif rst = '0

16、' thenrdmemaddr <= (others =>'0') 。elsif clk'event and clk = '1' thenif ss = s2 thenrdmemaddr <= rdmemaddr +1 。end if 。end if 。end process。memaddr <= wrmemaddr when wrmem_s = '0' else rdmemaddr 。memdata <= wrmemdata when wrmem_s = '0' else "

17、;ZZZZZZZZ" 。rdmemdata <= memdata 。wrmem <= wrmem_s 。end behav。library IEEE 。use IEEE.std_logic_1164.all 。use ieee.std_logic_arith.all 。use ieee.std_logic_unsigned.all 。entity states isport (rst : in std_logic 。clk : in std_logic 。nscar: in std_logic 。ewcar: in std_logic 。nsred: out std_lo

18、gic 。nsgreen: out std_logic 。nsyellow: out std_logic 。ewred: out std_logic 。ewgreen: out std_logic 。ewyellow: out std_logic)。end states。architecture behav of states isconstant s0 :std_logic_vector(1 downto 0):= "00" 。 - ewgreenconstant s1 :std_logic_vector(1 downto 0):= "01" 。con

19、stant s2 :std_logic_vector(1 downto 0):= "11" 。 - nsgreenconstant s3 :std_logic_vector(1 downto 0):= "10" 。signal ss: std_logic_vector(1 downto 0) 。signal tm60s,tm40s :std_logic_vector(5 downto 0) 。signal tm3s :std_logic_vector(1 downto 0) 。signal entm60s,entm40s,entm3s,tm60soc,t

20、m40soc,tm3soc :std_logic 。beginprocess(rst,clk)beginif rst = '0' thenss <= s0。when s0 =>if nscar = '1' thenif ewcar = '1' thenif tm60soc = '1' thenss <= s1。end if。elsess <= s1。end if 。end if 。when s1 =>if tm3soc = '1' thenss <= s2。end if 。whe

21、n s2 =>if nscar = '1' thenif ewcar = '1' thenif tm40soc = '1' thenss <= s3。end if。end if 。elsess <= s3。end if 。when s3 =>if tm3soc = '1' thenss <= s0。end if 。when others =>ss <= s0。end case。end if 。end process。process(rst,clk)beginif rst = '0&

22、#39; thenentm60s <= '0' 。elsif clk'event and clk = '1' thenif ss = s0 thenentm60s <= '1' 。elseentm60s <= '0' 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thenentm40s <= '0' 。elsif clk'event and clk = '1' th

23、enif ss = s2 thenentm40s <= '1' 。elseentm40s <= '0' 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thenentm3s <= '0' 。elsif clk'event and clk = '1' thenif ss = s1 or ss = s3 thenentm3s <= '1' 。elseentm3s <= '0'

24、; 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thentm60s <= B"000000" 。elsif clk'event and clk = '1' thenif entm60s = '1' thenif tm60s = 59 thentm60s <= B"000000" 。elsetm60s <= tm60s + 1 。end if 。elsetm60s <= B"000000

25、" 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thentm40s <= B"000000" 。elsif clk'event and clk = '1' thenif entm40s = '1' thenif tm40s = 39 thentm40s <= B"000000" 。elseend if 。elsetm40s <= B"000000" 。end if 。en

26、d if 。end process。process(rst,clk)beginif rst = '0' thentm3s <= B"00" 。elsif clk'event and clk = '1' thenif entm3s = '1' thenif tm3s = 2 thentm3s <= B"00" 。elsetm3s <= tm3s + 1 。end if 。elsetm3s <= B"00" 。end if 。end if 。end proce

27、ss。process(rst,clk)beginif rst = '0' thentm60soc <= '0' 。elsif clk'event and clk = '1' thenif tm60s = 59 thentm60soc <= '1' 。elsetm60soc <= '0' 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thentm40soc <= '0' 。e

28、lsif clk'event and clk = '1' thenif tm40s = 39 thentm40soc <= '1' 。elsetm40soc <= '0' 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thentm3soc <= '0' 。elsif clk'event and clk = '1' thenif tm3s = 2 thentm3soc <= '

29、;1' 。elsetm3soc <= '0' 。end if 。end if 。end process。process(rst,clk)beginif rst = '0' thennsred <= '1' 。ewred <= 'O'。ewgreen <= '1'oewyellow <= 'O'。elsif clk'event and elk = '1' thencase ss iswhen sO =>nsred <= '

30、;1'onsgreen <= 'O'。nsyellow <= 'O'。ewred <= 'O'。ewgreen <= '1'o ewyellow <= 'O'。when s1 =>nsred <= 'O'。nsgreen <= 'O'。nsyellow <= '1'。ewred <= 'O'。ewgreen <= 'O'。ewyellow <= '1

31、'。when s2 =>nsred <= 'O'。nsgreen <= '1'o nsyellow <= 'O'。ewred <= '1' oewgreen <= 'O'。ewyellow <= 'O'。when s3 =>nsred <= 'O'。nsgreen <= 'O'。nsyellow <= '1'。ewred <= 'O'。ewgreen <= 'O'。ewyellow <= '1' 。when others =>end casaend if。end process。 end behav。版權申明本文部分內容，包括文字、圖片、以及設計等在網上搜集整 理。版權為潘宏亮個人所有This article includes some parts, including text, pictures, and design. Copyright is Pan Hongli