verilog并串轉(zhuǎn)換

1、實用文檔題目要求：實現(xiàn)8位的并行數(shù)據(jù)轉(zhuǎn)換為串行的數(shù)據(jù)。題目分析：并行轉(zhuǎn)串行，只要把每個輸入按從高到低的順序輸出即可。即每個時鐘脈沖輸出一個數(shù)據(jù)。但是下面的代碼有一個的問題，不能解決在8為數(shù)據(jù)串行 輸出的過程當中如果又有一個并行的輸入數(shù)據(jù)輸入，沒有做到緩沖處理。也許這個緩沖處理可以在調(diào)用此模塊時在外部實現(xiàn)吧。功能代碼：module para_to_serial_8bit(para_i n, clock,reset,ser_out);in put 7:0 para_ in;in put reset,clock;output ser_out;reg ser_out;reg 7:0 data;alwa

2、ys(posedge clock or n egedge reset) beg inif(reset) begi nser_out = 1b0;data = para_i n;endelse begi ndata = data6:0,data7;ser_out = data7;endenden dmodule測試代碼：module test_para_to_ser;reg 7:0 para_i n;reg clock,reset;wire out;para_to_serial_8bitf1(.para_ in( para_i n),.clock(clock),.reset(reset),.se

3、r_out(out);in itial$mo nitor($time,in_8bit=%b,reset= %b,ser_out= %b,data=%b,para_ in, reset,out,f1.data);in itial begi nclock = 1b0;reset = 1b0;#3 reset = 1b1;#300 $stop;endin itial實用文檔para_in = 8b1010_0100;always#5clock = clock;en dmodule測試結(jié)果:測試波形如下:作業(yè)二題目要求：實現(xiàn)8位的串行數(shù)據(jù)轉(zhuǎn)換為并行的數(shù)據(jù)題目分析：8位串行數(shù)據(jù)轉(zhuǎn)換為并行數(shù)據(jù)，需要一個模

4、為8的計數(shù)器，當計到8個時鐘脈沖時，把之前的8個數(shù)據(jù)全部輸出，然后從新接收。功能模塊代碼：模8計數(shù)器：module coun ter_mod_8(clock,reset,Q);in put clock; /posedge effectivein put reset; / n egedge effective實用文檔output 2:0 Q;reg 2:0 Q;always(posedge clock or n egedge reset) begi nif(reset)Q = 3d0;elseQ = Q + 1;enden dmodule串轉(zhuǎn)并模塊：module ser_to_par_8bit(

5、ser_ in, clk,rst,out);in put ser_ in, clk,rst;output 7:0 out;wire 7:0 out;reg 7:0 par_out;wire 2:0 count;coun ter_mod_8 f1(.clock(clk),.reset(rst),.Q(co un t);always(posedge clk or n egedge rst) beg inif(rst)par_out = 8b0000_0000;else begi npar_out = par_out6:0,ser_ in;endendassign out = (count = 7)

6、? par_out : 8b0000_0000; en dmodule測試模塊代碼：module test_ser_par;reg 7:0 data;wire data_i n;reg clock, reset;wire 7:0 out;in itial begi nclock = 1b0;實用文檔reset = 1bO;#3 reset = 1b1;data = 8b1001_1101;#300 $stop;endalways#5clock = clock; always(posedge clock)data =data6:0,data7; assig n data_ in = data7;

7、ser_to_par_8bit a(.ser_ in( data_ in ),.clk(clock),.rst(reset),.out(out);in itial%b,data= %b,data_i n= %b,out= %b,reset,data,data_i n,out);測試結(jié)果:測試波形:$mo nitor($time,reset=en dmodule實用文檔作業(yè)三題目：可變模計數(shù)器，當控制信號為1時，模值為16,當控制信號為0是模值 為32。功能模塊代碼：/ contr = 1 mod =16; contr =0 mod =32module coun t_mod_chg(clk,re

8、set,c on tr,Q);in put clk,reset,c ontr;output 4:0 Q;實用文檔reg 4:0 Q;wire 4:0 last;assign last =(contr ? 5b01111:5b11111);always(posedge clk or n egedge reset) beg inif(reset | Q = last)Q = 5b00000;elseQ = Q + 1;enden dmodule測試模塊代碼：module test_co un t_mod_chg;reg clock,reset;reg con trol;wire 4:0 out;c

9、oun t_mod_chg coun ter1(.clk(clock),.reset(reset),.c ontr(con trol),.Q(out); in itial$mon itor($time,reset= %b,c on trol= %b,out= %b,reset,c on trol,out);in itial beg inclock = 1b0;forever #5 clock = clock;endin itial begi n reset = 1b0;#5reset = 1b1; endin itial begi ncon trol = 1;#200 control = 0;enden dmodule測試結(jié)果:實用文檔仿真波形如下實用文檔f Wae:Messages deck0L_TT TLTLTTjirlrLn rLnrrkTln_reset1controlQD outooinotaciloa jckxniitookiKuiiboiio!bciii：roSDionniKObiioiMjiiDtomitaotaoiM10FT陰幗-MessagesJM1x rn jn_rTr1L r1 -ruL rJreset1Jcontrol0D-Jout1100 o.lotouii