西北工業(yè)大學(xué)部分?jǐn)?shù)電實驗VHDL程序合集

1、3位二進制數(shù)比較器 4選1數(shù)據(jù)選擇器 8421碼轉(zhuǎn)換為格雷碼 8421碼轉(zhuǎn)換為余三碼 數(shù)碼管譯碼器 帶異步復(fù)位的四位二進制減計數(shù)器 帶異步復(fù)位的8421碼十進制計數(shù)器分頻器 帶異步復(fù)位的四位環(huán)形計數(shù)器 數(shù)碼管顯示012345 數(shù)碼管滾動顯示012345數(shù)碼管滾動顯示012345，且用全滅的數(shù)碼管填充右邊，直至全滅 彩燈控制電路（1）3位二進制數(shù)比較器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY comp3 IS PORT(A:IN STD_LOGIC_VECTOR(2 DO

2、WNTO 0); B:IN STD_LOGIC_VECTOR(2 DOWNTO 0); YA,YB,YC:OUT STD_LOGIC); END comp3; ARCHITECTURE behave OF comp3 IS BEGIN PROCESS(A,B) BEGIN IF(AB)THEN YA=1;YB=0;YC=0; ELSIF(AB)THEN YA=0;YB=1;YC=0; ELSE YA=0;YB=0;YC Y=D0;YB Y=D1;YB Y=D2;YB Y=D3;YB Y=Z;YB=Z; END CASE; END PROCESS; END behave;（3）8421碼轉(zhuǎn)換為格

3、雷碼 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY trans1 IS PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END trans1; ARCHITECTURE trans_gray OF trans1 IS BEGIN B(0)=A(0)XOR A(1); B(1)=A(1)XOR A(2); B(2)=A(2)XOR A(3); B(3) B B B B B B

4、 B B B B B=ZZZZ; END CASE; END PROCESS; END trans_ex3;（5）數(shù)碼管譯碼器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sunyu_encoder IS PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); C:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); END sunyu_encoder; ARCHI

5、TECTURE encoder_arch OF sunyu_encoder IS BEGIN PROCESS(A) BEGIN C B B B B B B B B B B B=ZZZZZZZ; END CASE; END PROCESS; END encoder_arch;（1）帶異步復(fù)位的四位二進制減計數(shù)器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY count_1 IS PORT( clk,reset:IN STD_LOGIC; q:OUT STD_LOGIC_VECT

6、OR(3 DOWNTO 0); END count_1; ARCHITECTURE a OF count_1 IS SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(clk,reset) BEGIN IF reset=0 THEN q_temp =1111; ELSIF clkEVENT AND clk=1 THEN q_temp =q_temp-1; END IF; END PROCESS; q= q_temp; END a;（2）帶異步復(fù)位的8421碼十進制計數(shù)器 LIBRARY IEEE; USE IEEE.STD_LOG

7、IC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY count_BCD IS PORT( clk,reset:IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END count_BCD; ARCHITECTURE a OF count_BCD IS SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(clk,reset) BEGIN IF reset=0 THEN q_temp =0000; ELSIF clkEVENT AN

8、D clk=1 THEN IF q_temp=1001 THEN q_temp =0000; ELSE q_temp =q_temp+1; END IF; END IF; END PROCESS; q= q_temp; END a;（3）分頻器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY div_12 IS PORT( clk:IN STD_LOGIC; clear:IN STD_LOGIC; clk_out:OUT STD_LOGIC); END div_12; ARCH

9、ITECTURE a OF div_12 IS SIGNAL temp:INTEGER RANGE 0 TO 11; BEGIN p1:PROCESS(clear,clk) BEGIN IF clear=0THEN temp=0; ELSIF clkEVENT AND clk=1 THEN IF temp=11 THEN temp=0; ELSE temp=temp+1; END IF; END IF; END PROCESS p1; p2:PROCESS(temp) BEGIN IF temp6 THEN clk_out=0; ELSE clk_out=1; END IF; END PROC

10、ESS p2; END a;（4）帶異步復(fù)位的四位環(huán)形計數(shù)器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ring IS PORT( clk,reset:IN STD_LOGIC; countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ring; ARCHITECTURE behave OF ring IS SIGNAL nextcount:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(clk

11、,reset) -0001-0010-0100-1000-0001 BEGIN IF reset=0 THEN nextcount nextcount nextcount nextcount nextcount=0001; END CASE; END IF; END PROCESS; countout=nextcount; END behave;（1）數(shù)碼管顯示012345 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity nixietube1 is port(clk: in s

12、td_logic; partout:out std_logic_vector(6 downto 0); catout: out std_logic_vector(5 downto 0); end nixietube1; architecture a of nixietube1 is signal part: std_logic_vector(6 downto 0); signal cat: std_logic_vector(5 downto 0); signal tempclk: std_logic; signal count: integer range 0 to 50000; begin

13、p1:process(clk) begin if(clkevent and clk=1)then if count=50000 then count=0; tempclk= not tempclk; else count cat=011111;part cat=101111;part cat=110111;part cat=111011;part cat=111101;part cat=111110;part cat=011111;part=1111110; -0 end case; end if; end process p2; catout=cat; partout=part; end a

14、;（2） 數(shù)碼管滾動顯示012345 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shiyan12new2 isport(clk: in std_logic; partout:out std_logic_vector(6 downto 0); catout: out std_logic_vector(5 downto 0); end shiyan12new2; architecture a of shiyan12new2 is signal part: std_logic_

15、vector(6 downto 0); signal cat: std_logic_vector(5 downto 0); signal number: std_logic_vector(5 downto 0); signal tempclk: std_logic;-a clk(div 1) signal move: std_logic;-a clk(div 2) begin p1:process(clk)-div 1 (cat 0-5) variable count:integer range 0 to 50000:=0; begin if(clkevent and clk=1)then i

16、f(count=50000)then count:=0; tempclkcatcatcatcatcatcat=011111; end case; end if; end process p2; catout=cat;p3:process(clk)-div 2 (one cat and change) about 1Hz variable count:integer range 0 to 25000000:=0; begin if (clkevent and clk=1) then if (count=25000000) then count:=0; movenumbernumbernumber

17、numbernumbernumbernumbernumbernumbernumbernumbernumberpartpartpartpartpartpartpart=1111110; end case; end process p5; partout=part; end a;（3）數(shù)碼管滾動顯示012345，且用全滅的數(shù)碼管填充右邊，直至全滅 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity shiyan12new3 is port(clk: in std_logic; part

18、out:out std_logic_vector(6 downto 0); catout: out std_logic_vector(5 downto 0); end shiyan12new3; architecture a of shiyan12new3 is signal part: std_logic_vector(6 downto 0); signal cat: std_logic_vector(5 downto 0); signal number: std_logic_vector(5 downto 0); signal tempclk: std_logic;-a clk(div 1

19、) signal move: std_logic;-a clk(div 2) begin p1:process(clk)-div 1 (cat 0-5) variable count:integer range 0 to 50000 :=0; begin if(clkevent and clk=1)then if(count=50000)then count:=0; tempclktemp:=101111; when101111=temp:=110111; when110111=temp:=111011; when111011=temp:=111101; when111101=temp:=111110; when others =temp:=011111; end case; end if; case count is when 0 =catcatcatcatcatcatcatcatcatcatcatcat=(temp or 100000)