EDA技術(shù)復(fù)習(xí)大綱1

1、EDA技術(shù)復(fù)習(xí)大綱1. 題型：填空，判斷改錯，讀程題，編程題 (3 道) 、問答題，共 100 分。2. EDA FPGA及 quart us 軟件基礎(chǔ)知識：如quart us相關(guān)文件的后綴名；quartus軟 件使用常用命令，如管腳分配，編譯，編程下載等 (2 的開發(fā)流程 )3. 復(fù)習(xí)計數(shù)器、分頻電路的設(shè)計、 7 段譯碼器設(shè)計、數(shù)字時鐘、搶答器，數(shù)字秒表 的 設(shè)計。 (全加器 )4. 編程題實(shí)體部分已經(jīng)寫好。全加器的VHDL程序設(shè)計：全加器的邏輯表達(dá)式為：S = a?b? ciCo = (a ? b) + (a ? ci) + (b*ci)Quartus II中創(chuàng)建一個EDA工程的流程。計數(shù)

2、和分頻綜合題ENTITY DVF ISPORT ( CLK : IN STD_L0GIC:D : IN STD_LOGIC_VECTOR(7 D0WNT0 0);FOUT : OUT STD_LOGIC );END;ARCHITECTURE one OF DVF ISSIGNAL FULL : STD_LOGIC:BEGINP_REG: PROCESS(CLK)VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLK' EVENT AND CLK = ' 1' THENIF CNT8 = "1111111

3、1" THENCNT8 := D;FULL <= ' 1'ELSE CNT8 := CNT8 + 1;FULL <= ' O'END IF; END IF;END PROCESS P_REG ;P_DIV: PROCESS(FULL)VARIABLE CNT2 : STD_LOGIC;BEGINIF FULL' EVENT AND FULL = ' 1' THENCNT2 := NOT CNT2;IF CNT2 = ' 1' THEN FOUT <= ' 1' ; ELSE FO

4、UT <= ' O'END IF; END IF;END PROCESS P_DIV ;END;(1) 上述VHDL苗述所實(shí)現(xiàn)的功能是一數(shù)控分頻器，D端口輸入不同的數(shù)據(jù)，可以得到不同的分頻輸出。(2) 已知CLK時鐘頻率是10MHZ要使輸出信號的頻率FOUT為50KHZ該如何實(shí)(256-D)現(xiàn)？根據(jù)分頻原理：Q；HZX- = 50KH乙所以輸入端口 D端口應(yīng)該輸入數(shù)據(jù)為156,標(biāo)準(zhǔn)邏輯矢量形式為：“ 10011100',即D端口應(yīng)該輸入數(shù)據(jù)“ 10011100',艮阿實(shí)現(xiàn)F0UT為50KHZ數(shù)字秒表設(shè)計-用VHDL語句設(shè)計一個數(shù)字秒表，該秒表計時從0? 5

5、9秒(提示：60進(jìn)制計數(shù)器)。ENTITY FEN60 ISPORT (CLK : IN STD_LOGIC;時鐘信號為 1HZRSTINSTD_LOGIC;Q0UT1OUTSTD_L0GIC_VECT0R(3 DOWNTO 秒低位Q0UT2OUTSTD_L0GIC_VECT0R(3 DOWNTO 0一秒高位CARROUSTD_L0GlO ; 一進(jìn)位輸出，每計滿 60秒時為1END FEN60;architecture behave of fen60 is sig nal teml:std_logic_vector(3 dow nto 0); sig nal tem2:std_logic_ve

6、ctor(3 downto 0); begi nprocess (elk,rst)begi nif (rst=，O') thenteml<=，z0000/z; tem2二 0000 ;elsif clkeve nt and clk1' the nif teml 二 1001 thenteml 二 0000 ;if tem2= 0101 then tem2二 0000 ； carryv = T ;elsetem2<=tem2+l; carryv =，O'end if;elseteml<=teml+l;end if;end if;qoutl<=tem

7、l; qout2<=tem2;end process; end behave;計數(shù)譯碼顯示電路設(shè)計一一如圖1所示是一個計數(shù)譯碼顯示電路，圖中的 CNT10是一個十進(jìn)制加法計數(shù)器，DECL7S是 7段顯示譯碼器。用VHDL語句將該電路描述出 來。clkO rstOinput-VCCenO I _ 、 input1 _>CNT10DECL7SCLK CQC 3RCT COUENI > led6.O?UTPUT ICoutoENDEROCESS圖1計數(shù)譯碼顯示電路原理圖10進(jìn)制計數(shù)器ENTITY CNT10 ISPORT (CLK, RST, EN : IN STD_LOGIC;C

8、Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT10;ARCHITECTURE behav OF CNT10 ISBEGINPROCESS(CLK, RST, EN)VARIABLE CQI:STD_LOGIC_VECTOR(3DOWNTO 0);BEGINIF RST = '1' THEN CQI := (OTHERS=>'0')；ELSIF CLK' EVENT AND CLK=' 1' THENIF EN = ' 1' THE

9、NIF CQI < 9 THEN CQI := CQI +1；ELSE CQI := (OTHERS =>' 0');END IF;END IF;END IF;IF CQI = 9 THEN COUT <= ' 1'ELSE COUT二'O'END IF;CQ <= CQI;END PROCESS:END behav7段數(shù)碼管顯示ENTITY DECL7S ISPORT ( A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);LED7S:OUT STD_LOGIC_VECTOR(6 DOWNTO0);E

10、ND ;ARCHITECTURE one OF DECL7S ISBEGINROCESS( ABegiNWHEN "0000=>LED7<="0111111"WHEN "0001=>SED7<="0000110"WHEN "0010=>SED7S<="1011011"WHEN "0011=>LED7S<="1001111"WHEN "0100=>LED7Q<="1100110"WHEN

11、"0101=>SED7S<="1101101"WHEN "0110=>LED7S<="1111101"WHEN "0111=>LED7SED7S<="0000111"WHEN "1000=><="1111111"WHEN "1001=>LED7<="1101111"SEND CASE ;以上兩個程序有效組合實(shí)現(xiàn)計數(shù)并在 7 段數(shù)碼管上顯示，即計數(shù)譯碼顯示電路ENTITY CNTLED I

12、SPORT (CLKO, RSTO, ENO: IN STD_LOGIC;LED: OUT STD_LOGIC_VECTOR (6 DOWNTO 0):COUTO: OUT STD_LOGIC);END CNTLED:ARCHITECTURE behav OF CNTLED ISCOMPONENT cntlOPORT (CLK, RST, EN: IN STD_LOGIC:CQ: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);COUT: OUT STD_LOGIC);END COMPONENT:COMPONENT DECL7SPORT (A: IN STD_LOGIC_V

13、ECTOR (3 DOWNTO 0);LED7S: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);END COMPONENT:SIGNAL temp: STD_LOGIC_VECTOR (3 DOWNTO 0):BEGINul: cntlO PORT MAP (CLKO, RSTO, ENO, TEMP, COUTO): u2: DECL7S PORT MAP (TEMP, LED);END behav;分別用結(jié)構(gòu)體的 3 種描述法設(shè)計一個 4 位計數(shù)器。答：用行為描述方法設(shè)計一個 4 位計數(shù)器如下，其它描述方法，讀者可自行設(shè)計LIBRARY IEEE;USE IEEE.

14、STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY countAISPORT (clk,clr,en:IN STD_LOGIC; Qa,qb,qc,qd:OUT STD_LOGIC);END countA;ARCHITECTURE example OF countA ISSIGNAL count_4:STD_LOGIC_vector (3 DOWNTO 0);BEGINQa <= count_4(0);Qb <= count_4(l);Qc <= count_4(2);Qd <= count_4(3);PR

15、OCESS (clk,clr)BEGINIF (clr = T ) THENCount_4 <= ” 000；0 ”ELSIF (clk'EVENTAND elk = T ) THENIF (en = T ) THENIF (count_4 =” 1)1T1H1E”Ncount_4 v= ” 00；00 ”ELSEcount_4 <= count_4+ '1'END IF;END IF;END IF;END PROCESS;END example;設(shè)計一個六十進(jìn)制計數(shù)器。答: 60進(jìn)制計數(shù)器的 VHDL 參考程序設(shè)計如下： Library ieee;use

16、ieee. std_logic_1164. all;use ieee. std_logic_unsigned. all;use ieee. std_logic_arith. all;Entity counter60 isport (cp:in std_logic;bin:out std_logic_vector(6 downto 0); s:in std_logic;clr:in std_logic;ec:in std_logic;cy60:out std_logic);End counter60;Architecture b of counter60 issignal q:std_logic_vector(6 downto 0);signal rst, dly:std_logic;beginprocess(rst, cp)beginif rst='1' then elsif cp&