AD9854 驅(qū)動程序設(shè)計

1、/=/ AD9854 驅(qū)動程序設(shè)計/硬件連接: P0 Data; / P2 Adr; / RESET P37; / UDCLK P36; / WR P3.5; / RD p3.4; / FDATA P33; / OSK P32; / VDD-邏輯電源(3.3V)/ VSS-GND(0V) /AD9854.c/writer:谷雨 2008年8月22日24日于EDA實驗室/說明：本程序基于硬件的外接晶振為20MHZ/=#include <STC89C51RC.h> /STC單片機頭文件#include <intrins.h> #define uint unsigned in

2、t#define uchar unsigned char#define ulong unsigned longuchar FreqWord6; /6個字節(jié)頻率控制字/*以下為系統(tǒng)時鐘以及其相關(guān)變量設(shè)置*/* 此處根據(jù)自己的需要設(shè)置系統(tǒng)時鐘以及與其相關(guān)的因子，一次需且只需開啟一個 CLK_Set為時鐘倍頻設(shè)置，可設(shè)置420倍倍頻，但最大不能超過300MHZ Freq_mult_ulong和Freq_mult_doulle均為2的48次方除以系統(tǒng)時鐘，一個為長整形，一個為雙精度型*/*#define CLK_Set 4const ulong Freq_mult_ulong = 3518437;co

3、nst double Freq_mult_doulle = 3518437.2088832;*/*#define CLK_Set 5const ulong Freq_mult_ulong = 2814750;const double Freq_mult_doulle = 2814749.76710656;*/#define CLK_Set 6const ulong Freq_mult_ulong = 2345625;const double Freq_mult_doulle = 2345624.80592213;/*#define CLK_Set 7const ulong Freq_mult_

4、ulong = 2010536;const double Freq_mult_doulle = 2010535.54793326;*/*#define CLK_Set 8const ulong Freq_mult_ulong = 1759219;const double Freq_mult_doulle = 1759218.6044416;*/*#define CLK_Set 9const ulong Freq_mult_ulong = 1563750;const double Freq_mult_doulle = 1563749.87061476;*/*#define CLK_Set 10c

5、onst ulong Freq_mult_ulong = 1407375;const double Freq_mult_doulle = 1407374.88355328;*/*#define CLK_Set 11const ulong Freq_mult_ulong = 1279432;const double Freq_mult_doulle = 1279431.712321164;*/*#define CLK_Set 12const ulong Freq_mult_ulong = 1172812;const double Freq_mult_doulle = 1172812.402961

6、067;*/*#define CLK_Set 13const ulong Freq_mult_ulong = 1082596;const double Freq_mult_doulle = 1082596.064271754;*/*#define CLK_Set 14const ulong Freq_mult_ulong = 1005268;const double Freq_mult_doulle = 1005267.773966629;*/*#define CLK_Set 15const ulong Freq_mult_ulong = 938250;const double Freq_mu

7、lt_doulle = 938249.9223688533;*/*修改硬件時要修改的部分*#define AD9854_DataBus P0#define AD9854_AdrBus P2sbit AD9854_RST = P37; /AD9854復(fù)位端口sbit AD9854_UDCLK = P36; /AD9854更新時鐘sbit AD9854_WR = P35; /AD9854寫使能，低有效sbit AD9854_RD = P34; /AD9854讀使能，低有效sbit AD9854_FDATA = P33; /AD9854 FSK,PSK控制sbit AD9854_OSK = P32;

8、 /AD9854 OSK控制端/*以下部分為函數(shù)定義*static void AD9854_WR_Byte(uchar addr,uchar dat); extern void AD9854_Init(void); static void Freq_convert(long Freq); extern void AD9854_SetSine(ulong Freq,uint Shape); static void Freq_double_convert(double Freq); extern void AD9854_SetSine_double(double Freq,uint Shape);

9、extern void AD9854_InitFSK(void);extern void AD9854_SetFSK(ulong Freq1,ulong Freq2); extern void AD9854_InitBPSK(void); extern void AD9854_SetBPSK(uint Phase1,uint Phase2);extern void AD9854_InitOSK(void); extern void AD9854_SetOSK(uchar RateShape); extern void AD9854_InitAM(void); extern void AD985

10、4_SetAM(uint Shape);extern void AD9854_InitRFSK(void); extern void AD9854_SetRFSK(ulong Freq_Low,ulong Freq_High,ulong Freq_Up_Down,ulong FreRate);static void delay (uint us);/=/函數(shù)名稱:void AD9854_WR_Byte(uchar addr,uchar dat)/函數(shù)功能:AD9854并行口寫入數(shù)據(jù)/入口參數(shù):addr 6位地址/ dat 寫入的數(shù)據(jù)/出口參數(shù):無/=void AD9854_WR_Byte(uc

11、har addr,uchar dat)AD9854_AdrBus = (addr&0x3f) | (P2&0xc0);AD9854_DataBus = dat;AD9854_WR = 0;AD9854_WR = 1;/=/函數(shù)名稱:void AD9854_Init(void)/函數(shù)功能:AD9854初始化/入口參數(shù):無/出口參數(shù):無/=void AD9854_Init(void)AD9854_WR=1;/將讀、寫控制端口設(shè)為無效 AD9854_RD=1; AD9854_UDCLK=0; AD9854_RST=1; /復(fù)位AD9854 AD9854_RST=0;AD9854_WR

12、_Byte(0x1d,0x10); /關(guān)閉比較器AD9854_WR_Byte(0x1e,CLK_Set); /設(shè)置系統(tǒng)時鐘倍頻 AD9854_WR_Byte(0x1f,0x00); /設(shè)置系統(tǒng)為模式0，由外部更新AD9854_WR_Byte(0x20,0x60); /設(shè)置為可調(diào)節(jié)幅度，取消插值補償AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void Freq_convert(long Freq)/函數(shù)功能:正弦信號頻率數(shù)據(jù)轉(zhuǎn)換/入口參數(shù):Freq 需要轉(zhuǎn)換的頻率，取值從0SYSCLK/2/出口參數(shù):無 但是影響全局變量FreqWord6

13、的值/說明： 該算法位多字節(jié)相乘算法，有公式FTW = (Desired Output Frequency × 2N)/SYSCLK/ 得到該算法，其中N=48，Desired Output Frequency 為所需要的頻率，即Freq，SYSCLK/ 為可編程的系統(tǒng)時鐘，F(xiàn)TW為48Bit的頻率控制字，即FreqWord6/=void Freq_convert(long Freq) ulong FreqBuf; ulong Temp=Freq_mult_ulong; uchar Array_Freq4; /將輸入頻率因子分為四個字節(jié)Array_Freq0=(uchar)Freq;

14、Array_Freq1=(uchar)(Freq>>8);Array_Freq2=(uchar)(Freq>>16);Array_Freq3=(uchar)(Freq>>24);FreqBuf=Temp*Array_Freq0; FreqWord0=FreqBuf; FreqBuf>>=8; FreqBuf+=(Temp*Array_Freq1); FreqWord1=FreqBuf; FreqBuf>>=8; FreqBuf+=(Temp*Array_Freq2); FreqWord2=FreqBuf; FreqBuf>>

15、;=8;FreqBuf+=(Temp*Array_Freq3); FreqWord3=FreqBuf; FreqBuf>>=8; FreqWord4=FreqBuf; FreqWord5=FreqBuf>>8; /=/函數(shù)名稱:void AD9854_SetSine(ulong Freq,uint Shape)/函數(shù)功能:AD9854正弦波產(chǎn)生程序/入口參數(shù):Freq 頻率設(shè)置，取值范圍為0(1/2)*SYSCLK/ Shape 幅度設(shè)置. 為12 Bit,取值范圍為(04095) ,取值越大,幅度越大 /出口參數(shù):無/=void AD9854_SetSine(ulon

16、g Freq,uint Shape)uchar count;uchar Adress;Adress = 0x04; /選擇頻率控制字地址的初值Freq_convert(Freq); /頻率轉(zhuǎn)換for(count=6;count>0;) /寫入6字節(jié)的頻率控制字 AD9854_WR_Byte(Adress+,FreqWord-count); AD9854_WR_Byte(0x21,Shape>>8); /設(shè)置I通道幅度AD9854_WR_Byte(0x22,(uchar)(Shape&0xff);AD9854_WR_Byte(0x23,Shape>>8);

17、/設(shè)置Q通道幅度AD9854_WR_Byte(0x24,(uchar)(Shape&0xff);AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void Freq_doublt_convert(double Freq)/函數(shù)功能:正弦信號頻率數(shù)據(jù)轉(zhuǎn)換/入口參數(shù):Freq 需要轉(zhuǎn)換的頻率，取值從0SYSCLK/2/出口參數(shù):無 但是影響全局變量FreqWord6的值/說明： 有公式FTW = (Desired Output Frequency × 2N)/SYSCLK得到該函數(shù)，/ 其中N=48，Desired Output

18、 Frequency 為所需要的頻率，即Freq，SYSCLK/ 為可編程的系統(tǒng)時鐘，F(xiàn)TW為48Bit的頻率控制字，即FreqWord6/注意： 該函數(shù)與上面函數(shù)的區(qū)別為該函數(shù)的入口參數(shù)為double，可使信號的頻率更精確/ 谷雨建議在100HZ以下用本函數(shù)，在高于100HZ的情況下用函數(shù)void Freq_convert(long Freq)/=void Freq_double_convert(double Freq) ulong Low32;uint High16; double Temp=Freq_mult_doulle; /23ca99為2的48次方除以120MFreq*=(doub

19、le)(Temp);/1 0000 0000 0000 0000 0000 0000 0000 0000 = 4294967295High16 = (int)(Freq/4294967295); /232 = 4294967295Freq -= (double)High16*4294967295;Low32 = (ulong)Freq; FreqWord0=Low32; FreqWord1=Low32>>8; FreqWord2=Low32>>16; FreqWord3=Low32>>24; FreqWord4=High16; FreqWord5=High1

20、6>>8; /=/函數(shù)名稱:void AD9854_SetSine_double(double Freq,uint Shape)/函數(shù)功能:AD9854正弦波產(chǎn)生程序/入口參數(shù):Freq 頻率設(shè)置，取值范圍為01/2*SYSCLK/ Shape 幅度設(shè)置. 為12 Bit,取值范圍為(04095) /出口參數(shù):無/=void AD9854_SetSine_double(double Freq,uint Shape)uchar count=0;uchar Adress;Adress=0x04; /選擇頻率控制字1地址的初值Freq_double_convert(Freq); /頻率轉(zhuǎn)

21、換 for(count=6;count>0;) /寫入6字節(jié)的頻率控制字 AD9854_WR_Byte(Adress+,FreqWord-count); AD9854_WR_Byte(0x21,Shape>>8); /設(shè)置I通道幅度AD9854_WR_Byte(0x22,(uchar)(Shape&0xff);AD9854_WR_Byte(0x23,Shape>>8); /設(shè)置Q通道幅度AD9854_WR_Byte(0x24,(uchar)(Shape&0xff);AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0

22、;/=/函數(shù)名稱:void AD9854_InitFSK(void)/函數(shù)功能:AD9854的FSK初始化/入口參數(shù):無/出口參數(shù):無/=void AD9854_InitFSK(void)AD9854_WR=1; /將讀、寫控制端口設(shè)為無效 AD9854_RD=1; AD9854_UDCLK=0; AD9854_RST=1; /復(fù)位AD9854 AD9854_RST=0;AD9854_WR_Byte(0x1d,0x10); /關(guān)閉比較器AD9854_WR_Byte(0x1e,CLK_Set); /設(shè)置系統(tǒng)時鐘倍頻AD9854_WR_Byte(0x1f,0x02); /設(shè)置系統(tǒng)為模式1，由外部更

23、新AD9854_WR_Byte(0x20,0x60); /設(shè)置為可調(diào)節(jié)幅度，取消插值補償AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void AD9854_SetFSK(ulong Freq1,ulong Freq2)/函數(shù)功能:AD9854的FSK設(shè)置/入口參數(shù):Freq1 FSK頻率1 / Freq2 FSK頻率2/出口參數(shù):無/=void AD9854_SetFSK(ulong Freq1,ulong Freq2) uchar count=6;uchar Adress1,Adress2;const uint Shape=4000;

24、 /幅度設(shè)置. 為12 Bit,取值范圍為(04095)Adress1=0x04; /選擇頻率控制字1地址的初值A(chǔ)dress2=0x0a; /選擇頻率控制字2地址的初值Freq_convert(Freq1); /頻率轉(zhuǎn)換1for(count=6;count>0;) /寫入6字節(jié)的頻率控制字 AD9854_WR_Byte(Adress1+,FreqWord-count); Freq_convert(Freq2); /頻率轉(zhuǎn)換2for(count=6;count>0;) /寫入6字節(jié)的頻率控制字 AD9854_WR_Byte(Adress2+,FreqWord-count); AD98

25、54_WR_Byte(0x21,Shape>>8); /設(shè)置I通道幅度AD9854_WR_Byte(0x22,(uchar)(Shape&0xff);AD9854_WR_Byte(0x23,Shape>>8); /設(shè)置Q通道幅度AD9854_WR_Byte(0x24,(uchar)(Shape&0xff);AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void AD9854_InitBPSK(void)/函數(shù)功能:AD9854的BPSK初始化/入口參數(shù):無/出口參數(shù):無/=void AD9854_I

26、nitBPSK(void)AD9854_WR=1; /將讀、寫控制端口設(shè)為無效 AD9854_RD=1; AD9854_UDCLK=0; AD9854_RST=1; /復(fù)位AD9854 AD9854_RST=0;AD9854_WR_Byte(0x1d,0x10); /關(guān)閉比較器AD9854_WR_Byte(0x1e,CLK_Set); /設(shè)置系統(tǒng)時鐘倍頻AD9854_WR_Byte(0x1f,0x08); /設(shè)置系統(tǒng)為模式4，由外部更新AD9854_WR_Byte(0x20,0x60); /設(shè)置為可調(diào)節(jié)幅度，取消插值補償AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UD

27、CLK=0;/=/函數(shù)名稱:void AD9854_SetBPSK(uint Phase1,uint Phase2)/函數(shù)功能:AD9854的BPSK設(shè)置/入口參數(shù):Phase1 調(diào)制相位1/ Phase2調(diào)制相位2/出口參數(shù):無/說明： 相位為14Bit，取值從016383，谷雨建議在用本函數(shù)的時候?qū)hase1設(shè)置為0，/ 將Phase1設(shè)置為8192，180°相位/=void AD9854_SetBPSK(uint Phase1,uint Phase2)uchar count;const ulong Freq=60000; const uint Shape=4000;uchar

28、 Adress;Adress=0x04; /選擇頻率控制字1地址的初值A(chǔ)D9854_WR_Byte(0x00,Phase1>>8); /設(shè)置相位1AD9854_WR_Byte(0x01,(uchar)(Phase1&0xff);AD9854_WR_Byte(0x02,Phase2>>8); /設(shè)置相位2AD9854_WR_Byte(0x03,(uchar)(Phase2&0xff);Freq_convert(Freq); /頻率轉(zhuǎn)換for(count=6;count>0;) /寫入6字節(jié)的頻率控制字 AD9854_WR_Byte(Adress+,F

29、reqWord-count); AD9854_WR_Byte(0x21,Shape>>8); /設(shè)置I通道幅度AD9854_WR_Byte(0x22,(uchar)(Shape&0xff);AD9854_WR_Byte(0x23,Shape>>8); /設(shè)置Q通道幅度AD9854_WR_Byte(0x24,(uchar)(Shape&0xff);AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void AD9854_InitOSK(void)/函數(shù)功能:AD9854的OSK初始化/入口參數(shù):無/出口參

30、數(shù):無/=void AD9854_InitOSK(void)AD9854_WR=1; /將讀、寫控制端口設(shè)為無效AD9854_RD=1;AD9854_UDCLK=0;AD9854_RST=1; /復(fù)位AD9854AD9854_RST=0; AD9854_WR_Byte(0x1d,0x10); /關(guān)閉比較器AD9854_WR_Byte(0x1e,CLK_Set); /設(shè)置系統(tǒng)時鐘倍頻AD9854_WR_Byte(0x1f,0x00); /設(shè)置系統(tǒng)為模式0，由外部更新AD9854_WR_Byte(0x20,0x70); /設(shè)置為可調(diào)節(jié)幅度，取消插值補償,通斷整形內(nèi)部控制AD9854_UDCLK=1

31、; /更新AD9854輸出AD9854_UDCLK=0;/=/函數(shù)名稱:void AD9854_SetOSK(uchar RateShape)/函數(shù)功能:AD9854的OSK設(shè)置/入口參數(shù): RateShape OSK斜率,取值為4255，小于4則無效/出口參數(shù):無/=void AD9854_SetOSK(uchar RateShape)uchar count;const ulong Freq=60000; /設(shè)置載頻 const uint Shape=4000;/幅度設(shè)置. 為12 Bit,取值范圍為(04095)uchar Adress;Adress=0x04; /選擇頻率控制字地址的初值

32、Freq_convert(Freq); /頻率轉(zhuǎn)換for(count=6;count>0;) /寫入6字節(jié)的頻率控制字 AD9854_WR_Byte(Adress+,FreqWord-count); AD9854_WR_Byte(0x21,Shape>>8); /設(shè)置I通道幅度AD9854_WR_Byte(0x22,(uchar)(Shape&0xff);AD9854_WR_Byte(0x23,Shape>>8); /設(shè)置Q通道幅度AD9854_WR_Byte(0x24,(uchar)(Shape&0xff); AD9854_WR_Byte(0x2

33、5,RateShape); /設(shè)置OSK斜率AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void AD9854_InitAM(void)/函數(shù)功能:AD9854的AM初始化/入口參數(shù):無/出口參數(shù):無/=void AD9854_InitAM(void)uchar count;const ulong Freq=60000; /設(shè)置載頻uchar Adress;Adress=0x04; /選擇頻率控制字地址的初值 AD9854_WR=1; /將讀、寫控制端口設(shè)為無效 AD9854_RD=1; AD9854_UDCLK=0; AD9854_R

34、ST=1; /復(fù)位AD9854 AD9854_RST=0;AD9854_WR_Byte(0x1d,0x10); /關(guān)閉比較器AD9854_WR_Byte(0x1e,CLK_Set); /設(shè)置系統(tǒng)時鐘倍頻AD9854_WR_Byte(0x1f,0x00); /設(shè)置系統(tǒng)為模式0，由外部更新AD9854_WR_Byte(0x20,0x60); /設(shè)置為可調(diào)節(jié)幅度，取消插值補償Freq_convert(Freq); /頻率轉(zhuǎn)換for(count=6;count>0;) /寫入6字節(jié)的頻率控制字 AD9854_WR_Byte(Adress+,FreqWord-count); AD9854_UDCL

35、K=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void AD9854_SetAM(uchar Shape)/函數(shù)功能:AD9854的AM設(shè)置/入口參數(shù):Shape 12Bit幅度,取值從04095 /出口參數(shù):無/=void AD9854_SetAM(uint Shape)AD9854_WR_Byte(0x21,Shape>>8); /設(shè)置I通道幅度AD9854_WR_Byte(0x22,(uchar)(Shape&0xff);AD9854_WR_Byte(0x23,Shape>>8); /設(shè)置Q通道幅度AD9854_WR_By

36、te(0x24,(uchar)(Shape&0xff);AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void AD9854_InitRFSK(void)/函數(shù)功能:AD9854的RFSK初始化/入口參數(shù):無/出口參數(shù):無/=void AD9854_InitRFSK(void)AD9854_WR=1; /將讀、寫控制端口設(shè)為無效 AD9854_RD=1; AD9854_UDCLK=0; AD9854_RST=1; /復(fù)位AD9854 AD9854_RST=0;AD9854_WR_Byte(0x1d,0x10); /關(guān)閉比較器AD9

37、854_WR_Byte(0x1e,CLK_Set); /設(shè)置系統(tǒng)時鐘倍頻AD9854_WR_Byte(0x1f,0x24); /設(shè)置系統(tǒng)為模式2，由外部更新,使能三角波掃頻功能AD9854_WR_Byte(0x20,0x60); /設(shè)置為可調(diào)節(jié)幅度，取消插值補償AD9854_UDCLK=1; /更新AD9854輸出 AD9854_UDCLK=0;/=/函數(shù)名稱:void AD9854_SetRFSK(void)/函數(shù)功能:AD9854的RFSK設(shè)置/入口參數(shù):Freq_Low RFSK低頻率 48Bit/ Freq_High RFSK高頻率 48Bit/ Freq_Up_Down 步進頻率 4

38、8Bit/ FreRate 斜率時鐘控制 20Bit/出口參數(shù):無/注： 每兩個脈沖之間的時間周期用下式表示（FreRate +1）*（System Clock ），一個脈沖,/ 頻率 上升或者下降 一個步進頻率/=void AD9854_SetRFSK(ulong Freq_Low,ulong Freq_High,ulong Freq_Up_Down,ulong FreRate)uchar count=6;uchar Adress1,Adress2,Adress3; const uint Shape=4000; /幅度設(shè)置. 為12 Bit,取值范圍為(04095)Adress1=0x04; /選擇頻率控制字地址的初值 Adress2=0x0a;