集成電路綜合課程設(shè)計(jì)

1、課程設(shè)計(jì)開(kāi)課學(xué)期： 2013-2014學(xué)年第一學(xué)期 課程名稱： 集成電路綜合課程設(shè)計(jì) 學(xué) 院： 專(zhuān) 業(yè)： 班 級(jí)： 學(xué) 號(hào)： 姓 名： 任課教師： 2013 年 9 月 11 日 一、課程設(shè)計(jì)目的3二、設(shè)計(jì)要求33三、設(shè)計(jì)基本原理3四、設(shè)計(jì)設(shè)計(jì)分析4五，設(shè)計(jì)實(shí)現(xiàn)過(guò)程5A.電路設(shè)計(jì)5B.綜合過(guò)程5C.結(jié)果8五.總結(jié)及感想9附件：23設(shè)計(jì)目的利用verilogHDL設(shè)計(jì)數(shù)字電路異步FIFO,通過(guò)對(duì)verilogHDL的學(xué)習(xí)，掌握一些基本的知識(shí)，本次課程設(shè)計(jì)的安排旨在提升學(xué)生的動(dòng)手能力，加強(qiáng)大家對(duì)專(zhuān)業(yè)理論知識(shí)的理解和實(shí)際運(yùn)用，加強(qiáng)大家的自學(xué)能力，為大家做畢業(yè)設(shè)計(jì)做很好的鋪墊。設(shè)計(jì)要求遵循RTL設(shè)計(jì)規(guī)

2、則，利用VerilogHDL 設(shè)計(jì)數(shù)字電路異步FIFO.異步FIFO具有讀寫(xiě)兩個(gè)時(shí)鐘，讀時(shí)鐘100MHz，寫(xiě)時(shí)鐘50MHz。RTL為可綜合設(shè)計(jì)，需要考慮不同時(shí)鐘領(lǐng)域的同步設(shè)計(jì)，具有空滿標(biāo)志產(chǎn)生邏輯，并且根據(jù)空滿標(biāo)志進(jìn)行讀寫(xiě)數(shù)據(jù)及讀寫(xiě)使能等邏輯控制。根據(jù)RTL設(shè)計(jì)，編寫(xiě)驗(yàn)證環(huán)境，即testbench，在testbench中測(cè)試異步FIFO的讀寫(xiě)功能是否正確。異步FIFO寫(xiě)數(shù)據(jù)由testbench產(chǎn)生。編寫(xiě)一定的測(cè)試向量，來(lái)測(cè)試覆蓋所設(shè)計(jì)的異步FIFO各項(xiàng)功能及指標(biāo)。將異步FIFO RTL在DC環(huán)境中進(jìn)行綜合，編寫(xiě)約束文件，給出最終的綜合結(jié)果，包括面積報(bào)告，網(wǎng)表及時(shí)序報(bào)告。約束

3、文件中，讀寫(xiě)時(shí)鐘要求見(jiàn)上，輸入延遲為寫(xiě)時(shí)鐘周期的一半，輸出延遲為讀時(shí)鐘周期的1/3,其他約束要求根據(jù)RTL設(shè)計(jì)自己確定。設(shè)計(jì)基本原理從硬件的觀點(diǎn)來(lái)看，就是一塊數(shù)據(jù)內(nèi)存。它有兩個(gè)端口，一個(gè)用來(lái)寫(xiě)數(shù)據(jù)，就是將數(shù)據(jù)存入FIFO；另一個(gè)用來(lái)讀數(shù)據(jù)，也就是將數(shù)據(jù)從FIFO當(dāng)中取出。與FIFO操作相關(guān)的有兩個(gè)指針，寫(xiě)指針指向要寫(xiě)的內(nèi)存部分，讀指針指向要讀的內(nèi)存部分。FIFO控制器通過(guò)外部的讀寫(xiě)信號(hào)控制這兩個(gè)指針移動(dòng)，并由此產(chǎn)生FIFO空信號(hào)或滿信號(hào)。對(duì)于異步FIFO而言，數(shù)據(jù)是由某一個(gè)時(shí)鐘域的控制信號(hào)寫(xiě)入FIFO，而由另一個(gè)時(shí)鐘域的控制信號(hào)將數(shù)據(jù)讀出FIFO。也就是說(shuō)，讀寫(xiě)指針的變化動(dòng)作是由不同的時(shí)鐘產(chǎn)生

4、的。因此，對(duì)FIFO空或滿的判斷是跨時(shí)鐘域的。如何根據(jù)異步的指針信號(hào)對(duì)FIFO的滿狀態(tài)或空狀態(tài)進(jìn)行正確的判斷。設(shè)計(jì)分析在數(shù)字集成電路中，觸發(fā)器要滿足setup/hold的時(shí)間要求。當(dāng)一個(gè)信號(hào)被寄存器鎖存時(shí)，如果信號(hào)和時(shí)鐘之間不滿足這個(gè)要求，Q端的值是不確定的，并且 在未知的時(shí)刻會(huì)固定到高電平或低電平。這個(gè)過(guò)程稱為亞穩(wěn)態(tài)（Metastability）。圖2所示為異步時(shí)鐘和亞穩(wěn)態(tài)，圖中clka和clkb為異步時(shí) 鐘。對(duì)寫(xiě)地址/讀地址采用格雷碼。由實(shí)踐可知，同步多個(gè)異步輸入信號(hào)出現(xiàn)亞穩(wěn)態(tài)的概率遠(yuǎn)遠(yuǎn)大于同步一個(gè)異步信號(hào)的概率。對(duì)多個(gè)觸發(fā)器的輸出所組成的寫(xiě)地址/讀地址可以采用格雷碼。由于格雷碼每次只變化

5、一位，采用格雷碼可以有效地減少亞穩(wěn)態(tài)的產(chǎn)生。  2.2 空/滿標(biāo)志的產(chǎn)生空/滿標(biāo)志的產(chǎn)生FIFO的核心部分。如何正確設(shè)計(jì)此部分的邏輯，直接影響到FIFO的性能。空/ 滿標(biāo)志產(chǎn)生的原則是：寫(xiě)滿不溢出，讀空不多讀。即無(wú)論在什么進(jìn)修，都不應(yīng)出現(xiàn)讀寫(xiě)地址同時(shí)對(duì)一個(gè)存儲(chǔ)器地址操作的情況。在讀寫(xiě)地址相等或相差一個(gè)或多個(gè)地 址的時(shí)候，滿標(biāo)志應(yīng)該有效，表示此時(shí)FIFO已滿，外部電路應(yīng)對(duì)FIFO發(fā)數(shù)據(jù)。在滿信號(hào)有效時(shí)寫(xiě)數(shù)據(jù)，應(yīng)根據(jù)設(shè)計(jì)的要求，或保持、或拋棄重發(fā)。同理，空 標(biāo)志的產(chǎn)生也是如此，即：空標(biāo)志<=(|寫(xiě)地址-讀地址|<=預(yù)定值)AND（寫(xiě)地址超前讀地址）滿標(biāo)志<=（|寫(xiě)地址-

6、讀地址|<=預(yù)定值）AND(讀地址超前寫(xiě)地址)設(shè)計(jì)實(shí)現(xiàn)過(guò)程五、設(shè)計(jì)實(shí)現(xiàn)過(guò)程A、電路實(shí)現(xiàn)過(guò)程 附圖 1 由異步FIFO內(nèi)部模塊圖和接口信號(hào)（附圖1）可以知道，因?yàn)槭莾蓚€(gè)異步的時(shí)鐘，所以用鎖存器來(lái)避免產(chǎn)生亞穩(wěn)態(tài)。為了生成空滿標(biāo)志，我們采用格雷碼來(lái)編寫(xiě)。我們可以看出FIFO中的讀寫(xiě)指針是一個(gè)循環(huán)指針，讀寫(xiě)指針初始化值都為0，滿標(biāo)志初始化為0，空標(biāo)志初始化值為1.讀寫(xiě)操作開(kāi)始的時(shí)候，每做一次寫(xiě)操作，寫(xiě)指針加1，每做一次讀操作，讀指針也加1,。當(dāng)讀指針在加1過(guò)程中與寫(xiě)指針相等的時(shí)候，表示緩沖區(qū)為空，應(yīng)置空標(biāo)志。反之，寫(xiě)指針加1過(guò)程中等于讀指針，緩沖區(qū)滿，應(yīng)置滿標(biāo)志。 經(jīng)上面的分析，結(jié)合格雷碼的特點(diǎn)

7、，我們可以將滿標(biāo)志定義如下： overflow=(wptrnrptrn-1)&(wptrn-1rptrn 我們可以將空標(biāo)志定義如下： underflow=(wptrnrptrn-1&(wptrn-1rptrn)分析后根據(jù)RTL設(shè)計(jì)的規(guī)則來(lái)編寫(xiě)代碼如下所示：/asyn fifotimescale 1ns/1nsmodule fifo (wdata,full,winc,wclk,wrst_n,rdata,rinc,empty,rclk,rrst_n);/-parameterWIDTH = 8;parameter DEPTH = 2;parametermax_count = 2

8、9;b11;/-inputWIDTH:0wdata;inputwinc;inputwclk;inputwrst_n;inputrinc;inputrclk;inputrrst_n;/-outputfull;outputWIDTH:0rdata;outputempty;/-regfull_r;regempty_r;regWIDTH:0rdata_r;/-regDEPTH:0wptr; /n+1 ptrregDEPTH:0rptr;regDEPTH:0w1_rptr;regDEPTH:0w2_rptr;regDEPTH:0r1_wptr;regDEPTH:0r2_wptr;/-reg(WIDTH-

9、1):0fifomem 0:max_count;regDEPTH:0wbin,rbin;wireDEPTH:0rgnext,rbnext,wgnext,wbnext;regDEPTH:0 rgnext_r,rbnext_r;wire(DEPTH-1):0raddr,waddr;/reg(DEPTH-1):0raddr_r;wirefull_val,empty_val;/-/write inalways(posedge wclk)beginif(!winc&!full)/write enable no fullfifomemwaddr <= wdata;end/read outal

10、ways(posedge rclk)beginif(!rinc&!empty)rdata_r <= fifomemraddr;end/-/asyn write ptralways(posedge wclk or negedge wrst_n)beginif(!wrst_n)w2_rptr,w1_rptr <= 2'b00;elsew2_rptr,w1_rptr <= w1_rptr,rptr;end/-/generate wptr and wbinalways(posedge wclk or negedge wrst_n)beginif(!wrst_n)wbi

11、n,wptr <= 2'b00;elsewbin,wptr <= wbnext,wgnext;end/-assign waddr = wbin(DEPTH-1):0;assign wbnext = !full ? (wbin + !winc) : wbin;assignwgnext = (wbnext >> 1) wbnext;assign full_val = (wgnext = w2_rptrDEPTH,w2_rptr(DEPTH-1):0);always(posedge wclk or negedge wrst_n)beginif(!wrst_n)full

12、_r <= 1'b0;elsefull_r <= full_val;end/asyn read ptr -always(posedge rclk or negedge rrst_n)beginif(!rrst_n)r2_wptr,r1_wptr <= 2'b00;elser2_wptr,r1_wptr <= r1_wptr,wptr;end/-/generate rbin and rptralways(posedge rclk or negedge rrst_n)beginif(!rrst_n)rbin,rptr <= 2'b00;else

13、rbin,rptr <= rbnext_r,rgnext_r;end/-assignraddr = rbin(DEPTH-1):0;assignrbnext = !empty ? (rbin + !rinc) :rbin;assign rgnext = (rbnext >> 1) rbnext;assignempty_val = (rgnext_r = r2_wptr);always(posedge rclk or negedge rrst_n)beginif(!rrst_n)empty_r <= 1'b0;elseempty_r <= empty_val

14、;end/-assignfull = full_r;assignempty = empty_r;assignrdata = rdata_r;/assign rgnext = rgnext_r;always (posedge rclk )beginrgnext_r <= rgnext;rbnext_r <= rbnext;/raddr_r <= raddr;endendmodule在quartus II中進(jìn)行編譯，語(yǔ)法正確無(wú)誤后在modelsim中進(jìn)行仿真查看是否有滿足預(yù)設(shè)的功能和要求。編譯文件（testbench）如下所示。timescale 1 ns/ 1 psmodule

15、 FIFO_vlg_tst();/ constants / general purpose registers/reg eachvec;/ test vector input registersreg 7:0 IN;reg RD_CLOCK;reg RINC;reg RRESET_N;reg WINC;reg WRESET_N;reg WR_CLOCK;/ wires wire EMPTY_P;wire FULL_P;wire 7:0 OUT;/ assign statements (if any) FIFO i1 (/ port map - connection between master

16、 ports and signals/registers .EMPTY_P(EMPTY_P),.FULL_P(FULL_P),.IN(IN),.OUT(OUT),.RD_CLOCK(RD_CLOCK),.RINC(RINC),.RRESET_N(RRESET_N),.WINC(WINC),.WRESET_N(WRESET_N),.WR_CLOCK(WR_CLOCK);initial fork WR_CLOCK = 0;WINC = 1;#10 WRESET_N = 0;#20 WRESET_N = 1;#40 WINC = 0;/IN = 8'd10;join initial fork

17、 RD_CLOCK = 0;RINC = 1;#10 RRESET_N = 0;#200 RRESET_N = 1;#400 RINC = 0;join always begin #10 WR_CLOCK = WR_CLOCK; end always begin #100 RD_CLOCK = RD_CLOCK; end endmoduleB、綜合過(guò)程將RTL文件拷如liux系統(tǒng)中進(jìn)行綜合，生成門(mén)級(jí)網(wǎng)表，并根據(jù)要求來(lái)編寫(xiě)約束文件，使文件最優(yōu)化。完成后的約束文件如下：#fifo constrains #authou johnny#design entry#read_verilog ./rtl/f

18、ifo.vcheck_designcurrent_designset_max_area 1000#set_min_area 0.0#setup operating conditions ,wire load, clocks,reset#create_clock -period 10 -waveform0 5 get_ports CLOCKcreate_clock -period 20 get_ports wclkcreate_clock -period 10 get_ports rclkset_dont_touch_network get_clocks wclkset_dont_touch_n

19、etwork get_clocks rclk#set_dont_touch_network list CLOCK RESET_Nset_operating_conditions -max WCIND -min WCCOMset_wire_load_model -name "10x10"set_wire_load_mode enclosedset_clock_latency 4.0 get_clocks wclkset_clock_latency 2.0 get_clocks rclkset_clock_uncertainty -setup 4.0 -hold 0.50 ge

20、t_clocks wclkset_clock_uncertainty -setup 2.0 -hold 0.25 get_clocks rclk#useful commands #report_port -verbose #report_clock#reset_design#list_libs#remove_design -all#remove_design -design#list_files#lists all files in DC memory#list_designs#list_license#input drives#set_driving_cell -lib_cell AN2 g

21、et_ports wdata#set_drive 0 list RESET_N#output load #set_load 5 all_outputs#set input & set output delay#set_input_delay -max 10 -clock wclk get_ports wdataset_input_delay -max 5 -clock rclk get_ports rdataset_output_delay -max 3.3 -clock rclk get_ports rdata#set_input_delay 5 -clock CLOCK all_i

22、nputs#Advanced constrints#group_path#set_false_path#set_multicycle#compile and write the database#compile#create reports#write -hierarchy -format verilog -output ./rtl/fifo_timing.vwrite_sdc ./rtl/fifo_timing.sdcreport_timingreport_areareport_area > ./fifo_test.area_rptreport_constraint -all_viol

23、ators > fifo_test.constraint_rpt#gui_start#report#report_timing結(jié)果系統(tǒng)功能仿真波形：時(shí)序仿真波形：總結(jié)及感想雖然該設(shè)計(jì)用了差不多兩個(gè)星期的時(shí)間，雖然效率不高，但也對(duì)學(xué)到了不少東西。對(duì)同步異步信號(hào)有了較深的理解，以及怎樣通過(guò)看RTL和描述語(yǔ)言作對(duì)比，找出問(wèn)題的所在，此方法對(duì)于小的設(shè)計(jì)及有幫助。同時(shí)也讓我積累了一些經(jīng)驗(yàn)，比如在設(shè)計(jì)之前還查找相關(guān)的資料，了解該方面設(shè)計(jì)目前的大體情況。整理好設(shè)計(jì)方案、思想等。這樣能在很大程度上提高設(shè)計(jì)效率。附件：門(mén)級(jí)網(wǎng)表：module fifo ( wdata, full, winc, wclk,

24、wrst_n, rdata, rinc, empty, rclk, rrst_n ); input 8:0 wdata; output 8:0 rdata; input winc, wclk, wrst_n, rinc, rclk, rrst_n; output full, empty; wire N5, N6, fifomem07 , fifomem06 , fifomem05 , fifomem04 , fifomem03 , fifomem02 , fifomem01 , fifomem00 , fifomem17 , fifomem16 , fifomem15 , fifomem14

25、, fifomem13 , fifomem12 , fifomem11 , fifomem10 , fifomem27 , fifomem26 , fifomem25 , fifomem24 , fifomem23 , fifomem22 , fifomem21 , fifomem20 , fifomem37 , fifomem36 , fifomem35 , fifomem34 , fifomem33 , fifomem32 , fifomem31 , fifomem30 , N14, N15, N16, N17, N18, N19, N20, N21, w2_rptr2 , full_va

26、l, rbin2 , empty_val, n10, n20, n23, n26, n29, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81

27、, n82, n83, n84, n85, n86, n87, n88, n89, n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, dp_cluster_0/N34 , N32, dp_cluster_1/N36 , N31, n128, n129, n130, n131

28、, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181

29、, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193; wire 2:0 w1_rptr; wire 2:0 rptr; wire 2:0 wbnext; wire 1:0 wgnext; wire 2:0 wptr; wire 2:0 wbin; wire 2:0 r1_wptr; wire 1:0 rbnext_r; wire 2:0 rgnext_r; wire 2:0 rbnext; wire 2:0 rgnext; assign rdata8 = 1'b0; FD2 wptr_reg2

30、 ( .D(wbnext2), .CP(wclk), .CD(wrst_n), .Q(wptr2) ); FD2 wptr_reg1 ( .D(wgnext1), .CP(wclk), .CD(wrst_n), .Q(wptr1) ); FD2 wptr_reg0 ( .D(wgnext0), .CP(wclk), .CD(wrst_n), .Q(wptr0) ); FD2 wbin_reg2 ( .D(wbnext2), .CP(wclk), .CD(wrst_n), .Q(wbin2) ); FD2 r1_wptr_reg2 ( .D(wptr2), .CP(rclk), .CD(rrst

31、_n), .Q(r1_wptr2) ); FD2 r1_wptr_reg1 ( .D(wptr1), .CP(rclk), .CD(rrst_n), .Q(r1_wptr1) ); FD2 r1_wptr_reg0 ( .D(wptr0), .CP(rclk), .CD(rrst_n), .Q(r1_wptr0) ); FD2 r2_wptr_reg2 ( .D(r1_wptr2), .CP(rclk), .CD(rrst_n), .QN(n38) ); FD2 r2_wptr_reg1 ( .D(r1_wptr1), .CP(rclk), .CD(rrst_n), .QN(n39) ); F

32、D2 r2_wptr_reg0 ( .D(r1_wptr0), .CP(rclk), .CD(rrst_n), .QN(n37) ); FD1 rbnext_r_reg2 ( .D(rbnext2), .CP(rclk), .Q(rgnext2) ); FD1 rgnext_r_reg2 ( .D(rgnext2), .CP(rclk), .Q(rgnext_r2) ); FD2 rptr_reg2 ( .D(rgnext_r2), .CP(rclk), .CD(rrst_n), .Q(rptr2) ); FD2 w1_rptr_reg2 ( .D(rptr2), .CP(wclk), .CD

33、(wrst_n), .Q(w1_rptr2) ); FD2 w2_rptr_reg2 ( .D(w1_rptr2), .CP(wclk), .CD(wrst_n), .Q( w2_rptr2 ) ); FD2 rbin_reg2 ( .D(rgnext2), .CP(rclk), .CD(rrst_n), .Q(rbin2 ) ); FD1 rbnext_r_reg1 ( .D(rbnext1), .CP(rclk), .Q(rbnext_r1) ); FD2 rbin_reg1 ( .D(rbnext_r1), .CP(rclk), .CD(rrst_n), .Q(N6), .QN( n16

34、3) ); FD1 rgnext_r_reg1 ( .D(rgnext1), .CP(rclk), .Q(rgnext_r1) ); FD2 rptr_reg1 ( .D(rgnext_r1), .CP(rclk), .CD(rrst_n), .Q(rptr1) ); FD2 w1_rptr_reg1 ( .D(rptr1), .CP(wclk), .CD(wrst_n), .Q(w1_rptr1) ); FD2 w2_rptr_reg1 ( .D(w1_rptr1), .CP(wclk), .CD(wrst_n), .QN(n40) ); FD1 rbnext_r_reg0 ( .D(rbn

35、ext0), .CP(rclk), .Q(rbnext_r0) ); FD2 rbin_reg0 ( .D(rbnext_r0), .CP(rclk), .CD(rrst_n), .Q(N5), .QN( n178) ); FD1 rgnext_r_reg0 ( .D(rgnext0), .CP(rclk), .Q(rgnext_r0) ); FD2 rptr_reg0 ( .D(rgnext_r0), .CP(rclk), .CD(rrst_n), .Q(rptr0) ); FD2 w1_rptr_reg0 ( .D(rptr0), .CP(wclk), .CD(wrst_n), .Q(w1

36、_rptr0) ); FD2 w2_rptr_reg0 ( .D(w1_rptr0), .CP(wclk), .CD(wrst_n), .QN(n41) ); FD1 fifomem_reg07 ( .D(n96), .CP(wclk), .Q(fifomem07 ), .QN(n73) ); FD1 fifomem_reg06 ( .D(n97), .CP(wclk), .Q(fifomem06 ), .QN(n72) ); FD1 fifomem_reg05 ( .D(n98), .CP(wclk), .Q(fifomem05 ), .QN(n71) ); FD1 fifomem_reg0

37、4 ( .D(n99), .CP(wclk), .Q(fifomem04 ), .QN(n70) ); FD1 fifomem_reg03 ( .D(n100), .CP(wclk), .Q(fifomem03 ), .QN(n69) ); FD1 fifomem_reg02 ( .D(n101), .CP(wclk), .Q(fifomem02 ), .QN(n68) ); FD1 fifomem_reg01 ( .D(n102), .CP(wclk), .Q(fifomem01 ), .QN(n67) ); FD1 fifomem_reg00 ( .D(n103), .CP(wclk),

38、.Q(fifomem00 ), .QN(n66) ); FD1 fifomem_reg17 ( .D(n104), .CP(wclk), .Q(fifomem17 ), .QN(n65) ); FD1 fifomem_reg16 ( .D(n105), .CP(wclk), .Q(fifomem16 ), .QN(n64) ); FD1 fifomem_reg15 ( .D(n106), .CP(wclk), .Q(fifomem15 ), .QN(n63) ); FD1 fifomem_reg14 ( .D(n107), .CP(wclk), .Q(fifomem14 ), .QN(n62)

39、 ); FD1 fifomem_reg13 ( .D(n108), .CP(wclk), .Q(fifomem13 ), .QN(n61) ); FD1 fifomem_reg12 ( .D(n109), .CP(wclk), .Q(fifomem12 ), .QN(n60) ); FD1 fifomem_reg11 ( .D(n110), .CP(wclk), .Q(fifomem11 ), .QN(n59) ); FD1 fifomem_reg10 ( .D(n111), .CP(wclk), .Q(fifomem10 ), .QN(n58) ); FD1 fifomem_reg27 (

40、.D(n112), .CP(wclk), .Q(fifomem27 ), .QN(n57) ); FD1 fifomem_reg26 ( .D(n113), .CP(wclk), .Q(fifomem26 ), .QN(n56) ); FD1 fifomem_reg25 ( .D(n114), .CP(wclk), .Q(fifomem25 ), .QN(n55) ); FD1 fifomem_reg24 ( .D(n115), .CP(wclk), .Q(fifomem24 ), .QN(n54) ); FD1 fifomem_reg23 ( .D(n116), .CP(wclk), .Q(

41、fifomem23 ), .QN(n53) ); FD1 fifomem_reg22 ( .D(n117), .CP(wclk), .Q(fifomem22 ), .QN(n52) ); FD1 fifomem_reg21 ( .D(n118), .CP(wclk), .Q(fifomem21 ), .QN(n51) ); FD1 fifomem_reg20 ( .D(n119), .CP(wclk), .Q(fifomem20 ), .QN(n50) ); FD1 fifomem_reg37 ( .D(n120), .CP(wclk), .Q(fifomem37 ), .QN(n49) );

42、 FD1 fifomem_reg36 ( .D(n121), .CP(wclk), .Q(fifomem36 ), .QN(n48) ); FD1 fifomem_reg35 ( .D(n122), .CP(wclk), .Q(fifomem35 ), .QN(n47) ); FD1 fifomem_reg34 ( .D(n123), .CP(wclk), .Q(fifomem34 ), .QN(n46) ); FD1 fifomem_reg33 ( .D(n124), .CP(wclk), .Q(fifomem33 ), .QN(n45) ); FD1 fifomem_reg32 ( .D(

43、n125), .CP(wclk), .Q(fifomem32 ), .QN(n44) ); FD1 fifomem_reg31 ( .D(n126), .CP(wclk), .Q(fifomem31 ), .QN(n43) ); FD1 fifomem_reg30 ( .D(n127), .CP(wclk), .Q(fifomem30 ), .QN(n42) ); FD2 empty_r_reg ( .D(empty_val), .CP(rclk), .CD(rrst_n), .Q(empty), .QN( dp_cluster_1/N36 ) ); FD1 rdata_r_reg0 ( .D

44、(n89), .CP(rclk), .Q(rdata0), .QN(n74) ); FD1 rdata_r_reg1 ( .D(n88), .CP(rclk), .Q(rdata1), .QN(n75) ); FD1 rdata_r_reg2 ( .D(n87), .CP(rclk), .Q(rdata2), .QN(n76) ); FD1 rdata_r_reg3 ( .D(n86), .CP(rclk), .Q(rdata3), .QN(n77) ); FD1 rdata_r_reg4 ( .D(n85), .CP(rclk), .Q(rdata4), .QN(n78) ); FD1 rd

45、ata_r_reg5 ( .D(n84), .CP(rclk), .Q(rdata5), .QN(n79) ); FD1 rdata_r_reg6 ( .D(n83), .CP(rclk), .Q(rdata6), .QN(n80) ); FD1 rdata_r_reg7 ( .D(n82), .CP(rclk), .Q(rdata7), .QN(n81) ); OR2 U68 ( .A(full), .B(winc), .Z(n20) ); AN3 U69 ( .A(n31), .B(n32), .C(n33), .Z(full_val) ); AN3 U75 ( .A(n34), .B(n

46、35), .C(n36), .Z(empty_val) ); EOI U3 ( .A(rgnext2), .B(rbnext_r1), .Z(rgnext1) ); EOI U4 ( .A(rbnext_r1), .B(rbnext_r0), .Z(rgnext0) ); EOI U70 ( .A(wgnext1), .B(n40), .Z(n33) ); EOI U71 ( .A(wbnext2), .B(wbnext1), .Z(wgnext1) ); EOI U72 ( .A(wbnext2), .B(w2_rptr2 ), .Z(n32) ); EOI U73 ( .A(wgnext0), .B(n41), .Z(n31) ); EOI U74 ( .A(wbnext0), .B(wbnext1), .Z(wgnext0) ); EOI U76 ( .A(rgnext_r2), .B(n38), .Z(n36) ); EOI U77 ( .A(rgnext_r1), .B(n39), .Z(n35) ); EOI U78 ( .A(rgnext_r0), .B(n37), .Z(n34) ); FD2 wbin_reg1 ( .D(wbnext1), .CP(wclk), .CD(wrst_