單片機(jī)英文文獻(xiàn)及翻譯

1、 南 京 工 程 學(xué) 院畢業(yè)設(shè)計(jì)文獻(xiàn)資料翻譯 （原文及譯文） 原文名稱：Structure and function of the MCS-51 series課題名稱： 基于單片機(jī)的交通燈控制系統(tǒng) 學(xué)生姓名： 吳茜茜 學(xué) 號(hào)： 240072310 指導(dǎo)老師： 宋 紅 梅 所在系部： 康尼學(xué)院 專業(yè)名稱： 通信工程 2011 年 3 月 南 京Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer MCS-51 is a name of a p

2、iece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have, such as 8051, 803

3、1, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same.8051 daily representatives-51 serial one-chip computers.A one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). ( 2) At slice data memory RA

4、M (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM wit

5、hin some one-chip computers, such as 8031, 8032.(4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into

6、a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control system of the source. (7) One all duplex serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or o

7、ne-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus

8、.Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 stor

9、ing device temporaries of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is i

10、t make operation to go on to count temporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a

11、express in the order. The controller includes the procedure counter, the order is deposited, the order deciphering, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is t

12、he next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out. Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. T

13、his pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded.There are ROM (procedure memory , can only read ) and R

14、AM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the proced

15、ure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, using for middle result to deposit operation, the data are stored temporarily and the data are buffered. In RAM of this 128B, there is unit of 32 bytes that can be appointed as the job register, this and gene

16、ral microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM ca

17、n arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order simila

18、rly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedu

19、re memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH, 0000H of loc

20、ation, in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses o

21、verlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice.8051 one-chip computer have four 8 walk abreast

22、I/O ports, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register), one exports the driver and a introduction buffer. Make

23、 data can latch when outputting, data can buffer when making introduction, but four function of pass away these self-same. Expand among the system of memory outside having slice, four ports these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside havi

24、ng slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use port cor

25、rectly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability an

26、d interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouth, its output grade draws the resistance supremely. When using it as the mouth in common use, output grade is it leak circuit to turn on, is it urge NMOS draw the resistance on taking to be

27、 outer with it while inputting to go out to fail. When being used as introduction, should write"1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circ

28、uit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change

29、 approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate, can draw the pin to the high level fast; when resistance value is very large, P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw electric cu

30、rrent load to offer outwards, draw the resistance on needn't answer and thinking. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end relatively about 20,000 ohms because of load resistance in scene and because 40,000 ohms, will not ex

31、ert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1.P3 mouth one multi-functional port, mouth getting many than P1 it have "3 doors a

32、nd 4 buffers". Two parts there, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and" door 3 functions one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W=At 1 o'

33、;clock, output Q end signal; act as Q=At 1 o'clock, can output W line signal. At the time of programming, it is that the first function is still the second function but needn't have software that set up P3 mouth in advance .It hardware not inside is the automatic to have two function outputt

34、ed when CPU carries on SFR and seeks the location to visit to P3 mouth/at not lasting lining, there are inside hardware latch Qs=1. The operation principle of P3 mouth is similar to P1 mouth.Output grade, P3 of mouth, P1 of P1, connect with inside have load resistance of drawing, every one of they c

35、an drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way. Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, d

36、o not need to have the resistance of drawing outer. Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first. As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urgi

37、ng one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base, in order to the electricity while restraining the high level from exporting P1P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function

38、 is to turn PC into 0000H initially, make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally, as because procedure operate it make mistakes or operate there aren't mistake, in order to extricate oneself f

39、rom a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective, should sustain 24 shake cycle (namely 2 machine cycles) the above its effe

40、ctive times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: restore to the throne the circuit and inc

41、lude two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST) hand over to Schmitt's trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and re

42、stored to the throne and operated the necessary signal inside. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored t

43、o the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running, should first check it can restore to the throne not succeeding. Checking and can pop one's head and monitor the pin with the oscilloscope tentatively, push and is resto

44、red to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change.MCS-51系列單片機(jī)的功能和結(jié)構(gòu)MSC-51系列單片機(jī)具有一個(gè)單芯片電腦的結(jié)構(gòu)和功能，它是英特爾公司的系列產(chǎn)品的名稱。這家公司在1976年推出后，引進(jìn)8位單芯片的MCS-48

45、系列計(jì)算機(jī)后于1980年推出的8位的MCS-51系列單芯片計(jì)算機(jī)。諸如此類的單芯片電腦有很多種，如8051，8031，8751，80C51BH,80C31BH等，其基本組成，基本性能和指令系統(tǒng)都是相同的。8051是51系列單芯片電腦的代表。一個(gè)單芯片的計(jì)算機(jī)是由以下幾個(gè)部分組成：（1）一個(gè)8位的微處理器（CPU）。（2）片內(nèi)數(shù)據(jù)存儲(chǔ)器RAM（128B/256B）,它只讀/寫數(shù)據(jù)，如結(jié)果不在操作過程中，最終結(jié)果要顯示數(shù)據(jù)（3）程序存儲(chǔ)器ROM/EPROM(4KB/8KB).是用來保存程序一些初步的數(shù)據(jù)和切片的形式。但一些單芯片電腦沒有考慮ROM/EPROM,如8031，8032，80C51等等。

46、（4）4個(gè)8路運(yùn)行的I/O接口，P0，P1，P2，P3，每個(gè)接口可以用作入口，也可以用作出口。（5）兩個(gè)定時(shí)/計(jì)數(shù)器， 每個(gè)定時(shí)方式也可以根據(jù)計(jì)算結(jié)果或定時(shí)控制實(shí)現(xiàn)計(jì)算機(jī)。（6）5個(gè)中斷（7）一個(gè)全雙工串行的I/UART（通用異步接收器I口/發(fā)送器（UART），它是實(shí)現(xiàn)單芯片電腦或單芯片計(jì)算機(jī)和計(jì)算機(jī)的串行通信使用。（）振蕩器和時(shí)鐘產(chǎn)生電路，需要考慮石英晶體微調(diào)能力。允許振蕩頻率為12MHz，每個(gè)上述的部分都是通過內(nèi)部數(shù)據(jù)總線連接。其中CPU是一個(gè)芯片計(jì)算機(jī)的核心，它是計(jì)算機(jī)的指揮中心，是由算術(shù)單元和控制器等部分組成。算術(shù)單元可以進(jìn)行位算術(shù)運(yùn)算和邏輯運(yùn)算，ALU單元是其中一種運(yùn)算器，18個(gè)存儲(chǔ)

47、設(shè)備，暫存設(shè)備的積累設(shè)備進(jìn)行協(xié)調(diào)，程序狀態(tài)寄存器PSW積累了2個(gè)輸入端的計(jì)數(shù)等檢查暫時(shí)作為一個(gè)操作往往由人來操作，誰儲(chǔ)存1輸入的是它使操作去上暫時(shí)計(jì)數(shù)，另有一個(gè)操作的結(jié)果，回環(huán)協(xié)調(diào)。此外，協(xié)調(diào)往往是作為對8051內(nèi)的數(shù)據(jù)傳輸轉(zhuǎn)運(yùn)站考慮。作為一般的微處理器，解碼的順序。振蕩器和定時(shí)電路等的程序計(jì)數(shù)器是一個(gè)由8個(gè)計(jì)數(shù)器為2，總計(jì)16位。這是一個(gè)字節(jié)的地址，其實(shí)程序計(jì)數(shù)器，是將在個(gè)人電腦內(nèi)進(jìn)行。從而改變它的內(nèi)容可以改變它的程序進(jìn)行。在8051的單芯片電腦的電路，只需要外部石英晶體和頻率微調(diào)電容，其頻率范圍為1.2MHz到12MHz。這種脈沖信號(hào)，作為8051的工作，即單位時(shí)間的最低基本節(jié)奏。8051

48、是其他電腦一樣，控制的基本工作在于和諧，就像一個(gè)管弦樂隊(duì)，根據(jù)擊敗發(fā)揮是指揮。有光盤（程序存儲(chǔ)器，只能讀?。⒃?051片（數(shù)據(jù)存儲(chǔ)器RAM，可以是可寫可讀，他們各自獨(dú)立的內(nèi)存地址空間，處理辦法是，與一般的電腦記憶體相同。8051可8751的程序存儲(chǔ)的存儲(chǔ)容量4KB的程序切片，地址開始從0000H開始執(zhí)行，維護(hù)的程序和形式不斷使用。數(shù)據(jù)8051-8751的內(nèi)存數(shù)據(jù)存儲(chǔ)器128B）條8031，地址虛假00FH，中層結(jié)果存入操作使用，數(shù)據(jù)存儲(chǔ)和數(shù)據(jù)暫時(shí)緩沖等。在這128B條內(nèi)存，有32字節(jié)，可以作為工作寄存器使用，這和一般的微處理器是不同的，8051片RAM和登記形式的同一級(jí)到安排的位置。這不是

49、很相同，MCS-51系列內(nèi)存的單芯片計(jì)算機(jī)和通用計(jì)算機(jī)為主。通用計(jì)算機(jī)的第一個(gè)地址空間，ROM和RAM,可安排在不同的空間在這個(gè)范圍內(nèi)的地址范圍，即ROM和RAM 地址的形成與分布在不同的地址空間。在訪問內(nèi)存，相應(yīng)的，只有一個(gè)地址的內(nèi)存單元，可以用外部存儲(chǔ)，也可以內(nèi)存，并通過訪問順序與此類似。這種內(nèi)存結(jié)構(gòu)的一種被稱為普林斯頓結(jié)構(gòu)。8051記憶分為程序存儲(chǔ)器空間和數(shù)據(jù)存儲(chǔ)空間的物理結(jié)構(gòu)上劃分，有四個(gè)在所有的記憶體空間。在1和數(shù)據(jù)外部數(shù)據(jù)存儲(chǔ)器和程序存儲(chǔ)器空間之一，一組在外面一個(gè)內(nèi)存空間的程序商店，結(jié)構(gòu)這一種形式的程序和數(shù)據(jù)存儲(chǔ)器器件數(shù)據(jù)存儲(chǔ)分開的形式，稱為哈佛結(jié)構(gòu)。但是，從用戶使用，8051的內(nèi)

50、存地址空間分為三種：分為（1）片內(nèi)，（使用16個(gè)地址一致的FFFFH，地點(diǎn)為0000H）。（2）64KB的外部數(shù)據(jù)存儲(chǔ)器空間的一個(gè)地址，該地址是從0000H開始執(zhí)行64KB的FFFFH安排16地址，也到該位置。（3）數(shù)據(jù)存儲(chǔ)器的256B（使用8個(gè)地址）的地址空間。上述三個(gè)內(nèi)存空間的地址重疊，區(qū)分和設(shè)計(jì)的8051指令系統(tǒng)中不同的數(shù)據(jù)傳輸順序代碼，CPU的訪問片，訪問RAM塊順序使用MOVX指令外片，內(nèi)存為訪問片。8051單芯片的電腦有4個(gè)8步行并進(jìn)的I/O端口，分別為P0,P1,P2和P3。每個(gè)端口8位的雙向口，共占了32針。每一個(gè)I/O線可作為獨(dú)立的入口和出口。每個(gè)端口包括一個(gè)鎖存器，1名入口和一出口引進(jìn)緩沖區(qū)。使數(shù)據(jù)能鎖存輸