數(shù)字集成電路設(shè)計(jì)

1、數(shù)字集成電路設(shè)計(jì)1. 課程情況簡(jiǎn)介2. 集成電路系統(tǒng)規(guī)模3. 數(shù)字與模擬集成電路設(shè)計(jì)4. 你將在這門課上學(xué)到什么？5. 從CMOS到系統(tǒng)的綜合概述北京市最大的市屬211大學(xué)全國(guó)20所A類微電子學(xué)院之一培訓(xùn)集成電路設(shè)計(jì)、微電子器件與工藝人才全新的授課內(nèi)容與理念廣闊的就業(yè)前景和旺盛的就業(yè)需求國(guó)際合作與交流將是未來(lái)的重要方向微信號(hào)：Wensi_Vincent郵箱： 辦公室電話： 6739-2620手機(jī)： 135209620598次課程：1次介紹課程，7次正式課程周二晚， 9-12節(jié)，每次4學(xué)時(shí)從下次課程起在科學(xué)樓（綜合樓）中廳考試形式： 40% 平時(shí)分（作業(yè)、出勤等）+60%考試分參考書(shū)目：1. 超

2、大規(guī)模集成電路與系統(tǒng)導(dǎo)論 John P. Uyemura 周潤(rùn)德 譯2.數(shù)字集成電路-設(shè)計(jì)透視 Jan Rabaey第一次課：歷史、發(fā)展與宏觀概述： “什么是數(shù)字微電子”第二次課：MOSFET和CMOS 邏輯門第三次課：CMOS集成電路的物理結(jié)構(gòu)與制造工藝第四次課：Verilog硬件描述語(yǔ)言（常用部件）第五次課：SPICE Level 1&2仿真(以反相器為例）第六次課：版圖Layout設(shè)計(jì)第七次課：系統(tǒng)級(jí)物理設(shè)計(jì)、可靠性與測(cè)試第八次課：高速CMOS邏輯與低功率CMOS電路以及內(nèi)存芯片設(shè)計(jì) 7n+n+SGD+DEVICECIRCUITGATEMODULESYSTEM8910First tran

3、sistorBell Labs, 194811Bipolar logic1960sECL 3-input GateMotorola 19661219711000 transistors1 MHz operation1315lIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. lHe made a prediction that semiconductor technology will double its effectiveness every

4、18 months16171,000,0001,000,000100,000100,00010,00010,0001,0001,00010101001001 119751975 19801980 19851985 19901990 19951995 20002000 20052005 20102010808680868028680286i386i386i486i486PentiumPentium PentiumPentium Pro ProK KPentiumPentium II IIPentiumPentium IIIIIICourtesy, Intel1840044004800880088

5、08080808085808580868086286286386386486486Pentium procPentium procP6P60.0010.0010.010.010.10.11 11010100100100010001970197019801980199019902000200020102010YearYearTransistors (MT)Transistors (MT)2 2X growth in 1.96 years!X growth in 1.96 years!Transistors on Lead Microprocessors double every 2 yearsT

6、ransistors on Lead Microprocessors double every 2 yearsCourtesy, Intel194004400480088008808080808085808580868086286286386386486486Pentium procPentium procP6P61 110101001001970197019801980199019902000200020102010YearYearDie size (mm)Die size (mm)7% 7% growth per yeargrowth per year22X growth in 10 ye

7、arsX growth in 10 yearsDie size grows by 14% to satisfy Moores LawDie size grows by 14% to satisfy Moores LawCourtesy, Intel20P6P6Pentium procPentium proc48648638638628628680868086808580858080808080088008400440040.10.11 110101001001000100010000100001970197019801980199019902000200020102010YearYearFre

8、quency (Mhz)Frequency (Mhz)Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 yearsDoubles every2 yearsCourtesy, Intel21P6P6Pentium procPentium proc48648638638628628680868086808580858080808080088008400440040.10.11 11010100100197119711974197419781978198

9、519851992199220002000YearYearPower (Watts)Power (Watts)Lead Microprocessors power continues to increaseLead Microprocessors power continues to increaseCourtesy, Intel225 5KW KW 1818KW KW 1.51.5KW KW 500500W W 4004400480088008808080808085808580868086286286386386486486Pentium procPentium proc0.10.11 1

10、101010010010001000100001000010000010000019711971 19741974 19781978 19851985 19921992 20002000 20042004 20082008YearYearPower (Watts)Power (Watts)Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitiveCourtesy, Intel2340044004800880088080808080858085808680

11、86286286386386486486Pentium procPentium procP6P61 110101001001000100010000100001970197019801980199019902000200020202020YearYearPower Density (W/cm2)Power Density (W/cm2)Hot PlateHot PlateNuclearNuclearReactorReactorRocketRocketNozzleNozzlePower density too high to keep junctions at low tempPower den

12、sity too high to keep junctions at low tempCourtesy, Intel24 “Microscopic Problems”Microscopic Problems” Ultra-high speed design Ultra-high speed design Interconnect Interconnect Noise, Crosstalk Noise, Crosstalk Reliability, Manufacturability Reliability, Manufacturability Power Dissipation Power D

13、issipation Clock distribution. Clock distribution.Everything Looks a Little DifferentEverything Looks a Little Different “Macroscopic Issues”Macroscopic Issues” Time-to-Market Time-to-Market Millions of Gates Millions of Gates PredictabilityPredictability etc. etc.and Theres a Lot of Them!and Theres

14、 a Lot of Them!? ?25How to evaluate performance of a digital circuit (gate, block, )? Cost Reliability Scalability Speed (delay, operating frequency) Power dissipation Energy to perform a function26 NRE (non-recurrent engineering) costs design time and effort, mask generation one-time cost factor Re

15、current costs silicon processing, packaging, test proportional to volume proportional to chip area27Single dieWaferFrom http:/12” (30cm)非常常見(jiàn)28Fabrication capital cost per transistor (Moores law)29%100per wafer chips ofnumber Totalper wafer chips good of No.Yyield Dieper wafer DiescostWafer cost Diea

16、rea die2diameterwafer area diediameter/2wafer per wafer Dies230area dieareaunit per defects1yield die is approximately 3 4area) (die cost diefnppnBASiO2AlABAlABCross-section of pn -junction in an IC process One-dimensionalrepresentationdiode symboln+n+p-substrateDSGBVGS+-DepletionRegionn-channel00.5

17、11.522.50123456x 10-4VDS (V)ID (A)VGS= 2.5 VVGS= 2.0 VVGS= 1.5 VVGS= 1.0 VResistiveSaturationVDS = VGS - VTtoxn+n+Cross sectionCross sectionLGate oxidexdxdLdPolysilicon gateTop viewTop viewGate-bulkoverlapSourcen+Drainn+Wp-welln-wellp+p-epiSiO2AlCupolyn+SiO2p+gate-oxideTungstenTiSi2oxidationoxidatio

18、nopticalopticalmaskmaskprocessprocessstepstepphotoresist coatingphotoresist coatingphotoresistphotoresistremoval (ashing)removal (ashing)spin, rinse, dryspin, rinse, dryacid etchacid etchphotoresist photoresist stepper exposurestepper exposuredevelopmentdevelopmentTypical operations in a single Typi

19、cal operations in a single photolithographic cycle (from Fullman).photolithographic cycle (from Fullman).Connect in MetalShare power and groundAbut cellsVDDC(a) pul l - d o wn netwo rkSN1SN4SN2SN3DFFADBCDFABCsub-net sDAABCVDDVDDB(c) com p l e t e g ateCell boundaryCell boundaryN WellN WellCell heigh

20、t 12 metal tracksMetal track is approx. 3 + 3Pitch = repetitive distance between objectsCell height is “12 pitch”2Rails 10 InInOutOutV VDDDDGNDGNDA AOutOutV VDDDDGNDGNDB B2-input NAND gateBVDDAtransmittersreceiversschematicsschematicsphysicalphysical422 Phase, with multiple conditional buffered cloc

21、ks 2.8 nF clock load 40 cm final driver widthLocal clocks can be gated “off” to save powerReduced load/skewReduced thermal issuesMultiple clocks complicate race checkingtrise = 0.35nstskew = 50pstcycle= 1.67nsGlobal clock waveformGlobal clock waveformPLL2 phase single wire clock, distributed globally2 distributed driver channels Reduced RC delay/skew Improved thermal distribution 3.75nF clock load 58 cm final driver widthLocal inverters for latchingConditional clocks in caches to reduce powerMore complex race checki