實(shí)驗(yàn)四 多周期CPU與存儲(chǔ)器實(shí)驗(yàn)

1、湘 潭 大 學(xué) 實(shí) 驗(yàn) 報(bào) 告   課程名稱(chēng)          計(jì)算機(jī)原理與設(shè)計(jì)              實(shí)驗(yàn)名稱(chēng)_多周期CPU與存儲(chǔ)器實(shí)驗(yàn) _   頁(yè)數(shù)     專(zhuān)業(yè)    &

2、#160;計(jì)算機(jī)科學(xué)與技術(shù)                   班級(jí)_2_  同組者姓名            組別          學(xué)號(hào)   &#

3、160;       2015962138     姓名  莊振南               實(shí)驗(yàn)日期_2016.11.02_   一、實(shí)驗(yàn)?zāi)康?1、深入理解MIPSCPU指令系統(tǒng)的功能和工作原理；2、掌握多周期CPU的工作原理和邏輯功能實(shí)現(xiàn)；3、熟練掌握用Verilog HDL語(yǔ)言設(shè)計(jì)多周期存儲(chǔ)

4、器的方法；4、熟練掌握對(duì)多周期存儲(chǔ)器的仿真實(shí)驗(yàn)驗(yàn)證和硬件測(cè)試兩種調(diào)試方法；5、通過(guò)對(duì)多周期CPU的運(yùn)行情況進(jìn)行觀察和分析，進(jìn)一步加深理解。二、實(shí)驗(yàn)要求 1、深入理解MIPSCPU指令系統(tǒng)的功能和工作原理；2、掌握多周期CPU的工作原理和邏輯功能實(shí)現(xiàn)；3、熟練掌握用Verilog HDL語(yǔ)言設(shè)計(jì)多周期存儲(chǔ)器的方法；三、實(shí)驗(yàn)原理 實(shí)現(xiàn)上述原理框圖根據(jù)功能將其分劃分為控制單元(cunit)、執(zhí)行單元(eunit)、指令單元(iunit)以及存儲(chǔ)單元(munit)四大模塊。 （1）.控制單元(cunit)是多周期微處理器的核心控制微處理器取指令、指令譯碼和指令執(zhí)行等工作。主要由指令譯碼器控制器(out

5、puts control)、算術(shù)邏輯運(yùn)算控制器(ALU control)兩個(gè)子模塊組成。 （2）.執(zhí)行單元(eunit)主要由寄存器堆(registers)和算術(shù)邏輯單元(ALU)兩個(gè)子模塊組成。其中寄存器是微處理器最基本的元素MIPS系統(tǒng)的寄存器堆由32個(gè)32位寄存器組成而ALU則是微處理器的主要功能部件執(zhí)行加、減、比較等算術(shù)運(yùn)算和與、或、或非、異或等邏輯運(yùn)算。指令單元(iunit)的作用是決定下一條指令的地址PC值。 （3）.存儲(chǔ)單元(munit)由存儲(chǔ)器(memory)、指令寄存器(instruction register)和存儲(chǔ)數(shù)據(jù)寄存器(memory data register)組成

6、。四、實(shí)驗(yàn)內(nèi)容 1、設(shè)計(jì)一個(gè)32位MIPS多周期CPU具體的要求如下: 至少運(yùn)行下列的6類(lèi)32條MIPS指令。 （1）算術(shù)邏輯指令and、sub、addi （2）邏輯運(yùn)算指令and、0r、xor、 andi、 ori、xori（3）位移指令sll、srl、sra（4）條件分支指令beq、bne、（5）無(wú)條件跳轉(zhuǎn)指令j、jr （6）數(shù)據(jù)傳送指令lw、sw2.設(shè)計(jì)一個(gè)存儲(chǔ)器五、實(shí)驗(yàn)環(huán)境與設(shè)備 電腦，電箱。六、實(shí)驗(yàn)代碼設(shè)計(jì)（含符號(hào)說(shuō)明） 寄存器元件代碼：module regfile (rna,rnb,d,wn,we,clk,clrn,qa,qb);input4:0rna,rnb,wn;input31

7、:0d;inputwe,clk,clrn;output31:0qa,qb;reg31:0register1:31;/r1-r31assign qa = (rna = 0) ? 0 : registerrna;/readassign qb = (rnb = 0) ? 0 : registerrnb;/readalways (posedge clk or negedge clrn) beginif (clrn = 0) begin/resetinteger i;for (i=1; i<32; i=i+1)registeri <= 0;endelse beginif (wn != 0)

8、&& (we = 1)/writeregisterwn <= d;endendendmodule32位四選一選擇器：module mux4x32 (a0,a1,a2,a3,s,y);input 31:0a0,a1,a2,a3;input1:0s;output31:0y;function31:0select;input 31:0a0,a1,a2,a3;input 1:0s;case (s)2'b00:select=a0;2'b01:select=a1;2'b10:select=a2;2'b11:select=a3;endcaseendfunc

9、tionassigny=select (a0,a1,a2,a3,s);endmodule5位二選一選擇器：module mux2x5 (a0,a1,s,y);input 4:0a0,a1;inputs;output4:0y;assigny = s ? a1 : a0;endmodule32位二選一選擇器：module mux2x32 (a0,a1,s,y);input 31:0a0,a1;inputs;output31:0y;assigny = s ? a1 : a0;endmodule存儲(chǔ)器元件：module mcmem (clk, dataout, datain, addr, we, in

10、clk, outclk);input31:0 datain;input31:0 addr;inputclk, we, inclk, outclk;output31:0dataout;wirewrite_enable = we & clk;lpm_ram_dqram (.data(datain),.address(addr7:2),.we(write_enable),.inclock(inclk),.outclock(outclk),.q(dataout);defparamram.lpm_width=32;defparam ram.lpm_widthad=6;defparamram.lp

11、m_indata="registered"defparamram.lpm_outdata="registered"defparamram.lpm_file="mcmem.mif"defparamram.lpm_address_control="registered"endmodule控制部件：module mccu (op, func, z, clock, resetn, wpc, wir, wmem, wreg, iord, regrt, m2reg, aluc, shift, alusrca, alusrcb,

12、 pcsource, jal, sext, state);input5:0op, func;inputz, clock, resetn;output regwpc, wir, wmem, wreg, iord, regrt, m2reg;output reg3:0aluc;output reg1:0alusrcb, pcsource;output regshift, alusrca, jal, sext;output reg2:0state;reg2:0next_state;parameter2:0sif=3'b000,/ IF statesid=3'b001,/ ID sta

13、tesexe=3'b010,/ EXE statesmem=3'b011,/ MEM stateswb=3'b100;/ WB statewire r_type,i_add,i_sub,i_and,i_or,i_xor,i_sll,i_srl,i_sra,i_jr;wire i_addi,i_andi,i_ori,i_xori,i_lw,i_sw,i_beq,i_bne,i_lui,i_j,i_jal;and(r_type,op5,op4,op3,op2,op1,op0);and(i_add,r_type, func5,func4,func3,func2,func1,f

14、unc0);and(i_sub,r_type, func5,func4,func3,func2, func1,func0);and(i_and,r_type, func5,func4,func3, func2,func1,func0);and(i_or, r_type, func5,func4,func3, func2,func1, func0);and(i_xor,r_type, func5,func4,func3, func2, func1,func0);and(i_sll,r_type,func5,func4,func3,func2,func1,func0);and(i_srl,r_ty

15、pe,func5,func4,func3,func2, func1,func0);and(i_sra,r_type,func5,func4,func3,func2, func1, func0);and(i_jr, r_type,func5,func4, func3,func2,func1,func0);and(i_addi,op5,op4, op3,op2,op1,op0);and(i_andi,op5,op4, op3, op2,op1,op0);and(i_ori, op5,op4, op3, op2,op1, op0);and(i_xori,op5,op4, op3, op2, op1,

16、op0);and(i_lw, op5,op4,op3,op2, op1, op0);and(i_sw, op5,op4, op3,op2, op1, op0);and(i_beq, op5,op4,op3, op2,op1, op0);and(i_bne, op5,op4,op3, op2,op1, op0);and(i_lui, op5,op4, op3, op2, op1, op0);and(i_j, op5,op4,op3,op2, op1,op0);and(i_jal, op5,op4,op3,op2, op1, op0);wire i_shift;or (i_shift,i_sll,

17、i_srl,i_sra);always * begin/ control signals' dfault outputs:wpc=0;/do not write pcwir=0;/do not write irwmem=0;/ do not write memorywreg=0;/ do not write register fileiord=0;/ select pc as memory addressaluc=4'bx000;/ ALU operation: addalusrca=0;/ ALU input a: reg a or saalusrcb=2'h0;/

18、ALU input b: reg bregrt=0;/ reg dest no: rdm2reg=0;/ select reg cshift=0;/ select reg apcsource=2'h0;/ select alu outputjal=0;/ not a jalsext=1;/ sign extendcase (state)/- IF:sif: begin/ IF statewpc=1;/ write pcwir=1;/ write IRalusrca=1;/ PCalusrcb=2'h1;/ 4next_state=sid;/ next state: IDend/

19、- ID:sid: begin/ ID stateif (i_j) begin/ j instructionpcsource=2'h3;/ jump addresswpc=1;/ write PCnext_state=sif;/ next state: IFendelse if (i_jal) begin/ jal instructionpcsource=2'h3;/ jump addresswpc=1;/ write PCjal=1;/ reg no = 31wreg=1;/ save PC+4next_state=sif;/ next state: IFendelse if

20、 (i_jr) begin/ jr instructionpcsource=2'h2;/ jump registerwpc=1;/ write PCnext_state=sif;/ next state: IFendelse begin/ other instructionaluc=4'bx000;/ addalusrca=1;/ PCalusrcb=2'h3;/ branch offsetnext_state=sexe;/ next state: EXEendend/- EXE:sexe: begin/ EXE statealuc3=i_sra;aluc2=i_sub

21、 | i_or | i_srl | i_sra | i_ori | i_lui ;aluc1=i_xor | i_sll | i_srl | i_sra | i_xori | i_beq | i_bne | i_lui ;aluc0=i_and | i_or | i_sll | i_srl | i_sra | i_andi | i_ori ;if (i_beq | i_bne) begin/ beq or bne instructionpcsource=2'h1;/ branch addresswpc=i_beq & z | i_bne & z;/ write PCne

22、xt_state=sif;/ next state: IFendelse begin/ other instructionif(i_lw | i_sw) begin/ lw or sw instructionalusrcb=2'h2;/ select offsetnext_state=smem;/ next state: MEMendelse begin/ other instructionif (i_shift)shift=1;/ shift instructionif (i_addi | i_andi | i_ori | i_xori | i_lui)alusrcb=2'h

23、2;/ select immediateif (i_andi | i_ori | i_xori)sext=0;/ 0-extendnext_state=swb;/ next state: WBendendend/- MEM:smem: begin/ MEM stateiord=1;/ memory address = Cif (i_lw) beginnext_state=swb;/ next state: WBendelse begin/ storewmem=1;/ write memorynext_state=sif;/ next state: IFendend/- WB:swb: begi

24、n/ WB stateif (i_lw)m2reg=1;/ select memory dataif (i_lw | i_addi | i_andi | i_ori | i_xori | i_lui)regrt=1;/ reg dest no: rtwreg=1;/ write register filenext_state=sif;/ next state: IFend/- ENDdefault: beginnext_state=sif;/default stateendendcaseendalways (posedge clock or negedge resetn) begin/ sta

25、te registersif (resetn = 0) beginstate<=sif;endelse beginstate<=next_state;endendendmodule32位帶使能端觸發(fā)器：module dffe32 (d,clk,clrn,e,q);input31:0d;inputclk,clrn,e;output31:0q;reg31:0q;always (negedge clrn or posedge clk)if (clrn = 0) beginq <= 0;endelse beginif(e = 1)q <= d;endendmodule32位觸發(fā)

26、器：module dff32 (d,clk,clrn,q);input31:0d;inputclk,clrn;output31:0q;reg31:0q;always (negedge clrn or posedge clk)if (clrn = 0) beginq <= 0;endelse beginq <= d;endendmoduleALU計(jì)算部件：module alu (a,b,aluc,r,z);input 31:0 a,b;input 3:0 aluc;output 31:0 r;output z;assign r = cal(a,b,aluc);assign z = |

27、r;function 31:0 cal;input 31:0 a,b;input 3:0 aluc;casex (aluc)4'bx000: cal=a+b;4'bx100: cal=a-b;4'bx001: cal=a&b;4'bx101: cal=a|b;4'bx010: cal=ab;4'bx110: cal=b15:0,16'h0;4'bx011: cal=b<<a4:0;4'b0111: cal=b>>a4:0;4'b1111: cal=$signed(b)>>

28、>a4:0;endcaseendfunctionendmodule其他部件：module f (reg_dest,jal,wn);input4:0reg_dest;input jal;output4:0wn;assignwn=reg_dest | 5jal;endmodulemodule sa (di,dot);input 4:0 di;output 31:0 dot;assign dot = 27'b0,di;endmodulemodule out4 (out);output 31:0 out;assign out = 32'h4;endmodulemodule e (

29、immin,sext,immediate,offset);input15:0immin;inputsext;output31:0 immediate,offset;wire e=sext & immin15;wire15:0imm=16e;assignoffset =imm13:0,immin15:0,1'b0,1'b0;assignimmediate= imm,immin15:0;endmodulemodule combine (address,pc,add);input25:0address;input3:0pc;output31:0add;assignadd=pc

30、3:0,address25:0,1'b0,1'b0;endmodulemodule convert1 (dain,sain,op,func,rs,rt,rd,imm,addr);input31:0dain;output4:0sain,rs,rt,rd;output5:0op,func;output15:0imm;output25:0addr;assignsain=dain10:6;assignop=dain31:26;assignfunc=dain5:0;assignrs=dain25:21;assignrt=dain20:16;assignrd=dain15:11;assig

31、nimm=dain15:0;assignaddr=dain25:0;endmodulemodule convert2 (pc,pcout);input31:0pc;output3:0pcout;assignpcout=pc31:28;endmodule七、實(shí)驗(yàn)檢驗(yàn)與測(cè)試 存儲(chǔ)器內(nèi)的測(cè)試數(shù)據(jù)：- Copyright (C) 1991-2013 Altera Corporation- Your use of Altera Corporation's design tools, logic functions - and other software and tools, and its A

32、MPP partner logic - functions, and any output files from any of the foregoing - (including device programming or simulation files), and any - associated documentation or information are expressly subject - to the terms and conditions of the Altera Program License - Subscription Agreement, Altera Meg

33、aCore Function License - Agreement, or other applicable license agreement, including, - without limitation, that your use is for the sole purpose of - programming logic devices manufactured by Altera and sold by - Altera or its authorized distributors. Please refer to the - applicable agreement for

34、further details.- Quartus II generated Memory Initialization File (.mif)DEPTH = 64;%Memory depth and width are required%WIDTH = 32;%Enter a decimal number%ADDRESS_RADIX = HEX;%Address and value radixes are optional%DATA_RADIX = HEX;%Enter BIN, DEC, HEX, or OCT; unless%otherwise specified, radixes =

35、HEX%CONTENT BEGIN0.3F : 00000000;% Range-Every address from 0 to 3F = 00000000% 0 : 3c010000;% (00)main:luir1,0# address of data0% 1 : 34240080;% (04)orir4,r1,0x80# address of data0% 2 : 20050004;% (08)addir5,r0,4# counter% 3 : 0c000018;% (0c)call:jalsum# call function% 4 : ac820000;% (10)swr2,0(r4)

36、# store result% 5 : 8c890000;% (14)lwr9,0(r4)# check sw% 6 : 01244022;% (18)subr8,r9,r4# sub: r8 <- r9 - r4% 7 : 20050003;% (1c)addir5,r0,3# counter% 8 : 20a5ffff;% (20)loop2:addir5,r5,-1# counter - 1% 9 : 34a8ffff;% (24)orir8,r5,0xffff# zero-extend: 0000ffff% A : 39085555;% (28)xorir8,r8,0x5555# zero-extend: 0000aaaa% B : 2009ffff;% (2c)addir9,r0,-1# sign-extend: ffffffff% C : 312affff;% (30)andir10,r9,0xffff# zero-extend: 0000ffff% D : 01493025;% (34)orr6,r10,r9# or: ffffffff% E : 01494026;% (38)xorr8,r10,r9# xor: ffff0000