用FPGA實(shí)現(xiàn)SMPTE協(xié)議,292M,259M等

1、Copyright Lattice Semiconductor 2006 Page-1Lattice ConfidentialCopyright Lattice Semiconductor 2006 Page-2Lattice ConfidentialvBasic Video Overview vBroadcast / Pro. Video StandardsvSDI Video Design and Testing vLattices SDI Solution FPGA with SerDes, IP, Demo Copyright Lattice Semiconductor 2006 Pa

2、ge-3Lattice ConfidentialImagesVideoActiveBlankingBlankingVertical ScanningHorizontal ScanningvVideo is composed of a series of still image framesvVideo spec will includev Image resolutionv Frames per secondv Progressive or Interlacedv Data bits used for each pixelCopyright Lattice Semiconductor 2006

3、 Page-4Lattice ConfidentialVsyncHsyncDER/G/BLine001Line002Line003Line479Line480HsyncPixel(001)R7:0Pixel(002)R7:0Pixel(003)R7:0Pixel(639)R7:0Pixel(640)R7:0Pixel(001)G7:0Pixel(002)G7:0Pixel(003)G7:0Pixel(639)G7:0Pixel(640)G7:0Pixel(001)B7:0Pixel(002)B7:0Pixel(003)B7:0Pixel(639)B7:0Pixel(640)B7:0R7:0G7

4、:0B7:0Pixel ClockDEvVsync : one pulse per framevHsync : one pulse per lineCopyright Lattice Semiconductor 2006 Page-5Lattice ConfidentialvProgressive:vInterlaced:Copyright Lattice Semiconductor 2006 Page-6Lattice ConfidentialvRGB : v Computer system: value range 0 255v Studio equipment: value range

5、16235vYUV :v PAL / NTSC / SECAM compositevYIU : v Derived from YUVv Optionally used by NTSCvYCbCr: (Y=16235, Cb=16240, Cr=16240)v Developed for digital video systemv With different sampling formats (4:4:4, 4:2:2, 4:1:1, 4:2:0)Copyright Lattice Semiconductor 2006 Page-7Lattice Confidential4:4:44:2:2

6、4:1:14:2:0 (MPEG1)4:2:0 (MPEG2, MPEG4)Copyright Lattice Semiconductor 2006 Page-8Lattice ConfidentialvBasic Video Overview vBroadcast / Pro. Video StandardsvSDI Video Design and Testing vLattices SDI Solution FPGA with SerDes, IP, Demo Copyright Lattice Semiconductor 2006 Page-9Lattice Confidentialv

7、Broadcast / Professional video standardsv used in studio, TV broadcasting, film making products including cameras, monitors, switchers, etc.v75 Ohm cablev Connecting systems up to several hundred meters (comparing to several meters of the DVI / HDMI standards).vBit Ratev SD-SDI: 270 Mbpsv HD-SDI: 1.

8、485 Gbpsv 3G-SDI: 3 GbpsCopyright Lattice Semiconductor 2006 Page-10Lattice ConfidentialTotal Resolution (Hx V)Active Resolution (H x V)Progressive or InterlacedAspect RatioFrame Rate (Hz)Sample Rate (MHz)SDTV or HDTVDigital Parallel StandardDigital Serial StandardSerDes Bit RateSupported by ECP2M85

9、8 x 525720 x 480i4 x 329.9713.5SDBT.656 BT.799 SMPTE 125MBT.656 BT.799 SMPTE 259M270 MbpsYes864 x 625720 x 576i4 x 32513.5SDBT.656 BT.799BT.656 BT.799 SMPTE 259M270 MbpsYes1650 x 7501280 x 720p16 x 960/M74.25/MHDSMPTE 274M SMPTE 292M1.485 GbpsYes2200 x 1125 1920 x 1080i16 x 930/M74.25/MHDBT.1120 SMP

10、TE 274MBT.1120 SMPTE 292M1.485 GbpsYes2200 x 1125 1920 x 1080p16 x 930/M74.25/MHDSMPTE 274M SMPTE 292M1.485 GbpsYes2640 x 1125 1920 x 1080p16 x 92574.25HDSMPTE 274M SMPTE 292M1.485 GbpsYes2750 x 1125 1920 x 1080p16 x 924/M74.25/MHDSMPTE 274M SMPTE 292M1.485 GbpsYes2200 x 1125 1920 x 1080p16 x 959.94

11、148.35HDBT.1120 SMPTE 274MSMPTE 424M3GTBD2200 x 1125 1920 x 1080p16 x 960148.5HDBT.1120 SMPTE 274MSMPTE 424M3GTBD2376 x 1250 1920 x 1080i16 x 92574.25HDBT.1120 SMPTE 295MBT.1120 SMPTE 292M1.485 GbpsYes2376 x 1250 1920 x 1080p16 x 950148.5HDBT.1120SMPTE 424M3GTBDCopyright Lattice Semiconductor 2006 P

12、age-11Lattice Confidential720pCopyright Lattice Semiconductor 2006 Page-12Lattice Confidential1080iCopyright Lattice Semiconductor 2006 Page-13Lattice ConfidentialG(x)=x9+x4+13FF000000XYZ200040 2000403FF000000XYZCRCBYY0001CRCBYY2223 CRCBYY7 1 87 1 87 1 87 1 9Y7 1 93FFH = 1E A VS A VH o riz o n ta l

13、B la n k in gH = 01 7 1 6 w o rd s (S D )7 2 0 x 2 = 1 4 4 0 w o rd s3FF000000XYZLN0LN13FF000000XYZCRCBYY0002CRCBYY4446 CRCBYY1 9 1 61 9 1 61 9 1 61 9 1 8Y7 1 93FFH = 1E A VS A VH o riz o n ta l B la n k in gH = 02 2 0 0 w o rd s (H D )1 9 2 0 w o rd s3FF000000XYZLN0LN1CRC3FF000000XYZCRCBYY2213CRCBY

14、Y6657 CRCBYY1 9 1 81 9 1 81 9 1 71 9 1 9Y7 1 93FF 0CRC0CRC1CRC1CRC= x18 +x5 +x4+1Copyright Lattice Semiconductor 2006 Page-14Lattice ConfidentialvP3 = V HvP2 = F HvP1 = F VvP0 = F V H3FF000000XYZCopyright Lattice Semiconductor 2006 Page-15Lattice ConfidentialvBasic Video Overview vBroadcast / Pro. V

15、ideo StandardsvSDI Video Design and Testing vLattices SDI Solution FPGA with SerDes, IP, Demo Copyright Lattice Semiconductor 2006 Page-16Lattice Confidential20 BITS19 BITS1 BIT20 BITSHORIZONTAL ACTIVE LINE ONLYvUse a pathological signalv Stresses the RX equalizer and the PLLv Produces certain strin

16、gs of values at the output of the serializer that require the receiver to work hardervCondition occurs for a complete linev Can occur randomly up to four times in half a fieldVERTICAL BLANKING INTERVALFIRST HALF OF ACTIVE FIELDCb/Cr= 300h, Y=198hFOR CABLE EQUALIZER TESTINGSECOND HALF OF ACTIVE FIELD

17、Cb/Cr= 200h, Y=110hFOR PHASE LOCKED LOOP TESTINGAND INVERSE TOOCopyright Lattice Semiconductor 2006 Page-17Lattice ConfidentialvSMPTE Color Barv Well known pattern for engineer to discern how an NTSC video signal has been alteredv75% Color Barv The top row of the SMPTE Color Bar is a 75% color bar (

18、75% intensity) . In this case, one replaces the lower portion of the SMPTE color bar with the 75% color bar.v In some circumstances, 75% color bar is required, e.g. measurement of the HD-SDI output jitter v Both have 16:9 aspect ratiov100% Color BarCopyright Lattice Semiconductor 2006 Page-18Lattice

19、 Confidentialv TIMING JITTER (SD: 0.2UI, HD: 1.0UI)v The variation in position of a signals transitions occurring at a rate greater than a specified frequency (10 Hz).v ALIGNMENT JITTER (SD: 0.2UI, HD: 0.2UI)v The variation in position of a signals transitions relative to those of a clock extracted

20、from that signal. The bandwidth of the clock extraction process determines the low-frequency limit for alignment jitterv Alignment jitter is the variation in the data transitions relative to a recovered clock, and timing jitter is the variation in the edge transitions of the recovered clock relative

21、 to a stable clock.Copyright Lattice Semiconductor 2006 Page-19Lattice ConfidentialVsyncHsyncVsyncHsyncVsyncHsyncClockGenerator #1148.499999MHz148.500001MHzClockGenerator #2FVH148.499999MHz148.500001MHz148.5MHzCopyright Lattice Semiconductor 2006 Page-20Lattice ConfidentialvBasic Video Overview vBro

22、adcast / Pro. Video StandardsvSDI Video Design and Testing vLattices SDI Solution FPGA with SerDes, IP, Demo Copyright Lattice Semiconductor 2006 Page-21Lattice ConfidentialvSupport for automatic RX rate detectionvRate Control & Word Alignment only necessary when multi-rate operation is desiredL

23、atticeECP2MSMPTE-259 M /292 MGS4511Clock Generator27 MHzOSCGS4915Clock CleanerRX Ref ClockRate ControlSERDESWord Alignment/TRS DetectMulti-rate IP from LatticeDecoderCopyright Lattice Semiconductor 2006 Page-22Lattice Confidentialv Other existing FPGA devices also require jitter mitigation when conn

24、ecting the recovered clock from the RX to the TX despite their higher cost.v In above example, the jitter was attenuated by Gennums GS4915 when the asynchronous re-timing FIFO data read used a low jitter clock.SERDESSERDESLatticeECP2MSMPTE-259 M /292 MSMPTE-259 M /292 MGS4511Clock Generator27 MHzOSC

25、GS4915Clock CleanerWord Alignment/TRS DetectRate ControlDecoderTX ChannelRX ChannelRetimingFIFOWCLK RCLKTX Ref ClockVideo Data from the FabricHigh Jitter ClockMulti-rate IP from LatticeCopyright Lattice Semiconductor 2006 Page-23Lattice ConfidentialvKey FeaturesvSupport for dynamic multi-rate SD-SDI

26、/HD-SDI (SMPTE 259 and SMPTE 292) interfaces.vSupport for automatic RX rate detection and dynamic TX rate selectionvSupport for SD source formats: SMPTE 125M and SMPTE 267M (13.5 MHz only)vSupport for HD source formats: SMPTE 260M, SMPTE 274M, SMPTE 295M and SMPTE 296MvWord alignment, TRS detection

27、and F/V/H identificationvCRC computation, error detection and insertion for HDvLN decoding/encoding for HD SERDESDescrambler/ decoderWordalignment/TRS detectScrambler/encoderEAV/SAV/LN insertSDI inSDI outCRCcheckCRCinsertionpdoutpdincrc_errorhd/sdtrslnRatecontrolSCI controlClockgeneratorsTx Ref ClkR

28、x Ref ClkSCICopyright Lattice Semiconductor 2006 Page-24Lattice ConfidentialvThe video pass-through demo has two modes: video pass-through mode and color bar mode.vIn the color bar mode, the user is free to switch between video formats.Multi-rate SDI Tx/RxIP CoreMUXSMPTEVideoInputSMPTEVideoOutputCol

29、or Bars GenerationControlsCopyright Lattice Semiconductor 2006 Page-25Lattice ConfidentialCopyright Lattice Semiconductor 2006 Page-26Lattice ConfidentialCopyright Lattice Semiconductor 2006 Page-27Lattice ConfidentialCopyright Lattice Semiconductor 2006 Page-28Lattice ConfidentialLatticesMulti-rate

30、SDI Tx/RxIP CoreMUXColor Bars GenerationControlsSMPTEVideoOutputSMPTEVideoInputC/B/H/SAdjustmentCopyright Lattice Semiconductor 2006 Page-29Lattice ConfidentialCopyright Lattice Semiconductor 2006 Page-30Lattice ConfidentialCopyright Lattice Semiconductor 2006 Page-31Lattice ConfidentialCopyright La

31、ttice Semiconductor 2006 Page-32Lattice ConfidentialCopyright Lattice Semiconductor 2006 Page-33Lattice ConfidentialSDI_PHY.ngoThis is the netlist file of the generated core.SDI_PHY_bb.vThis is the file that should be imported to the ispLEVER project.SDI_PHY_inst.vDo not use this file.SDI_PHY_top.vT

32、his is the file that has the correct instantiation of the core.You can implement your design by either of the following two ways.(1) Use this file as the design top level and put in your other codes.(2) Copy the core instantiation code into your top level file.Copyright Lattice Semiconductor 2006 Pa

33、ge-34Lattice Confidentialpdo_clkvblankpd_outln_outfieldprevious line numberx3FF000000XYZLN0LN1CR0CR1d1trs_outhblankLatency is around 15 cyclesRx inputstreamx3FF000000XYZLN0LN1CR0CR1d1current line numberd2d3d2crc_errorCopyright Lattice Semiconductor 2006 Page-35Lattice ConfidentialHD-SDI YCbCr 4:2:2 to 4:4:4 ConvertionDFFDFFDFFDFFY1Cr0DFFDFFY2Cb2DFFDFFY3Cr2DFFDFFY0Cb0pd_in_delay1pd_in_delay2pd_in_delay3pd_in_delay4hd_Y_inhd_Cb_inhd_Cr_inpd_in19:10pd_in9:0pd_in_delay