實(shí)驗(yàn)五-數(shù)字時(shí)鐘的設(shè)計(jì)

1、 實(shí)驗(yàn)五 數(shù)字時(shí)鐘的設(shè)計(jì)實(shí)驗(yàn)性質(zhì)：綜合性 實(shí)驗(yàn)級(jí)別： 開(kāi)課單位：信息與通信工程學(xué)院通信工程系 學(xué)時(shí)：4學(xué)時(shí)一、實(shí)驗(yàn)?zāi)康模?、學(xué)習(xí)用VHDL語(yǔ)言實(shí)現(xiàn)比較大型的電路的方法。 2、繼續(xù)鞏固cpld技術(shù)層次化設(shè)計(jì)方法。二、實(shí)驗(yàn)器材：計(jì)算機(jī)、Quartus II軟件三、實(shí)驗(yàn)內(nèi)容：設(shè)計(jì)一數(shù)字時(shí)鐘，要求具有時(shí)、分、秒、計(jì)數(shù)顯示功能，以24小時(shí)循環(huán)計(jì)時(shí)；具有清零，調(diào)節(jié)小時(shí)，分鐘功能；具有整點(diǎn)報(bào)時(shí)功能。四、實(shí)驗(yàn)步驟：1、根據(jù)電路特點(diǎn)，用層次設(shè)計(jì)的概念，將此任務(wù)分成若干模塊，規(guī)定每一模塊的功能和各模塊之間的接口。讓幾個(gè)學(xué)生分作和調(diào)試其中之一，然后再將各模塊合起來(lái)聯(lián)試。以培養(yǎng)學(xué)生之間的合作精神，同時(shí)加深層次化設(shè)計(jì)概

2、念。2、了解軟件的元件管理深層含義，以及模塊元件之間的連接概念，對(duì)于不同目錄下的同一設(shè)計(jì)，如何融合。3、模塊說(shuō)明： 各種進(jìn)制的計(jì)數(shù)及時(shí)鐘控制模塊（10進(jìn)制、6進(jìn)制、24進(jìn)制） 掃描分時(shí)顯示，譯碼模塊 各模塊都用VHDL語(yǔ)言編寫(xiě)五、實(shí)驗(yàn)?zāi)K：秒模塊LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY second ISPORT(clk, reset,setmin : INSTD_LOGIC;enmin : OUTSTD_LOGIC;da0out: out std_logic_vector (

3、6 downto 0);END entity second;ARCHITECTURE fun OF second ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);BEGIN da0out = count; process ( clk , reset , setmin) begin - enmin=k; if (reset=0) then count = 0000000; elsif (setmin=0) then enmin = clk; elsif (clk event and clk=1) then if (count(3 downto 0)=1

4、001) then if (count 16#60#) then if (count=1011001) then enmin=1; count=0000000; ELSE count=count+7; end if; else count=0000000; end if; elsif (count 16#60#) then count = count+1; enmin=0 after 100 ns; else count=0000000; end if; end if; end process;END fun;分析： 脈沖從0計(jì)數(shù)至59，向前進(jìn)1，enmin由低電平變至高電平。分模塊LIBRA

5、RY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY minute ISPORT(clk, reset,sethour : INSTD_LOGIC;enhour : OUTSTD_LOGIC;da1out: out std_logic_vector (6 downto 0);END entity minute;ARCHITECTURE fun OF minute ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);BEGIN da1out = count; p

6、rocess ( clk , reset , sethour) begin - enmin=k; if (reset=0) then count = 0000000; elsif (sethour=0) then enhour = clk; elsif (clk event and clk=1) then if (count(3 downto 0)=1001) then if (count 16#60#) then if (count=1011001) then enhour=1; count=0000000; ELSE count=count+7; end if; else count=00

7、00000; end if; elsif (count 16#60#) then count = count+1; enhour=0 after 100 ns; else count=0000000; end if; end if; end process;END fun;分析： 脈沖從0計(jì)數(shù)至59，向前進(jìn)1，enhour由低電平變至高電平。時(shí)模塊LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY hour ISPORT(clk, reset,setweek : INSTD_LOGIC;

8、enweek : OUTSTD_LOGIC;da2out: out std_logic_vector (6 downto 0);END entity hour ;ARCHITECTURE fun OF hour ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);BEGIN da2out = count; process ( clk , reset , setweek) begin - enmin=k; if (reset=0) then count = 0000000; elsif (setweek=0) then enweek = clk; elsi

9、f (clk event and clk=1) then if (count(3 downto 0)=1001) then if (count 16#23#) then if (count=00100011) then enweek=1; count=0000000; ELSE count=count+7; end if; else count=0000000; end if; elsif (count 16#23#) then count = count+1; enweek=0 after 100 ns; else countyyyyyyyyyyyyyyyyyyyyyy=0000000; e

10、nd case; end process; end beh;分析： 將8421BCD碼轉(zhuǎn)化成7段碼。 整點(diǎn)報(bào)時(shí)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity speaker is port(clk:in std_logic; speaksec:in std_logic_vector(6 downto 0); speakmin:in std_logic_vector(6 downto 0); speak:out std_logic);end entity speaker;archite

11、cture fun of speaker isbeginprocess(clk,speakmin)begin if(clk event and clk=1)then if(speakmin=0000000 and speaksec=0000000)then speak=1;else speak=0;end if; end if;end process;end fun;分析： 當(dāng)時(shí)鐘計(jì)數(shù)到整點(diǎn)，即秒和分都等于0時(shí)蜂鳴器報(bào)警，以實(shí)現(xiàn)整點(diǎn)報(bào)時(shí)功能。輸入：clk計(jì)數(shù)時(shí)鐘信號(hào)，speaksec秒輸出信號(hào)，speakmin分輸出信號(hào)輸出：報(bào)警信號(hào)輸出轉(zhuǎn)換模塊六轉(zhuǎn)一library IEEE;use IEEE

12、.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity sixtozero is Port ( d:in std_logic_vector(6 dow

13、nto 0); out6 : out std_logic; out5 : out std_logic; out4 : out std_logic; out3 : out std_logic; out2 : out std_logic; out1 : out std_logic; out0 : out std_logic); end sixtozero;architecture Behavioral of sixtozero isbeginprocess(d)Beginout6=d(6);out5=d(5); out4=d(4); out3=d(3); out2=d(2); out1=d(1);

14、 out0=d(0);end process;end Behavioral;二轉(zhuǎn)一library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VCompone

15、nts.all;entity twotozero is Port ( d:in std_logic_vector(2 downto 0); out2 : out std_logic; out1 : out std_logic; out0 : out std_logic);end twotozero;architecture Behavioral of twotozero isbeginprocess(d)begin out2=d(2); out1=d(1); out0=d(0);end process;end Behavioral;3.三轉(zhuǎn)一library IEEE;use IEEE.STD_

16、LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity tretozero is Port ( d:in std_logic_vector(6 downto 0); out3 : out std_logic; out2 : out std_logic; out1 : out std_logic; out0 : out std_logic); end tretozero;architecture Behavioral of