數(shù)字邏輯設計及應用教學課件：6-6 比較器 全加器

1、REVIEW OF LAST CLASS譯碼器編碼器三態(tài)器件多路復用器奇偶校驗器比較器加減器 標準MSI多路復用器 74x151、 74x153、74x157 擴展多路復用器 利用多路復用器實現(xiàn)邏輯函數(shù) 多路分配器 利用帶使能端的譯碼器 使能端作為數(shù)據(jù)輸入端REVIEW OF LAST CLASS譯碼器編碼器三態(tài)器件多路復用器奇偶校驗器比較器加減器 奇校驗：輸入有奇數(shù)個1，輸出為1 偶校驗：輸入有偶數(shù)個1，輸出為1 利用異或運算實現(xiàn) 9位奇偶發(fā)生器74x280 奇偶校驗的應用 檢測代碼在傳輸和存儲 過程中是否出現(xiàn)差錯。5.8.2 奇偶校驗電路什么是奇偶校驗?奇偶校驗位+一組信號位基本定理：基本

2、概念：使所有的1加起來為偶數(shù)或奇數(shù),來檢測系統(tǒng)的方法稱為奇偶校驗法。A0 A1 An = 1 變量為1的個數(shù)是奇數(shù)0 變量為1的個數(shù)是偶數(shù)奇校驗電路（odd-parity circuit）如果輸入有奇數(shù)個1，則輸出為1。偶校驗電路（even-parity circuit）如果輸入有偶數(shù)個1，則輸出為1。I1I2I3I4INODD菊花鏈式連接I1I2I3I4IMINODD樹狀連接奇校驗電路的輸出反相就得到偶校驗電路9位奇偶校驗發(fā)生器74x280（P291 圖575）ABCDEFGHIEVENODD74x280偶數(shù)個1時輸出為1奇數(shù)個1時輸出為1Answer key of Home work P5

3、15- 6.666.66 Show how to realize the 4-input, 18-bit multiplexer with the functionality of Table 6-46 using 9 74x153s and a “code converter” with inputs S2S0 and outputs C1,C0 such that C1,C0 = 0011 when S2S0 selects A-B-D-C, respectively. 0001001100100001C1C01D02D0123917D018D03D04D05D06D01Y2Y3Y4Y5Y

4、6Y17Y18YS2S1S0code converterC1C0BA6.67 Design a 3-input, 2-output combinational circuit that performs the code conversion specified in the previous exercise, using discrete gates. Answer key of Home work P515- 6.67S2S1S0code converterC1C00001001100100001C1C0USE karnaugh map !6.9 Comparators（比較器）6.10

5、 Adders, Subtractors, and ALUs(加減器和算術邏輯單元)6.9 comparator（比較器）(P458)比較2個二進制數(shù)值并指示其是否相等的電路等值比較器：檢驗數(shù)值是否相等數(shù)值比較器：比較數(shù)值的大?。?=,B（A=1, B=0）則 AB=1 可作為輸出信號 AB3)LT = EQ GT = ( EQ + GT )或 (A3 = B3) (A2 = B2) (A1B1)或 (A3 = B3)(A2 = B2)(A1 = B1) (A0B0)或 (A3 = B3) (A2B2)A3 B3A2 B2A1 B1A0 B0+輸出高有效!74x856.9.4 Standard

6、 MSI Comparatorsthe 74x85 4-bit comparator A0A1A2A3ALTBINAEQBINAGTBIN級聯(lián)輸入，用于擴展ALTBOUT = (AB高位A高位=B高位 & A低位B低位ABAEQBOUT = (A=B)AEQBINAGTBOUT = (AB) + (A=B)AGTBIN74X85Serial Expanding Comparators(比較器的串行擴展)XD11:0YD11:03:07:411:8XY+5VABIABOA0A3B0B374x85ABIABOA0A3B0B374x85ABIABOA0A3B0B374x853片74x85構成12位比

7、較器低位高位Digital Logic Design and Application (數(shù)字邏輯設計及應用)8-bit comparator 74x682 (P463)P0P1P2P3P4P5P6P78-bit comparator 74x682(P463)問題1：怎樣用輸出來表示下列條件？ DIFF高電平有效：P DIFF Q EQ高電平有效：P EQ Q GE高電平有效：P GE Q LT高電平有效：P LT Q （P463 Figure 6-80）GELT問題2：能否擴展？注意：沒有級聯(lián)輸入端3片74x682構成24位比較器P0P7 P=QQ0Q7 PQP0P7 P=QQ0Q7 PQP0

8、P7 P=QQ0Q7 PQ7:015:823:16P23:0Q23:0PEQQPGTQParalel Expanding Comparators(比較器的并行擴展)exercise Design a circuit to compare three 4-bit binary numbers A(a3a2a1a0), B(b3b2b1b0), C(c3c2c1c0) with two 4-bit comparators 74X85. You need to give three outputs: Fequal, FAmax, FAmin. Fequal =1 indicates A=B=C; F

9、Amax =1 indicates A is the biggest one among them; FAmin =1 indicates A is the smallest one among them. Show your work. (You can finish your design with some other gates you think necessary. ) 6.10 Adders, Subtractors, and ALUs (加減器和算術邏輯單元) (P471)6.10.1 half adders and full adders 半加器和 全加器 (P474)概念：

10、能對兩個1位二進制數(shù)進行相加而求得和及進位的邏輯電路稱為半加器。概念：能對兩個1位二進制數(shù)進行相加并考慮低位來的進位，即相當于3個1位二進制數(shù)相加，求得和及進位的邏輯電路稱為全加器。 SCOXYCIS = X Y CIXY00100111CIXY00 01 11 1001COXCICO = + +YCI= XY + (X+Y)CI0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1CIXYSCO全加器真值表6.10.2 Ripple Adders串行進位加法器缺點：運算速度慢，有較大的傳輸延遲tADD

11、= tXYCout + (n-2)*tCinCout + tCinSX YCI COSX YCI COSX YCI COSX YCI COSC1C2C3C4C0S0S1S2S3X0 Y0X1 Y1X2 Y2X3 Y3=0回顧：串行比較器 提高速度：并行加法器X YCI COSX YCI COSX YCI COSX YCI COSC1C2C3C4C0S0S1S2S3X0 Y0X1 Y1X2 Y2X3 Y3X YCMPEQI EQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11X YCMPEQI EQOX YCMPEQI EQO串行比較器串行加法器主 輸 入主 輸 出邊界輸入邊界輸

12、出級聯(lián)輸出迭代電路（iterative circuit）Iterative：重復的, 反復的, 數(shù)迭代的PICI COPOPICI COPOPICI COPOC0C1C2CnPO0PO1POn-1主 輸 出PI0PI1PIn-1主 輸 入邊界輸入邊界輸出級聯(lián)輸出P297一位全加器：S = X Y CiCi+1 = XY + (X+Y)Ci6.10.4 Carry Lookahead Adders并行進位加法器超前進位法：第 i 位的進位輸入信號可以由該位以前的各位狀態(tài)決定。Ci+1 = (XiYi) + (Xi+Yi) Ci= Gi + Pi Ci進位產(chǎn)生信號進位傳遞信號0 0 0 0 00

13、0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1CiXYSCi+1全加器真值表6.10.4 Carry Lookahead Adders并行進位加法器Ci+1 = (XiYi) + (Xi+Yi) Ci= Gi + Pi Ci進位產(chǎn)生信號進位傳遞信號6.10.5 MSI Adders(P479 )6.10.6 MSI Arithmetic and Logic Units (ALU, MSI 算術邏輯單元)Perform any of a number of different arithmetic and logical

14、 operations on a pair of b-bit operands.(對2個b位的操作數(shù)進行若干不同的算術和邏輯運算)S0S3MCINA0A3B0B3GPF0F3COUTA=B74x181輸入數(shù)據(jù)輸出數(shù)據(jù)0算術/1邏輯選擇特定操作P483 Table 6-7074x181 (P483)2 examples of 74x148.Answer key of homework6.52 Draw the logic diagram for a circuit that uses the 74x148 to resolve priority among eight active-high i

15、nputs, I0I7, where I7 has the highest priority. The circuit should produce active-high address outputs A2A0 to indicate the number of the highest-priority asserted input. If no input is asserted, then A2A0 should be 111 and an IDLE output should be asserted. You may use discrete gates in addition to

16、 the 148. Be sure to name all signals with the proper active levels. 設計判定優(yōu)先級電路：（利用74x148 ） 8個輸入I0I7高電平有效，I7優(yōu)先級最高 地址輸出A2A0，高電平有效 如果沒有輸入有效，輸出為000且輸出IDLE=1有效I7I0A2A1A0IDLEA2A1A0GSEOEII7I074x148若沒有輸入有效，地址輸出為111且輸出IDLE=1有效,電路需變化.見下頁!設計判定優(yōu)先級電路：（利用74x148 ） 8個輸入I0I7高電平有效，I7優(yōu)先級最高 地址輸出A2A0，高電平有效 如果沒有輸入有效，地址輸出

17、為111且輸出IDLE=1有效I7I0A2A1A0GSEOEII7I074x148P514 6.52A2A1A0IDLEAnswer key of homework6.53 Draw the logic diagram for a circuit that resolves priority among eight active-low inputs, I0_LI7_L, where I0_L has the highest priority. The circuit should produce active-high address outputs A2A0 to indicate the number of the highest-priority asserted input. If at least one input is asserted, then an AVALID output should be asserted. Be sure to na