嵌入式軟件系統(tǒng)設(shè)計(jì)：09_processor_pipeline

1、1Embedded System Architecture lecture 09-Processor(1)_stagesJun WANG2ContentsOperation fieldStorage and accessOperationsTop-view and block diagramVerilog for stagesDesign targetRISC CPUData path 16bData memory28 X 16bOperation memory:28 X 16bSize of operation set: 25General register8 X 16bFlagsNF, Z

2、F, CFControl Clock, reset, enable, startTesting4 bit selection for 16 bit output34Operation field5Access memory and registerAccess register:Ex. grr1, r1 for simplificationr1/r1gets register numberAccess memory:Ex. mr2+val3, r2+val3/gr(r2)+val3 gets address of memoryAccess immediate data:Ex. val2, va

3、l3,MSB: val2, LSB:val3An example of operation codes (assemble language) LOAD gr1, gr0, 0LOAD gr2, gr0, 1NOPNOPNOPADD gr3, gr1, gr2NOPNOPNOPSTORE gr3, gr0, 2HALT6In C code:Y = A + BMgr0+2 =Mgr0+1+Mgr0+07OperationData transfer & Arithmeticmnemonicoperand1operand2operand3op codeoperationNOP *00000no op

4、erationHALT *00001haltLOAD *r1r2val300010grr1-mr2+val3STORE *r1r2val300011mr2+val3-r1LDIHr1val2val310000r1-r1+val2, val3, 0000_0000 (lower 8b0 can be given with ADDI)ADD *r1r2r301000r1-r2+r3ADDIr1val2val301001r1-r1+val2, val3ADDCr1r2r310001r1-r2+r3+CFSUBSUBISUBCCMP *r2r301100r2-r3; set CF,ZF and NF*

5、: operations have been implemented in the following verilog8OperationLogical / shiftmnemonicoperand 1operand2operand3op codeoperationANDr1r2r301101r1-r2 and r3ORXORSLLr1r2val300100r1-r2 shift left logical (val3 bit shift)SRLSLAr1r2val300101r1-r2 shift left arithmetical (val3 bit shift)SRALogical shi

6、ft: 1001 SRL 2b 0010 (append 0)Arithmetical shift: 1001 SRA 2b 1110 (keep the sign)9OperationControlmnemonicoperand 1operand2operand3op codeoperationJUMPval2val311000jump to val2, val3JMPRr1val2val311001jump to r1+val2, val3BZ *r1val2val311010if ZF=1 branch to r1+val2, val3BNZr1val2val311011if ZF=0

7、branch to r1+val2, val3BN *r1val2val311100if NF=1 branch to r1+val2, val3BNNBCr1val2val311110if CF=1 branch to r1+val2, val3BNCFlag registers: -Used for control operations (conditional branch) -ZF (zero flag), NF (negative flag), CF (carry flag)10Block diagramsmdr: data for save memory directly Use

8、LOAD, STORE, ADD, BZ to help you understand this graph11Top view12StorageOutside CPUInstruction storageInstruction memory (25 X 16b)Data storageData memory (28 X 16b)Inside CPUInstruction storageStage instruction registersid_ir(16b x1), ex_ir (16b x 1), mem_ir (16b x 1), wb_ir (16b x 1)Data storageG

9、eneral registersStorage for operand data (23 X 16b) Stage data registers ID: reg_A (16b x 1), reg_B (16b x 1), smdr (16b x 1), EX : reg_C (16b x 1), flag (1b x3), dw (1b x1), smdr1 (16b x 1), WB: reg_C1 (16b x 1)13CPU control14IF15IDoperand1: r1operand2: r2operand3: r3operand2,3: val2+val3operand3:

10、val3reg_A: 1st input operand of ALU, always grreg_B: 2nd input operand of ALU, gr or valsmdr: used only for STORE Note latch!EXNote latch !MEMWBNote latch !Example of test pattern (texture simulation)LOAD gr1, gr0, 0LOAD gr2, gr0, 1NOPNOPNOPADD gr3, gr1, gr2NOPNOPNOPSTORE gr3, gr0, 2HALTSimulation r

11、esults (texture)Please test by yourself, and analyse itLOAD gr1, gr0, 0LOAD gr2, gr0, 1NOPNOPNOPADD gr3, gr1, gr2NOPNOPNOPSTORE gr3, gr0, 2HALTresetLabs1, Complete the designs aboveComplete the verilog with variable declarationsSimulate by the test pattern (texture simulation)2, Add more to your ver

12、ilogComplete the left operations other than * onesLDIH, ADDI,ADDC, Add flag registerCFAdd your original operationsYou can add up to 5 ops with unused codes: 10011, 10100, 10101, 10110, 10111.Design you own test patternsSubmit your report due to Dec 18thYour own operation set description (like the ta

13、ble in slide#7/8/9), verilog, testbenchsnapshot of simulation (texture only), RTL snapshots, design report (timing/area/power). Note: no board verificationImpression (感想) on this projectHazardsSituations that prevent starting the next instruction in the next cycleStructure hazardsA required resource

14、 is busyData hazardNeed to wait for previous instruction to complete its data read/writeControl hazardDeciding on control action depends on previous instructionStructure HazardsConflict for use of a resourceIn X86（by intel） pipeline with a single memoryLoad/store requires data accessInstruction fetch would have to stall for that cycleWould cause a pipeline “bubble”So called von Neumann structureIn ARM/MIPS pipelineseparate instruction/data cachesSo called von Harvard structureData HazardsAn instruction depends on completion o