基于FPGA數(shù)字秒表設(shè)計(jì)

1、數(shù)字秒表設(shè)計(jì)一、實(shí)驗(yàn)?zāi)康?、理解計(jì)時(shí)器的原理與Verilog/VHDL的編程方法；2、掌握多模塊設(shè)計(jì)及層次設(shè)計(jì)的方法。二、實(shí)驗(yàn)原理秒計(jì)時(shí)器是由計(jì)數(shù)器和譯碼器、顯示器組成，其核心是計(jì)數(shù)器與譯碼器。60秒計(jì)時(shí)器可由二個(gè)計(jì)數(shù)器分別完成：個(gè)位為十進(jìn)制計(jì)數(shù)器，十位為6進(jìn)制計(jì)數(shù)。個(gè)位計(jì)數(shù)器的計(jì)數(shù)信號(hào)由實(shí)驗(yàn)開(kāi)發(fā)板上主頻20MHZ分頻產(chǎn)生的1Hz時(shí)鐘信號(hào)提供,十位計(jì)數(shù)器的計(jì)數(shù)信號(hào)由個(gè)位的進(jìn)位信號(hào)提供。然后由譯碼器對(duì)計(jì)數(shù)結(jié)果進(jìn)行譯碼，送LED數(shù)碼管進(jìn)行顯示。Clr為清零，set為開(kāi)始。三、實(shí)驗(yàn)框圖圖2-1四、實(shí)驗(yàn)任務(wù)1、采用層次設(shè)計(jì)的方法，設(shè)計(jì)一個(gè)包括頂層及底層模塊的60秒計(jì)時(shí)器，底層模塊用Verilog/VH

2、DL設(shè)計(jì)（或者選用原理圖輸入法中宏功能元件），頂層用原理圖設(shè)計(jì)。2、秒計(jì)時(shí)器應(yīng)當(dāng)具有系統(tǒng)復(fù)位功能；3、每十秒發(fā)出提示信號(hào)及計(jì)滿60秒時(shí)發(fā)出報(bào)警信號(hào)。（選做）五、程序源代碼：文件名COUNT10.V代碼moduleCOUNT10(SET,CLR,CLK,DOUT,COUT);inputSET,CLR,CLK;output3:0DOUT;outputCOUT;reg3:0data;regCOUT;assignDOUT=data;always(negedgeCLKornegedgeCLR)beginif(!CLR)data=0;elseif(!SET)data=0;elseif(data9)data

3、=data+1;elsedata=4hO;endalways(data)beginif(data=4h9)COUT=lbl;elseCOUT=1b0;endendmodule文件名COUNT6.V代碼moduleCOUNT6(SET,CLR,CLK,DOUT,COUT);inputSET,CLR,CLK;output3:0DOUT;outputCOUT;reg3:0data;regCOUT;assignDOUT=data;always(negedgeCLKornegedgeCLR)beginif(!CLR)data=0;elseif(!SET)data=0;elseif(data5)data=

4、data+1;elsedata=4h0;endalways(data)beginif(data=4h5)COUT=1b1;elseCOUT=1bO;endendmodule文件名FrequenceDivider20Mto1.v代碼moduleFrequencyDivider_20M_to_1(CLKIn,CLKOut);inputCLKIn;outputCLKOut;reg24:0data=0;regCOUT;assignCLKOut=COUT;always(posedgeCLKIn)beginif(data1)data=data+1;elsebegindata=25h0;COUT=COUT;

5、endendendmodule文件名LED10.v代碼moduleLED10(a,Q);input3:0a;output6:0Q;reg6:0Q;always(a)begincase(a)4H0:Qv=7H3F;4H1:Q=7H06;4H2:Q=7H5B;4H3:Q=7H4F;4H4:Qv=7H66;4H5:Q=7H6D;4H6:Q=7H7D;4H7:Q=7H07;4H8:Q=7H7F;4H9:Q=7H6F;4HA:Q=7H77;4HB:Q=7H7C;4HC:Q=7H39;4HD:Q=7H5E;4HE:Q=7H79;4HF:Qv=7H71;default:Q=7B1111111;endcase

6、endendmodule文件名圖rm文件名圖rm理COUNT60.bdf2.2.選擇目標(biāo)器件五、實(shí)驗(yàn)步驟1.創(chuàng)建工程3.編寫veriloghdl程序4.編譯生成符號(hào)文件創(chuàng)建編輯原理圖設(shè)置頂層文件8.編譯9.創(chuàng)建編輯波形圖文件10.使用波形圖仿真11.鎖定管腳12.編譯13.下載至芯片六、實(shí)驗(yàn)結(jié)果1.編譯結(jié)果FlowStatusQurtusIIVersionFlowStatusQurtusIIVersionRevisionNameTopi亡”亡IEntityNameFamilyDeviceTimingModelsMettimingrequirementsTotallogicelemeiitgTo

7、talGQmbinstinlfunctionsDedicatedlogicregistersTotalregistersTotalpinsTotalvirtualpinsTotalmemorybitsEmbeddedMultiplier9-bitelementsTotalPLLsSuccessfLl-SatNov011112:49301491Build22210/21/20D&SJWebEditionCOUNTScdunCdcneIIIEP3C5E144CSFinalN/A1X62/5L1M(1%)33/5i1361葦33D/4Z3.9360)0/2(0%)NameNameValuei17.W

8、i匚LKHD-1CLHH1呻2SETHICOUTHOEDOUTHD2.仿真結(jié)果COUNT6.VCOUNT10.V文件名文件名仿真結(jié)果jninrLnrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLrLTLn2.仿真結(jié)果COUNT6.VCOUNT10.V文件名文件名仿真結(jié)果dgxnZXD3XEXZOffiKZCZgZZDgXDBSig)ffitgXDgXngXDgXD3Xgro(ng)C胞COUNT60.V（為了簡(jiǎn)便將分頻器設(shè)置2分頻的）兩DOLTTaDOUTL仿真結(jié)果文件名仿真結(jié)果2XD2XDKD(DCZD(DCTDCCOUNT60.V（為了簡(jiǎn)便將分頻器設(shè)置2分頻的）兩DOLTTa