數(shù)字邏輯電路設(shè)計(jì)

PAGEPAGE14數(shù)字邏輯電路設(shè)計(jì)——-——數(shù)字鐘學(xué)院：京江學(xué)院專業(yè)：軟件工程姓名：李永樂學(xué)號(hào)：4131169055指導(dǎo)老師：趙念強(qiáng)201設(shè)計(jì)任務(wù)及要求(1)擁有正常的時(shí)、分、秒計(jì)時(shí)功能。(2)能利用實(shí)驗(yàn)箱的開關(guān)實(shí)現(xiàn)校時(shí)、校分及清零功能。(3)能利用實(shí)驗(yàn)板上的揚(yáng)聲器做整點(diǎn)報(bào)時(shí)。(4)采用VHDL語言或畫圖方法進(jìn)行設(shè)計(jì)。(5)在完成全部電路設(shè)計(jì)后下載到實(shí)驗(yàn)箱，驗(yàn)證設(shè)計(jì)課題的正確性。多功能數(shù)字鐘的總體設(shè)計(jì)和頂層原理圖整個(gè)系統(tǒng)分為五個(gè)模塊來實(shí)現(xiàn)，分別是計(jì)時(shí)模塊、校時(shí)模塊、整點(diǎn)報(bào)時(shí)模塊、分頻模塊、動(dòng)態(tài)顯示模塊。1計(jì)時(shí)模塊1).計(jì)時(shí)——24進(jìn)制計(jì)數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt24isport(clk:instd_logic;ql:outstd_logic_vector(3downto0);qh:outstd_logic_vector(3downto0);c:outstd_logic);endcnt24;architectureoneofcnt24isbeginprocess(clk)variableqi:std_logic_vector(7downto4);variableqj:std_logic_vector(3downto0);beginif(clk'eventandclk='0')thenif(qi="0010"ANDqj="0011")thenc<='1';qi:="0000";qj:="0000";elsec<='0';qj:=qj+1;if(qj<9)thenqj:=qj+1;elseqj:="0000";if(qi<2)thenqi:=qi+1;elseqi:="0000";endif;endif;endif;endif;qh<=qi;ql<=qj;endprocess;endone;2).計(jì)分計(jì)秒——60進(jìn)制計(jì)數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt60isport(clk:instd_logic;clr:instd_logic;ql:bufferstd_logic_vector(3downto0);qh:bufferstd_logic_vector(3downto0);c:outstd_logic);endcnt60;architectureoneofcnt60isbeginc<='1'when(qh="0101"andql="1001")else'0';process(clk,clr)variableqi:std_logic_vector(7downto4);variableqj:std_logic_vector(3downto0);beginif(clr='0')thenqi:="0000";qj:="0000";elsif(clk'eventandclk='1')thenif(qj<9)thenqj:=qj+1;elseqj:="0000";if(qi<5)thenqi:=qi+1;elseqi:="0000";endif;endif;endif;ql<=qj;qh<=qi;endprocess;endone;2校時(shí)模塊1）.選擇計(jì)時(shí)或校時(shí)——2路選擇器（計(jì)時(shí)采用1HZ的脈沖驅(qū)動(dòng)計(jì)數(shù)器計(jì)數(shù)，而校時(shí)則需要較高頻率的信號(hào)驅(qū)動(dòng)以達(dá)到快速校時(shí)的目的）libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymux2_1isport(a,b,s:instd_logic;y:outstd_logic);endmux2_1;architecturebhvofmux2_1isbeginy<=awhens='0'elseb;endbhv;.利用按鍵實(shí)現(xiàn)“校時(shí)”、“校分”和“秒清0”功能（（1)SA：校時(shí)鍵。按下SA鍵時(shí)，時(shí)計(jì)數(shù)器迅速遞增，按24小時(shí)循環(huán)，并且計(jì)滿23時(shí)回到00。（2)SB：校分鍵。按下SB鍵時(shí)，分計(jì)數(shù)器迅速遞增，按60小時(shí)循環(huán)，并且計(jì)滿59時(shí)回到00，但不向時(shí)進(jìn)位。（3)SC：秒清零。按下SC時(shí)，秒計(jì)數(shù)器清零。3分頻模塊這個(gè)系統(tǒng)需要很多種不同頻率的脈沖信號(hào)，這些均可以通過一個(gè)基準(zhǔn)頻率分頻器生成。分頻器就是一個(gè)進(jìn)制很大的計(jì)數(shù)器，利用計(jì)數(shù)器的分頻功能，從不同的輸出位得到所需要的脈沖信號(hào)。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfreqdividerisport(clk:instd_logic; hz512,hz64,hz4,hz1:outstd_logic);endfreqdivider;architecturefoffreqdividerissignalcc:std_logic_vector(9downto0);beginprocess(clk)beginif(clk'eventandclk='1')thenif(cc="1111111111")thencc<="0000000000";elsecc<=cc+1;endif;endif;endprocess;hz512<=cc(0);hz64<=cc(3);hz4<=cc(7);hz1<=cc(9);endf;4整點(diǎn)報(bào)時(shí)模塊從59分50秒開始，每過2秒進(jìn)行低音報(bào)時(shí)，當(dāng)達(dá)到整點(diǎn)時(shí)，進(jìn)行一次高音報(bào)時(shí)libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityzdbsisport(mh,ml,sh,sl:instd_logic_vector(3downto0);sig500,sig1k:outstd_logic);endzdbs;architectureaofzdbsisbeginsig500<='1'when(mh="0101"andml="1001"andsh="0101"and(sl="0010"orsl="0100"orsl="0110"orsl="1000"))else'0';sig1k<='1'when(mh="0000"andml="0000"andsh="0000"andsl="0000")else'0';enda;5動(dòng)態(tài)掃描模塊24進(jìn)制（時(shí)）與60進(jìn)制（分、秒）計(jì)數(shù)器的輸出分成6組，每一組（4位BCD碼）接BCD-7段碼顯示譯碼器（動(dòng)態(tài)顯示只需1個(gè)），驅(qū)動(dòng)數(shù)碼管顯示。選用8個(gè)數(shù)碼管中的6個(gè)作為時(shí)間顯示。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydt_smisport(clk:instd_logic;h,m,s:instd_logic_vector(7downto0);seg7out:outstd_logic_vector(6downto0);sel:bufferstd_logic_vector(2downto0));enddt_sm;architecturebehaofdt_smissignalkey:std_logic_vector(3downto0);beginprocess(clk)variabledount:std_logic_vector(2downto0):="000";beginif(rising_edge(clk))thenifdount="101"thendount:="000";elsedount:=dount+1;endif;endif;sel<=dount;endprocess;PROCESS(sel)BEGINCASEselISwhen"000"=>key<=h(7downto4);when"001"=>key<=h(3downto0);when"010"=>key<=m(7downto4);when"011"=>key<=m(3downto0);when"100"=>key<=s(7downto4);when"101"=>key<=s(3downto0);whenothers=>null;ENDCASE;ENDPROCESS;PROCESS(key)BEGINcasekeyiswhen"0000"=>seg7out<="0111111";when"0001"=>seg7out<="0000110";when"0010"=>seg7out<="1011011";when"0011"=>seg7out<="1001111";when"0100"=>seg7out<="1100110";