數(shù)電實(shí)驗(yàn)ALU設(shè)計(jì)

數(shù)字邏輯設(shè)計(jì)實(shí)驗(yàn)報(bào)告ALU的設(shè)計(jì)與實(shí)現(xiàn)摘要：本實(shí)驗(yàn)基于vhdl語(yǔ)言設(shè)計(jì)一個(gè)基本的ALU,并使用FPGA完成兩個(gè)四位二進(jìn)制數(shù)的加、減、乘及左右移位功能，使用軟件modelsim進(jìn)行了仿真波形檢驗(yàn)，補(bǔ)充部分為了避免使用PPGA會(huì)產(chǎn)生按鍵抖動(dòng)，而使用chipscope和開(kāi)發(fā)平臺(tái)測(cè)量ALU的功能。實(shí)驗(yàn)?zāi)康模菏煜?shù)字電路中流水的概念設(shè)計(jì)一個(gè)基本的ALU，使其具有要求的運(yùn)算功能進(jìn)一步熟悉VHDL語(yǔ)言的編程實(shí)驗(yàn)要求：用FPGA完成兩個(gè)四位數(shù)的加、減、乘及移位功能；編寫(xiě)ALU的VHDL代碼，并通過(guò)Modelsim仿真測(cè)試；用chipscope和開(kāi)發(fā)平臺(tái)測(cè)量ALU的功能實(shí)驗(yàn)方案及原理：實(shí)驗(yàn)方案：我們的總體思路就是分別設(shè)計(jì)出加法、減法、左右移位、乘法部分，最后設(shè)計(jì)選擇器部分來(lái)進(jìn)行運(yùn)算形式的選擇控制。實(shí)驗(yàn)設(shè)計(jì)難點(diǎn)在于：一是流水的設(shè)計(jì)，二是乘法器的設(shè)計(jì)。乘法器的設(shè)計(jì)比較簡(jiǎn)單，還是通過(guò)加法器來(lái)構(gòu)造，只不過(guò)是連線(xiàn)要比以前的復(fù)雜一些。流水的設(shè)計(jì)是要求在輸入輸出端口分別設(shè)計(jì)出一個(gè)觸發(fā)器，達(dá)到延時(shí)的效果，來(lái)實(shí)現(xiàn)流水的功能。實(shí)驗(yàn)原理及系統(tǒng)架構(gòu)：加法器：加法器的設(shè)計(jì)要求：實(shí)現(xiàn)四位帶符號(hào)運(yùn)算。我們?cè)O(shè)計(jì)的思路是為了避免溢出問(wèn)題，先把輸入的4位數(shù)擴(kuò)為五位來(lái)考慮。我們通過(guò)用五個(gè)全加器來(lái)實(shí)現(xiàn)。匚匚—S= (A+B)+缸C=C^C^AB仿真結(jié)果:

注:結(jié)果延時(shí)兩拍輸出減法器設(shè)計(jì)只需將被減數(shù)轉(zhuǎn)換為其補(bǔ)碼然后利用加法器即可。減法時(shí)注意-8的運(yùn)算，a<=ain(3)&ain;b<=not(bin(3)&bin)+〃0001〃;由于帶有符號(hào)位，所以我們?cè)谧詈蠹由狭?001。乘法器：乘法器的設(shè)計(jì)要求：實(shí)現(xiàn)無(wú)符號(hào)位的乘法運(yùn)算。我們?cè)O(shè)計(jì)的思路是用全加器陣列實(shí)現(xiàn)一個(gè)用于四位無(wú)符號(hào)數(shù)的乘法器，將乘數(shù)和被乘數(shù)代入計(jì)算乘積。移位器：移位器的設(shè)計(jì)要求對(duì)四位輸入數(shù)據(jù)進(jìn)行左移，右移操作，并按8位輸出，我們的設(shè)計(jì)思路就是對(duì)于系統(tǒng)的兩個(gè)輸入，對(duì)第一個(gè)輸入進(jìn)行移位處理，取第二

個(gè)輸入的后兩位來(lái)判斷移幾位，在預(yù)先輸入的時(shí)候就判定了進(jìn)行左移還是右移。具體處理，使用case語(yǔ)句對(duì)每一種移位進(jìn)行處理。若是進(jìn)行右移將是循環(huán)移位，將溢出的位數(shù)到左邊補(bǔ)位。5）.頂層以及控制器的設(shè)計(jì):控制部分Instructions1.Fiveinstruetions?3bit5needed頂層的設(shè)計(jì)要求是設(shè)計(jì)一個(gè)控制器來(lái)決定對(duì)輸入的數(shù)據(jù)進(jìn)行哪種操作，并延時(shí)一拍后輸出相應(yīng)的結(jié)果。由輸入的控制信號(hào)來(lái)決定進(jìn)入下圖中六個(gè)運(yùn)算模塊中的哪一個(gè)，并針對(duì)每一個(gè)模塊設(shè)計(jì)一個(gè)狀態(tài)機(jī)，使輸入控制信號(hào)時(shí)打開(kāi)相應(yīng)的模塊，并在兩拍之后關(guān)閉現(xiàn)在以開(kāi)啟的模塊（如果這兩拍內(nèi)沒(méi)有收到打開(kāi)這個(gè)模塊控制信號(hào)）。我們使用的是觸發(fā)器的延時(shí)來(lái)設(shè)計(jì)狀態(tài)機(jī)。Iiisirction控制器結(jié)構(gòu)圖整體結(jié)構(gòu)Iiisirction控制器結(jié)構(gòu)圖整體結(jié)構(gòu)仿真結(jié)果:通卵、堰WMaII|ilF7|設(shè)計(jì)總結(jié)：這次ALU的設(shè)計(jì)，我們收獲很大，在設(shè)計(jì)各個(gè)模塊的時(shí)候，我們和其他同學(xué)進(jìn)行了很多交流，互相交流意見(jiàn)；這次設(shè)計(jì)，使我們進(jìn)一步了解了“流水”，“狀態(tài)機(jī)”，“頂層”的概念，為我們以后設(shè)計(jì)綜合數(shù)字電路打下了基礎(chǔ)；附錄：VHDL程序ALUentityALUisport(rst:instd_logic;clk:instd_logic;datin1:instd_logic_vector(3downto0);datin2:instd_logic_vector(3downto0);inst:instd_logic_vector(2downto0);ensure:instd_logic;datout:outstd_logic_vector(7downto0));endALU;architectureBehavioralofALUiscomponentMUXisport(inst:instd_logic_vector(2downto0);sum:instd_logic_vector(7downto0);sub:instd_logic_vector(7downto0);multi:instd_logic_vector(7downto0);ls:instd_logic_vector(7downto0);rs:instd_logic_vector(7downto0);datout:outstd_logic_vector(7downto0));endcomponent;componentADDERisport(ain:instd_logic_vector(3downto0);bin:instd_logic_vector(3downto0);sum:outstd_logic_vector(7downto0));endcomponent;componentsubtractorisport(ain:instd_logic_vector(3downto0);bin:instd_logic_vector(3downto0);sub:outstd_logic_vector(7downto0));endcomponent;componentmultiplierisport(a:instd_logic_vector(3downto0);b:instd_logic_vector(3downto0);multi:outstd_logic_vector(7downto0));endcomponent;componentLSisport(ain:instd_logic_vector(3downto0);bin:instd_logic_vector(3downto0);s:outstd_logic_vector(7downto0));endcomponent;componentRSisport(ain:instd_logic_vector(3downto0);bin:instd_logic_vector(3downto0);s:outstd_logic_vector(7downto0));endcomponent;signaldin1,din2:std_logic_vector(3downto0);signal datout0,datout1,datout2,datout3,datout4,dat :std_logic_vector(7downto0);beginU0:ADDERportmap(ain=>din1,bin=>din2,sum=>datout0);U1:subtractorportmap(ain=>din1,bin=>din2,sub=>datout1);U2:multiplierportmap(a=>din1,b=>din2,multi=>datout2);U3:LSportmap(ain=>din1,bin=>din2,s=>datout3);U4:RSportmap(ain=>din1,bin=>din2,s=>datout4);U5:MUXportmap(inst=>inst,sum=>datout0,sub=>datout1,multi=>datout2,ls=>datout3,rs=>datout4,datout=>dat);process(rst,clk)beginifrst='1'thendin1<=(others=>'0');din2<=(others=>'0');elsifclk'eventandclk='1'thendin1<=datin1;din2<=datin2;endif;endprocess;process(ensure,clk)beginifensure='0'thendatout<=(others=>'0');elsifclk'eventandclk='1'thendatout<=dat;endif;endprocess;endBehavioral;ADDERentityADDERisport(ain:instd_logic_vector(3downto0);bin:instd_logic_vector(3downto0);sum:outstd_logic_vector(7downto0));endADDER;architecturebehavioralofADDERiscomponentF_ADDisport(A:instd_logic;B:instd_logic;Cin:instd_logic;S:outstd_logic;Cout:outstd_logic);endcomponent;signalc1,c2,c3,c4,c5,s1,s2,s3,s4,s5:std_logic;signala,b:std_logic_vector(4downto0);begina<=ain(3)&ain;b<=bin(3)&bin;U1 : F_ADD port map(A=>a(0),B=>b(0),Cin=>'0',S=>s1,Cout=>c1);U2 : F_ADD port map(A=>a(1),B=>b(1),Cin=>c1,S=>s2,Cout=>c2);U3 : F_ADD port map(A=>a(2),B=>b(2),Cin=>c2,S=>s3,Cout=>c3);U4 : F_ADD port map(A=>a(3),B=>b(3),Cin=>c3,S=>s4,Cout=>c4);U5 : F_ADD port map(A=>a(4),B=>b(4),Cin=>c4,S=>s5,Cout=>c5);sum<=s5&s5&s5&s5&s4&s3&s2&s1;endbehavioral;Subtractorentitysubtractorisport(ain:instd_logic_vector(3downto0);bin:instd_logic_vector(3downto0);sub:outstd_logic_vector(7downto0));endsubtractor;architecturebehavioralofsubtractoriscomponentF_ADDisport(A:instd_logic;B:instd_logic;Cin:instd_logic;S:outstd_logic;Cout:outstd_logic);endcomponent;signalc1,c2,c3,c4,c5,s1,s2,s3,s4,s5:std_logic;signala,b:std_logic_vector(4downto0);begina<=ain(3)&ain;b<=not(bin(3)&bin)+〃0001〃；U1 : F_ADD port map(A=>a(0),B=>b(0),Cin=>'0',S=>s1,Cout=>c1);U2 : F_ADD port map(A=>a(1),B=>b(1),Cin=>c1,S=>s2,Cout=>c2);U3 : F_ADD port map(A=>a(2),B=>b(2),Cin=>c2,S=>s3,Cout=>c3);U4 : F_ADD port map(A=>a(3),B=>b(3),Cin=>c3,S=>s4,Cout=>c4);U5 : F_ADD port map(A=>a(4),B=>b(4),Cin=>c4,S=>s5,Cout=>c5);sub<=s5&s5&s5&s5&s4&s3&s2&s1;endbehavioral;Multiplierentitymultiplierisport(a:instd_logic_vector(3downto0);b:instd_logic_vector(3downto0);multi:outstd_logic_vector(7downto0));endmultiplier;architectureBehavioralofmultiplieriscomponentF_ADDisport(A:instd_logic;B:instd_logic;Cin:instd_logic;S:outstd_logic;Cout:outstd_logic);endcomponent;signalpp0,pp1,pp2,pp3:std_logic_vector(3downto0);signalC11,C12,C13,C21,C22,C23,C31,C32,C33,C41,C42,C43,S11,S12,S13,S21,S22,S23,S31,S32,S33,S41,S42,S43:std_logic;beginpp0<=(b(0)anda(3)) &(b(0) and a(2)) & (b(0) anda(1)) & (b(0) anda(0));pp1<=(b(1)anda(3)) &( b(1) and a(2)) & (b(1) anda(1)) & (b(1) anda(0));pp2<=(b(2)anda(3)) &( b(2) and a(2)) & (b(2) anda(1)) & (b(2) anda(0));pp3<=(b(3)anda(3)) &( b(3) and a(2)) & (b(3) anda(1)) & (b(3) anda(0));U11:F_ADDportmap(A=>pp1(0),B=>pp0(1),Cin=>'0',S=>S11,Cout=>C11);U12:F_ADDportmap(A=>pp1(1),B=>pp0(2),Cin=>'0',S=>S12,Cout=>C12);U13:F_ADDportmap(A=>pp1(2),B=>pp0(3),Cin=>'0',S=>S13,Cout=>C13);U21:F_ADDportmap(A=>pp2(0),B=> S12,Cin=>C11,S=>S21,Cout=>C21);U22:F_ADDportmap(A=>pp2(1),B=> S13,Cin=>C12,S=>S22,Cout=>C22);U23:F_ADDportmap(A=>pp2(2),B=>pp1(3),Cin=>C13,S=>S23,Cout=>C23);U31:F_ADDportmap(A=>pp3(0),B=> S22,Cin=>C21,S=>S31,Cout=>C31);U32:F_ADDportmap(A=>pp3(1),B=> S23,Cin=>C22,S=>S32,Cout=>C32);U33:F_ADDportmap(A=>pp3(2),B=>pp2(3),Cin=>C23,S=>S33,Cout=>C33);U41:F_ADDportmap(A=> C31,B=> S32,Cin=>'0',S=>S41,Cout=>C41);U42:F_ADDportmap(A=> C32,B=> S33,Cin=>C41,S=>S42,Cout=>C42);U43:F_ADDportmap(A=> C33,B=>pp3(3),Cin=>C42,S=>S43,Cout=>C43);multi<=C43&S43&S42&S41&S31&S21&S11&pp0(0);endBehavioral;MUXentityMUXisport(inst:instd_logic_vector(2downto0);sum:instd_logic_vector(7downto0);sub:instd_logic_vector(7downto0);multi:instd_logic_vector(7downto0);ls:instd_logic_vector(7downto0);rs:instd_logic_vector(7downto0);datout:outstd_logic_vector(7downto0));endMUX;architectureBehavioralofMUXisbeginprocess(inst)begincaseinstiswhen"001"=>datout<=sum;when"010"=>datout<=sub;when"011"=>datout<=multi;when"100"=>datout<=ls;when"101"=>datout<=rs;whenothers=>null;endcase;endprocess;endBehavioral;LSlibraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityLSisport(ain:instd_logic_vector(3downto0);

bin:instd_logic_vector(3downto0)s:outstd_logic_vector(7downto0))endLS;architectureBehavioralofLSissignalnum:std_logic_vector(2downto0);signala,b:std_logic_vector(7downto0);beginnum<=bin(2)&bin(1)&bin(0);a<="0000"&ain;process(num,a)begincasenumiswhen"000"=>b<=a;when"001"=>0) & a(7);0) & a(7 downto 6);0) & a(7);0) & a(7 downto 6);0) & a(7 downto 5);0) & a(7 downto 4);0) & a(7 downto 3);0) & a(7 downto 2);downto1);when"010"=>b<=a(5downtowh