復(fù)習(xí)第十二章2簡(jiǎn)化版

William

StallingsComputer

Organizationand

Architecture6th

EditionCPU結(jié)構(gòu)和功能Chapter12CPU

Structureand

FunctionPage424Execution

usually

does

not

access

mainmemoryCan

fetch

nextinstruction

during

executionof

current

instructionCalled

instruction

prefetch指令預(yù)取流水線§12.4

PipeliningFetch

accessing

main

memoryTwo

Stage

Instruction

PipelinePage425作廢Improved

PerformanceBut

not

doubled,

for

two

reasons:—Fetch

usually

shorter

than

execution—Any

jump

or

branch

means

thatprefetched

instructions

are

not

therequired

instructionsAdd

more

stages

to

improveperformancePage424Instruction

operationsdivided

6

stages

6階段Fetch

instruction(FI)Decode

instruction(DI)Calculate

operands(CO)

(i.e.

calculate

EA)Fetch

operands(FO)Execute

instructions(EI)Write

result(WR)Overlap

these

operationsPage425Page426Timing

of

Pipeline

流水線時(shí)序圖兩點(diǎn)說(shuō)明：不會(huì)總是6個(gè)階段；存儲(chǔ)器沖突問(wèn)題。Speedup

factort

–max

stage

delay

最大段延遲n

–

number

of

instructionsk

–

number

of

stagesWithout

pipeline—T1

=

n

k

t—e.g.

TK=

9

x

6

t=54

tWith

pipeline—TK

=[(K–1)

+

n]

t—e.g.

TK=(6-1+9)

t=14

tPage431加速因子Speedup

factorSk

=T1

/

Tk=

n

kt

/[k

+

(n

–1)]t=

n

k

/[k

+

(n

–1)]When

k

increases,

Sk

increases.When

n

increase,

Sk

tendsto

k.

It

means:thelargerthe

numberof

pipeline

stages,

thegreater

the

potentialforspeedup.However,as

a

practical

matter, k=(6~十幾個(gè))stagesPage431加速因子Speedup

Factors

withInstruction

PipeliningPage432對(duì)數(shù)坐標(biāo)log2

xK=6,9,12n=10,20,30※Branch

limits

pipeline’s

performance*Several

other

factors

serve

to

limit

theperformance

enhancement.The

worse

factor

isthe

conditional

branch

instruction,

which

can

invalidate

severalinstructionfetches.Itchanges the

sequenceof

instruction

flowing.Assume

instruction

3

isa

conditional

branchtoinstruction

15.Until

the

instruction

is

executed,

no

way

ofknowing

which

instruction

will

comenext.Page426The

Effect

of

a

Condition

Branch

onInstruction

Pipeline

OperationPage427知道轉(zhuǎn)移指令知道轉(zhuǎn)移目的知道條件滿(mǎn)足※Dealing

with

Branches*(1)Multiple

Streams多流水線Have

two

pipelinesprefetch

each

branch

into

a

separate

pipelinePrefetch

Branch

Target

預(yù)取轉(zhuǎn)移目標(biāo)Loop

buffer

循環(huán)緩沖Branch

prediction

轉(zhuǎn)移預(yù)測(cè)—Predict

never

taken

預(yù)測(cè)轉(zhuǎn)移絕不發(fā)生—Predict

always

taken

預(yù)測(cè)轉(zhuǎn)移總是發(fā)生—Predict

by

Opcode

依操作碼預(yù)測(cè)連續(xù)猜錯(cuò)兩次，改變狀態(tài)—Taken/Not

taken

switch預(yù)測(cè)轉(zhuǎn)移發(fā)生不發(fā)生—Branch

history

table

轉(zhuǎn)移歷史表(5)Delayed

branching

延遲轉(zhuǎn)移Do

not

take

jump

untilyouhave

toThis

following

instruction

is