簡單卷積器的設(shè)計(jì)

練習(xí)十一.簡單卷積器的設(shè)計(jì)// 'timescalelOOps/lOOpsmodulecon1(address,indata,outdata,wr,nconvst,nbusy,enoutl,enout2,CLK,reset,start);inputCLK, //采用lOMHZ的時(shí)鐘reset, //復(fù)位信號(hào)start, 〃因?yàn)镽AM的空間是有限的，當(dāng)RAM存滿后采樣和卷積都會(huì)停止。//此時(shí)給一個(gè)start的高電平脈沖將會(huì)開始下一次的卷積。nbusy; //從A/D轉(zhuǎn)換器來的信號(hào)表示轉(zhuǎn)換器的忙或閑outputwr,//RAM寫控制信號(hào)enout1,enout2,//enoutl是存儲(chǔ)卷積低字節(jié)結(jié)果RAM的片選信號(hào)〃enout2是存儲(chǔ)卷積高字節(jié)結(jié)果RAM的片選信號(hào)nconvst,//給A/D轉(zhuǎn)換器的控制信號(hào),命令轉(zhuǎn)換器開始工作,低電平有效address;//地址輸出input[7:O]indata;//從A/D轉(zhuǎn)換器來的數(shù)據(jù)總線output[7:O]outdata;//寫到RAM去的數(shù)據(jù)總線wirenbusy;regwr;regnconvst,enoutl,enout2;reg[7:O]outdata;reg[lO:O]address;reg[8:O]state;reg[l5:O]result;reg[23:O]line;reg[ll:O]counter;reg high;reg[4:O]j;reg EOC;parameterhl=l,h2=2,h3=3;//假設(shè)的系統(tǒng)系數(shù)parameterIDLE=9'bOOOOOOOOl,START=9'bOOOOOOOlO,NCONVST=9'bOOOOOOlOO,READ=9'bOOOOOlOOO,CALCU=9'bOOOOlOOOO,WRREADY=9'bOOOlOOOOO,WR=9'bOOlOOOOOO,WREND=9'bOlOOOOOOO,WAITFOR=9'blOOOOOOOO;parameterFMAX=20;〃因?yàn)锳/D轉(zhuǎn)換的時(shí)間是隨機(jī)的，為保證按一定的頻率采樣，A/D〃轉(zhuǎn)換控制信號(hào)應(yīng)以一定頻率給出。這里采樣頻率通過FMAX控制//為500KHZ。always@(posedgeCLK)if(!reset)beginstate<=IDLE;nconvst<=1'b1;enout1<=1;enout2<=1;counter<=12'b0;high<=0;wr<=1;line<=24'b0;address<=11'b0;endelsecase(state)IDLE:if(start==1)begincounter<=0; //counter是一個(gè)計(jì)數(shù)器，記錄已//用的RAM空間line<=24'b0;state<=START;endelsestate<=IDLE;//START狀態(tài)控制A/D開始轉(zhuǎn)換START:if(EOC)beginnconvst<=0;high<=0;state<=NCONVST;endelsestate<=START;//NCONVST狀態(tài)是A/D轉(zhuǎn)換保持階段NCONVST:beginnconvst<=1;state<=READ;end//READ狀態(tài)讀取A/D轉(zhuǎn)換結(jié)果，計(jì)算卷積結(jié)果READ:beginif(EOC)beginline<={line[15:0],indata};state<=CALCU;endelsestate<=READ;endCALCU:beginresult<=line[7:0]*h1+line[15:8]*h2+line[23:16]*h3;state<=WRREADY;end〃將卷積結(jié)果寫入RAM時(shí)，先寫入低字節(jié)，再寫入高字節(jié)//WRREADY狀態(tài)是寫RAM準(zhǔn)備狀態(tài)，建立地址和數(shù)據(jù)信號(hào)WRREADY:beginaddress<=counter;if(!high)outdata<=result[7:0];elseoutdata<=result[15:8];state<=WR;end//WR狀態(tài)產(chǎn)生片選和寫脈沖WR:beginif(!high)enout1<=0;elseenout2<=0;wr<=0;state<=WREND;end//WREND狀態(tài)結(jié)束一次寫操作，若還未寫入高字節(jié)則轉(zhuǎn)到WRREADY//態(tài)開始高字節(jié)寫入WREND:beginwr<=1;enout1<=1;enout2<=1;if(!high)beginhigh<=1;state<=WRREADY;endelsestate<=WAITFOR;end//WAITFOR狀態(tài)控制采樣頻率并判斷RAM是否已被寫滿WAITFOR:beginif(j==FMAX-1)begincounter<=counter+1;if(!counter[11])state<=START;elsebeginstate<=IDLE;$display($time,"Theramisusedup.");$stop;endendelsestate<=WAITFOR;enddefault:state<=IDLE;endcase//assignrd=1;//RAM的讀信號(hào)始終保持為高//j記錄時(shí)鐘，與FMAX共同控制采樣頻率〃由于直接用CLK的上升沿對(duì)nbusy判斷以//決定某些操作是否運(yùn)行時(shí)，會(huì)因?yàn)閮蓚€(gè)信號(hào)//的跳變沿相隔太近而令狀態(tài)機(jī)不能正常工作。因此〃利用CLK的下降沿建立EOC信號(hào)與nbusy同步，相位〃相差180度，然后用CLK的上升沿判斷操作是否進(jìn)行。always@(negedgeCLK)beginEOC<=nbusy;if(!reset||state==START)j<=1;elsej<=j+1;endendmodule// testcon1.v 'timescalelOOps/lOOpsmoduletestcon1;wirewr,enin,enout1,enout2;wire[10:0]address;regrd,CLK,reset,start;wirenbusy;wirenconvst;wire[7:0]indata;wire[7:0]outdata;integeri;parameterHALF_PERIOD=1000;//產(chǎn)生10KHZ的時(shí)鐘initialbeginrd=1;i=0;CLK=1;forever#HALF_PERIODCLK=~CLK;end//產(chǎn)生置位信號(hào)initialbeginreset=1;#(HALF_PERIOD*2+50)reset=0;#(HALF_PERIOD*3)reset=1;end//產(chǎn)生開始卷積控制信號(hào)initialbeginstart=0;#(HALF_PERIOD*7+20)start=1;#(HALF_PERIOD*2)start=0;#(HALF_PERIOD*1000)start=1;#(HALF_PERIOD*2)start=0;endassignenin=1;con1con(.address(address),.indata(indata),.outdata(outdata),.wr(wr),.nconvst(nconvst),.nbusy(nbusy),.enout1(enout1),.enout2(enout2),.CLK(CLK),.reset(reset),.start(start));sramramlow(.Address(address),.Data(outdata),.SRW(wr),.SRG(rd),.SRE(enout1));adcadc(.nconvst(nconvst),.nbusy(nbusy),.data(indata));endmodule//卷積器的改進(jìn)// con3ad.v 'timescalelns/100psmodulecon3ad(indata,outdata,address,CLK,reset,start,nconvst1,nconvst2,nconvst3,nbusy1,nbusy2,nbusy3,wr,enout1,enout2);inputindata,CLK,reset,start,nbusy1,nbusy2,nbusy3;outputoutdata,address,nconvstl,//采用三根控制線控制三片A/D轉(zhuǎn)換器nconvst2,nconvst3,wr,enout1,enout2;wire[7:0]indata;wireCLK,reset,start,nbusy1,nbusy2,nbusy3;reg[7:0]outdata;reg[10:0]address;reg nconvst1,nconvst2,nconvst3,wr,enout1,enout2;reg[6:0]state;reg[5:0]i;reg[1:0]j;reg[11:0]counter;reg[23:0]line;reg[15:0]result;reghigh;regk;regEOC1,EOC2,EOC3;parameterh1=1,h2=2,h3=3;parameterIDLE=7'b0000001,READ_PRE=7'b0000010,READ=7'b0000100,CALCU=7'b0001000,WRREADY=7'b0010000, WR=7'b0100000,WREND=7'b1000000;always@(posedgeCLK)beginif(!reset)beginstate<=IDLE;counter<=12'b0;wr<=1;enout1<=1;enout2<=1;outdata<=8'bz;address<=11'bz;line<=24'b0;result<=16'b0;high<=0;end//endof"if"elsebegincase(state)IDLE:if(start)begincounter<=0;state<=READ_PRE;endelsestate<=IDLE;READ_PRE:if(EOC1||EOC2||EOC3)//由于頻率相對(duì)改進(jìn)前的卷積//器大大提高，所以加入//READ_PRE狀態(tài)對(duì)取數(shù)操作//予以緩沖。state<=READ;elsestate<=READ_PRE;READ:beginhigh<=0;enout2<=1;wr<=1;if(j==1)beginif(EOC1)beginline<={line[15:0],indata};state<=CALCU;endelsestate<=READ_PRE;endelseif(j==2&&counter!=0)beginif(EOC2)beginline<={line[15:0],indata};state<=CALCU;endelsestate<=READ_PRE;endelseif(j==3&&counter!=0)beginif(EOC3)beginline<={line[15:0],indata};state<=CALCU;endelsestate<=READ_PRE;endelsestate<=READ;endCALCU:beginresult<=line[7:0]*h1+line[15:8]*h2+line[23:16]*h;state<=WRREADY;endWRREADY:beginwr<=1;address<=counter;if(k==1)state<=WR;elsestate<=WRREADY;endWR:beginif(!high)enout1<=0;elseenout2<=0;wr<=0;if(!high)outdata<=result[7:0];elseoutdata<=result[15:8];if(k==1)state<=WREND;elsestate<=WR;endWREND:beginwr<=1;enout1<=1;enout2<=1;if(k==1)if(!high)beginhigh<=1;state<=WRREADY;endelsebegincounter<=counter+1;if(counter[11]&&counter[0])state<=IDLE;elsestate<=READ_PRE;endelsestate<=WREND;enddefault:state<=IDLE;endcase//endofthecaseend//endof"else"end//endof"always"http://計(jì)數(shù)器i用來記錄時(shí)間always@(posedgeCLK)beginif(!reset)i<=0;elsebeginif(i==44)i<=0;elsei<=i+1;endend//j是控制信號(hào)，協(xié)調(diào)卷積器輪流從三片A/D上讀取數(shù)據(jù)。always@(posedgeCLK)beginif(i==4)j<=2;elseif(i==10)j<=0;elseif(i==19)j<=3;elseif(i==25)j<=0;elseif(i==34)j<=1;elseif(i==40)j<=0;end//k是計(jì)數(shù)器，用以控制寫操作信號(hào)always@(posedgeCLK)beginif(state==WRREADY||state==WR||state==WREND)if(k==1)k<=0;else k<=1;elsek<=0;end〃根據(jù)計(jì)數(shù)器i控制三片A/D轉(zhuǎn)換信號(hào)NCONVST1,NC0NVST2,NC0NVST3always@(posedgeCLK)beginif(!reset)nconvst1<=1;elseif(i==0)nconvst1<=0;elseif(i==3)nconvst1<=1;endalways@(posedgeCLK)beginif(!reset)nconvst2<=1;elseif(i==15)nconvst2<=0;elseif(i==18)nconvst2<=1;endalways@(posedgeCLK)beginif(!reset)nconvst3<=1;elseif(i==30)nconvst3<=0;elseif(i==33)nconvst3<=1;endalways@(negedgeCLK)beginEOC1<=nbusy1;EOC2<=nbusy2;EOC3<=nbusy3;endendmodule// 測試程序如下：'timescalelns/100psmoduletestcon3ad;wirewr,enin,enout1,enout2;wire[10:0]address;regclk,reset,start;rd;wirenbusy1,nbusy2,nbusy3;wirenconvst1,nconvst2,nconvst3;wire[7:0]indata;wire[7:0]outdata;parameterHALF_PERIOD=15;//時(shí)鐘周期為30nsinitialbeginclk=1;forever#HALF_PERIODclk=~clk;endinitialbeginreset=1;#110reset=0;#140reset=1;endinitialbeginstart=0;rd=1;#420start=1;#120start=0;#107600start=1;#150start=0;endassignenin=1;con3adcon3ad(.indata(indata),.outdata(outdata),.address(address),.CLK(clk),.reset(reset),.start(start),.nconvst1(nconvst1),.nconvst2(nconvst2),.nconvst3(nconvst3),.nbusy1(nbusy1),.nbusy2(nbusy2),.nbusy3(nbusy3),.wr(wr),.enout1(enout1),.enout2(enout2));sramramlow(.Address(address),.Data(outdata),.SRW(wr),.SRG(rd),.SRE(enout1));adcad_1(.nconvst(nconvst1),.nbusy(nbusy1),.data(indata));adcad_2(.nconvst(nconvst2),.nbusy(nbusy2),.data(indata));adcad_3(.nconvst(nconvst3),.nbusy(nbusy3),.data(indata));endmodule// A/D轉(zhuǎn)換器的VerilogHDL行為模型如下：// adc.v 'timescale100ps/100psmoduleadc(nconvst,nbusy,data);inputnconvst; //A/D啟動(dòng)脈沖ST,即上圖中outputnbusy; //A/D工作標(biāo)志，即上圖中output data; //數(shù)據(jù)總線，從AD.DATA文件中讀取數(shù)據(jù)后經(jīng)端口輸出reg[7:0]databuf,i;//內(nèi)部寄存器reg nbusy;wire[7:0]data;reg[7:0]data_mem[0:255];reg link_bus;integertconv,t5,t8,t9,t12;integerwideth1,wideth2,wideth;//時(shí)間參數(shù)定義(依據(jù)AD7886手冊)：always@(negedgenconvst)begintconv=9500+{$random}%500;//(type950ns,max1000ns)ConversionTimet5={$random}%1000;//(max100ns)CONVSTtoBUSYPropagationDlay//CL=10pft8=200;//(min20ns)CL=20pfDataSetupTimePriortoBUSY//(min10ns)CL=100pft9=100+{$random}%900;//(min10ns,max100ns)BusRelinquishTimeAfterCONVSTt12=2500;//(type)BUSYHightoCONVSTLow,SHAAcquisitionTimeendinitialbegin$readmemh("adc.data",data_mem);〃從數(shù)據(jù)文件adc.data中讀取數(shù)據(jù)i=0;nbusy=1;link_bus=0;endassigndata=link_bus?databuf:8'bzz;//三態(tài)總線/* 在信號(hào)nconvst的負(fù)跳降沿到來后，隔t5秒nbusy信號(hào)置為低，tconv是AD將模擬信號(hào)轉(zhuǎn)換為數(shù)字信號(hào)的時(shí)間，在信號(hào)nconvst的正跳降沿到來后經(jīng)過tconv時(shí)間后，輸出nbusy信號(hào)變?yōu)楦摺?*/always@(negedgenconvst)fork#t5nbusy=0;@(posedgenconvst)begin#tconvnbusy=1;endjoin/* nconvst信號(hào)的下降沿觸發(fā)，經(jīng)過t9延時(shí)后，把數(shù)據(jù)總線輸出關(guān)閉置為高阻態(tài)，如圖示。nconvst信號(hào)的上升沿到來后，經(jīng)過(tconv-⑻時(shí)間，輸出一個(gè)字節(jié)(8位數(shù)據(jù))到databuf,該數(shù)據(jù)來自于data_mem。而data_mem中的數(shù)據(jù)是初始化時(shí)從數(shù)據(jù)文件AD.DATA中讀取的。此時(shí)應(yīng)啟動(dòng)總線的三態(tài)輸出。 */always@(negedgenconvst)begin@(posedgenconvst)begin#(tconv-t8)databuf=data_mem[i];endif(wideth<10000&&wideth>500)beginif(i==255)i=0;elsei=i+1;endelsei=i;end//在模數(shù)轉(zhuǎn)換期間關(guān)閉三態(tài)輸出，轉(zhuǎn)換結(jié)束時(shí)啟動(dòng)三態(tài)輸出always@(negedgenconvst)fork#t9link_bus=1'b0; //關(guān)閉三態(tài)輸出，不允許總線輸出@(posedgenconvst)begin#(tconv-t8)link_bus=1'b1;endjoin/* 當(dāng)nconvst輸入信號(hào)的下一個(gè)轉(zhuǎn)換的下降沿與nbusy信號(hào)上升沿之間時(shí)間延遲小于t12時(shí)，將會(huì)出現(xiàn)警告信息，通知設(shè)計(jì)者請(qǐng)求轉(zhuǎn)換的輸入信號(hào)頻率太快，A/D器件轉(zhuǎn)換速度跟不上。仿真模型不僅能夠?qū)崿F(xiàn)硬件電路的輸出功能，同時(shí)能夠?qū)斎胄盘?hào)進(jìn)行檢測，

當(dāng)輸入信號(hào)不符合手冊要求時(shí)，顯示警告信息。*///檢查A/D啟動(dòng)信號(hào)的頻率是否太快always@(posedgenbusy)begin#t12;if(!nconvst)begin$display("Warning!SHAAcquisitionTimeistooshort!");end//else$display("SHAAcquisitionTimeisenough!");end//檢查A/D啟動(dòng)信號(hào)的負(fù)脈沖寬度是否足夠和太寬always@(negedgenconvst)beginwideth=$time;@(posedgenconvst)wideth=$time-wideth;if(wideth<=500||wideth>10000)begin$display("nCONVSTPulseWidth=%d",wideth);$display("Warning!nCONVSTPulseWidthistoonarrowortoowide!");//$stop;endendendmodule附錄二.2K*8位異步CMOS靜態(tài)RAMHM-65162模型:*FileName*FileName:sram.v*Function*Function*ModuleName:sram*ModuleName:sramDescriptionReferenceDescriptionReferencesramisaVerilogHDLmodelforHM-65162,2K*8bitAsynchronousCMOSStatic*RAM.ItisusedinsimulationtosubstitutetherealRAMtoverifywhether*thewritingorreadingoftheRAMisOK.Thismoduleisabehavioralmodel**forsimulationonly,notsynthesizable.It'swritingandreadingfunction**areverified./// sram.vmodulesram(Address,Data,SRG,SRE,SRW);input[10:0]Address;inputSRG,//OutputenableSRE,//ChipenableSRW;//Writeenableinout[7:0]Data;//Buswire[10:0]Addr=Address;reg[7:0] RdData;reg[7:0] SramMem[0:'h7ff];regRdSramDly,RdFlip;wire[7:0]FlpData,Data;regWR_flag;//TojudgethesignalsaccordingtothespecificationofHM-65162integeri;wire RdSram=~SRG&~SRE;wire WrSram=~SRW&~SRE;reg[10:0]DelayAddr;reg[7:0]DelayData;reg WrSramDly;integerfile;assignFlpData=(RdFlip)?~RdData:RdData;assignData =(RdSramDly)?FlpData:'hz;/ J 「 1*1 //*******************parametersofreadcircle***************************///參數(shù)序號(hào)、最大或最小、參數(shù)含義parameterTAVQV=90,//2(max)AddressaccesstimeTELQV=90,//3(max)ChipenableaccesstimeTELQX=5,//4(min)ChipenableoutputenabletimeTGLQV=65,//5(max)OutputenableaccesstimeTGLQX=5,//6(min)OutputinableoutputenabletimeTEHQZ=50,//7(max)ChipenableoutputdisabletimeTGHQZ=40,//8(max)OutputenableoutputdisabletimeTAVQX=5;//9(min)Outputholdfromaddresschange

「 /*******************parametersofwritecircle**************************/TWLWH=55,//13TWHAX=15,//14TWLQZ=50,//16TDVWH=30,//17TWHDX=20,//18TWHQX=20,//19TWLEH=55,//20TDVEH=30,//21parameterTAVWL=10,//12TAVWH=70;parameterTAVWL=10,//12TAVWH=70;//22(min)Chipenablepulsesetuptime,//writeenableplusewidth,(min10) Writeenablereadsetuptime,//讀上升沿后地址保留時(shí)間(max)Writeenableoutputdisabletime(min)Datasetuptime(min15)Dataholdtime(min0)Writeenableoutputenabletime,0(min)Writeenablepulsesetuptime(min)Chipenabledatasetuptime(min65)Addressvalidtoendofwriteinitialbeginfile=$fopen("ramlow.txt");if(!file)begin$display("Couldnotopenthefile.");$stop;endendinitialbeginfor(i=0;i<'h7ff;i=i+1)SramMem[i]=i;//$monitor($time,,"DelayAddr=%h,DelayData=%h",DelayAddr,DelayData);endinitialRdSramDly=0;initialWR_flag=1;always@(posedgeRdSram)#TGLQXRdSramDly=RdSram;always@(posedgeSRW) #TWHQXRdSramDly=RdSram;always@(Addr)begin#TAVQX;RdFlip=1;//addressaccesstime#(TGLQV-TAVQX);

//addressaccesstimeif(RdSram)RdFlip=0;endalways@(posedgeRdSram)beginRdFlip=1;#TAVQV;//Outputenableaccesstimeif(RdSram)RdFlip=0;endalways@(Addr)#TAVQXRdFlipalways@(Addr)#TAVQXRdFlip=1;RdSramDly=RdSram;RdSramDly=RdSramDly=RdSram;RdSramDly=RdSram;#TWLQZRdSramDly=0;#TAVWLDelayAddr=Addr;//Addresssetup#TDVWHDelayData