集成電路設(shè)計-組合邏輯電路設(shè)計

1集成電路設(shè)計第六章組合邏輯電路設(shè)計DesigningCombinationalLogicCircuits2主要內(nèi)容組合邏輯與時序邏輯；靜態(tài)互補CMOS；CMOS組合邏輯設(shè)計；CMOS延遲時間；有比邏輯；傳輸門；動態(tài)邏輯;串聯(lián)動態(tài)門。3Combinationalvs.SequentialLogicCombinationalSequentialOutput=f(In)Output=f(In,PreviousIn)無反饋；非再生；BOOL函數(shù)；NOR，NAND，XOR。與當(dāng)前輸入及以前的值有關(guān)；可再生；有記憶模塊/保持狀態(tài)；寄存器、計數(shù)器、振蕩器、存儲器。46-1靜態(tài)互補CMOSNMOS，PMOS傳輸壓降；靜態(tài)互補CMOS；組合邏輯設(shè)計；標(biāo)準(zhǔn)單元；互補CMOS特點；5ThresholdDropsVDDVDD

0PDN0

VDDCLCLPUNVDD0

VDD-VTnCLVDDVDDVDD

|VTp|CLSDSDVGSSSDDVGSPMOS傳送強1，弱0；NMOS傳送強0，弱1。6靜態(tài)（Static）CMOS穩(wěn)態(tài)時，輸出通過低電阻回路接地或電源；輸出是輸入的BOOL函數(shù)；7NMOS串并聯(lián)

（inSeries/ParallelConnection）Transistorscanbethoughtasaswitchcontrolledbyitsgatesignal8PMOS串并聯(lián)

（inSeries/ParallelConnection）9互補CMOS方式PUN是PDN的互補對（DUAL）；利用DeMorgan定律10StaticComplementaryCMOSVDDF(In1,In2,…InN)In1In2InNIn1In2InNPUNPDNPMOSonlyNMOSonly……上拉網(wǎng)絡(luò)下拉網(wǎng)絡(luò)11移動反相小圈的方法AOI，OAI中；用NFET構(gòu)成邏輯門關(guān)系，在輸出與GND之間構(gòu)成NFET邏輯電路；運用DeMorgan定律，將小圈回推至輸入端，使每個輸入都加上小圈；用PFET構(gòu)成邏輯門關(guān)系，在輸出與VDD之間構(gòu)成PFET邏輯電路；構(gòu)造CMOS電路。12ABA+BA+BAB13例子—NAND14例子—NOR15例子—ComplexCMOSGateDABCDABCOUT=D+A?(B+C)16復(fù)合邏輯電路綜合—結(jié)構(gòu)化設(shè)計17單元設(shè)計（CellDesign）標(biāo)準(zhǔn)單元（StandardCells）通用邏輯；可綜合；相同高度，不同寬度。數(shù)據(jù)路徑單元（DatapathCells）用于規(guī)則、結(jié)構(gòu)化設(shè)計（如算數(shù)運算）；含有連線；固定尺寸。18StandardCellLayoutMethodology–1980ssignalsRoutingchannelVDDGND19StandardCellLayoutMethodology–1990sM2NoRoutingchannelsVDDGNDM3VDDGNDMirroredCellMirroredCell20StandardCellsInOutVDDGND21StandardCellsAOutVDDGNDB2-inputNANDgate22StickDiagramsInOutVDDGNDInverterAOutVDDGNDBNAND223標(biāo)準(zhǔn)單元——OAI22ADBCCABX=(A+B)?(C+D)BADCDVDDXXGNDABCPUNPDNDLogicGraph24Multi-FingeredTransistorsOnefingerTwofingers(folded)Lessdiffusioncapacitance25PropertiesofComplementaryCMOSGatesHighnoisemargins；Nostaticpowerconsumption；Comparableriseandfalltimes.(underappropriatesizingconditions)266-2CMOS延遲時間工作模型；延遲時間輸入模式的關(guān)系；尺寸；扇入、扇出與延遲時間；高速設(shè)計技術(shù)27SwitchDelayModelAReqARpARpARnCLACLBRnARpBRpARnCintBRpARpARnBRnCLCintNAND2INVNOR228InputPatternEffectsonDelayDelayisdependentonthepatternofinputsLowtohightransitionbothinputsgolowdelayis0.69Rp/2CLoneinputgoeslowdelayis0.69RpCLHightolowtransitionbothinputsgohighdelayis0.692RnCLCLBRnARpBRpARnCint29DelayDependenceonInputPatternsA=B=10A=1,B=10A=10,B=1time[ps]Voltage[V]InputDataPatternDelay(psec)A=B=0164A=1,B=0161A=01,B=167A=B=1045A=1,B=1070A=10,B=181NMOS=0.5m/0.25mPMOS=0.75m/0.25mCL=100fF30TransistorSizing

CLBRnARpBRpARnCintBRpARpARnBRnCLCint22221144目標(biāo)：等同于反相器延遲時間；PUN與PDN延遲時間接近。31TransistorSizingaComplexCMOSGateOUT=D+A?(B+C)DABCDABC1222448832Fan-InConsiderationsDCBADCBACLC3C2C1DistributedRCmodel(Elmoredelay)tpHL=0.69Reqn(C1+2C2+3C3+4CL)Propagationdelaydeterioratesrapidlyasafunctionoffan-in–quadraticallyintheworstcase.33RCtreesGeneralizationofRCtransmissionline.34tpasaFunctionofFan-IntpLHtp(psec)fan-inGateswithafan-ingreaterthan4shouldbeavoided.tpHLquadraticlineartp35tpasaFunctionofFan-OuttpNOR2tp(psec)eff.fan-outAllgateshavethesamedrivecurrent.tpNAND2tpINVSlopeisafunctionof“drivingstrength”36tpasaFunctionofFan-InandFan-OutFan-in:quadraticduetoincreasingresistanceandcapacitanceFan-out:eachadditionalfan-outgateaddstwogatecapacitancestoCLtp=a1FI+a2FI2+a3FO376-3高速CMOS設(shè)計方法改變晶體管尺寸；重新安排輸入；重組邏輯結(jié)構(gòu)；隔離扇入-扇出。38FastComplexGates:DesignTechnique1改變晶體管尺寸InNCLC3C2C1In1In2In3M1M2M3MNDistributedRClineM1>M2>M3>…>MN

Canreducedelaybymorethan20%;39FastComplexGates:DesignTechnique2重新安排輸入。關(guān)鍵路徑—決定一個結(jié)構(gòu)最終速度的邏輯路徑。Placelatestarrivingsignal(criticalpath)closesttotheoutputC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcriticalpathcriticalpathcharged10

1chargedcharged1delaydeterminedbytimetodischargeCL,C1andC2delaydeterminedbytimetodischargeCL110

1chargeddischargeddischarged40FastComplexGates:DesignTechnique3重組邏輯結(jié)構(gòu)F=ABCDEFGH41FastComplexGates:DesignTechnique4Isolatingfan-infromfan-outusingbufferinsertionReduceCLonlargefan-ingates,especiallyforlargeCL.sizetheinvertersprogressivelytohandletheCLmoreeffectivelyCLCL426-4有比邏輯（RatioedLogic）有比邏輯偽NMOS差分串聯(lián)電壓開關(guān)邏輯（DCVSL）43RatioedLogicVDDVDDOUTOUT電阻型負(fù)載偽NMOS目的：減少晶體管數(shù)量44RatioedLogic——電阻型負(fù)載VDD45電阻型負(fù)載有比邏輯特點面積減?。ㄅcCMOS相比）靜態(tài)功耗不對稱延遲時間噪聲容限（輸出低電平不為VSS）46ActiveLoads——偽NMOSVDDPDN47Pseudo-nMOSUsesap-typeasaresistivepullup,n-typenetworkforpulldowns.48Characteristics面積減小靜態(tài)功耗（staticpower）不對稱延遲時間Pullup一直處于活動狀態(tài)Pulldowntime增加上升與下降時間不對稱噪聲容限（輸出低電平不為VSS）49OutputvoltagesLogic1outputisalwaysatVDD.Logic0outputisaboveVss.VOL=0.25(VDD-VSS).50Producingoutputvoltages分壓網(wǎng)絡(luò)選擇n,ptransistorsizes構(gòu)成等效電阻最壞情況—n-types串聯(lián).為使VOL小，PMOS尺寸應(yīng)明顯小于NMOS。上升延遲時間變大。51TransistorratiocalculationInsteadystatelogic0output:pullupisinsaturation,Vds=Vout-(VDD-VSS);pulldownisinlinearregion.Pullupandpulldownhavesamecurrentflowingthroughthem.Idp=Idd.Using0.5mmparameters,3.3Vpowersupply:Wp/Lp/Wn/Ln=3.9.52Pseudo-NMOS

withsamesize53Pseudo-NMOSVTC0.00.51.01.52.02.50.00.51.01.52.02.53.0Vin[V]Vout

[V]W/Lp=4W/Lp=2W/Lp=1W/Lp=0.25W/Lp=0.5W/Lp小

VOL小PMOS等效電阻增大下降延遲小PMOS影響減弱上升延遲加大54ImprovedLoads55DCVSL——

differentialcascadevoltageswitchlogic

ImprovedLoads

56DCVSstructure57DCVSlogic靜態(tài)功耗nostaticpower.互鎖Useslatchtocomputeoutputquickly.互補輸入/輸出Requirestrue/complementinputs,producestrue/complementoutputs.互補輸出具有相同的延遲時間。58DCVSexample59DCVSLExample60DCVSLExampleABA，B，（AB)’AB61DCVSLTransientResponse00.20.40.60.81.0-0.50.51.52.5Time[ns]Voltage[V]ABABA,BA,B62DCVS的特點差分（互補）輸出節(jié)省反相器產(chǎn)生額外輸出差分（互補）輸出具有相同的時間延遲與CMOS加反相器相比有比邏輯布線復(fù)雜636-5傳輸管邏輯(Pass-TransistorLogic)NMOS電平恢復(fù)CMOSTG64Pass-TransistorLogic65Typesofswitches66Behaviorofn-typeswitchconductslogic0perfectly;introducesthresholddropintologic1.VDDVDDVDD-Vt67VDD-VtVDDVDDVDD-VtVDDVDD-VtVDDVDD-2VtVDD68Example:ANDGate69NMOS-OnlyLogic00.511.520.01.02.03.0Time[ns]Voltage

[V]xOutIn70NMOS-onlySwitchA=2.5VBC=2.5

VCLA=2.5VC=2.5VBM2M1MnThresholdvoltagelosscausesstaticpowerconsumptionVBdoesnotpullupto2.5V,but2.5V-VTNNMOShashigherthresholdthanPMOS(bodyeffect)71NMOSOnlyLogic:LevelRestoringTransistorM2M1MnMrOutABVDDVDDLevelRestorerX電平恢復(fù)(B=1)輸入=0，X=0，OUT=VDD；輸入=0VDD，X=VDD-Vtn，OUT=low，Mr導(dǎo)通，X=VDD，OUT=0。復(fù)雜度提高有比邏輯輸入=VDD0

，X=VDD

0

，Mr已經(jīng)導(dǎo)通，X上拉，Mr、Mn有比。若Mn下拉強于Mr上拉，則X=0

，OUT=VDD。尺寸：Rn<<Rr，即Mr小于Mn尺寸。72LevelRestorer?Advantage:FullSwing?Restoreraddscapacitance,takesawaypulldowncurrentatX。放電時間加長，減慢速度。?Ratioproblem73RestorerSizing01002003004005000.01.02.0W/Lr=1.0/0.25W/Lr=1.25/0.25W/Lr=1.50/0.25W/Lr=1.75/0.25Voltage[V]Time[ps]3.0A=0時，Mn與Mr構(gòu)成有比網(wǎng)絡(luò)Upperlimitonrestorersize74ComplementaryPassTransistorLogic

晶體管數(shù)量減少；輸出互補，同步。75傳輸門(TransmissionGate)ABCCABCCBCLC

=0VA=2.5VC=2.5V76BehaviorofcomplementaryswitchComplementaryswitchproductsfull-supplyvoltagesforbothlogic0andlogic1:n-typetransistorconductslogic0;p-typetransistorconductslogic1.77ResistanceofTransmissionGate7879TransmissionGateXORABFBABBM1M2M3/M4B=1F=A’BB=0F=AB’6個晶體管(含B’產(chǎn)生）CMOS實現(xiàn)需要12個。80ABX=AB’+A’BBAB’A’B’A’X=AB’+A’B???81BX=AB’+A’BBAB’A’B’A’AX=AB’+A’B=(AB’)(A’B)

=（A’+B)(A+B’）826-6動態(tài)CMOS設(shè)計動態(tài)邏輯(DynamicLogic)特點問題電荷泄漏電荷分享電容耦合時鐘饋通83DynamicCMOSInstaticcircuitsateverypointintime(exceptwhenswitching)theoutputisconnectedtoeitherGNDorVDDviaalowresistancepath.fan-inofnrequires2n(nN-type+nP-type)devicesDynamiccircuitsrelyonthetemporarystorageofsignalvaluesonthecapacitanceofhighimpedancenodes.requiresonn+2(n+1N-type+1P-type)transistors84DynamicGateIn1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwophaseoperation預(yù)充電—Precharge(CLK=0)；求值——Evaluate(CLK=1)。85DynamicGateIn1In2PDNIn3MeMpClkClkOutCLOutClkClkABCMpMeTwophaseoperation

Precharge(Clk=0)

Evaluate(Clk=1)onoff1offon((AB)+C)Out=CLK+(AB+C)·CLK86ConditionsonOutputOncetheoutputofadynamicgateisdischarged,itcannotbechargedagainuntilthenextprechargeoperation.Inputstothegatecanmakeatmost

onetransitionduringevaluation.Outputcanbeinthehighimpedancestateduringandafterevaluation(PDNoff),stateisstoredonCL87特點LogicfunctionisimplementedbythePDNonlynumberoftransistorsisN+2(versus2NforstaticcomplementaryCMOS)Fullswingoutputs(VOL=GNDandVOH=VDD)無比的邏輯Non-ratioedPMOS尺寸影響上升時間，不影響邏輯功能。Fasterswitchingspeeds晶體管數(shù)目減少lowerinputcapacitance(Cin)smalleroutputloading(Cout)無短路電流，PDN提供的電流用于對CL放電。88電荷泄漏（ChargeLeakage）CLClkClkOutAMpMeLeakagesourcesCLKVOutPrechargeEvaluateDominantcomponentissubthresholdcurrent（亞閾值電流和反偏二極管）Requiresaminimumclockrate!!89SolutiontoChargeLeakageCLClkClkMeMpABOutMkpSameapproachaslevelrestorerforpass-transistorlogicKeeper90電荷分享（ChargeSharing）求值期間，若B=0，A=0->1電荷分享sharedoverCLandCA降低輸出電壓水平，reducedrobustness

。CLClkClkCACBB=0AOutMpMe91ChargeSharingB=0ClkXCLCaCbAOutMpMaVDDMbClkMeVout(Ca+CL)=VDD*CLMa一直導(dǎo)通92邊界條件?Vout=Vtn對應(yīng)電容比Ca/CL=Vtn/(Vdd-Vtn)電容比小時,電壓下降小于Vtn電容比大時,Vout=Vx>Vtn93ChargeSharingExampleCL=50fFClkClkAABBB!BCCOutCa=15fFCc=15fFCb=15fFCd=10fFOut=AxorBxorC30/(30+50)*2.5V=0.94Vsotheoutputdropsto2.5-0.94=1.56Vwhen!ABCorA!BC94SolutiontoChargeRedistributionClkClkMeMpABOutMkpClkPrechargeinternalnodes

Price:increasedareaandpower95回柵電容耦合（BackgateCoupling）CL1ClkClkB=0A=0Out1MpMeOut2CL2InDynamicNANDStaticNAND=1=0In為1時——OUT2變0——電容耦合——Out1顯著降低——OUT2不能到VSS。96BackgateCouplingEffectVoltageTime,nsClkInOut1Out297時鐘饋通（ClockFeedthrough）CLClkClkBAOutMpMeCouplingbetweenOutandClkgatetodraincapacitanceThefastrising(andfallingedges)oftheclockcoupletoOutvoltageofOutcanriseaboveVDD..98ClockFeedthroughClkClkIn1In2In3In4OutIn&ClkOutTime,nsVoltageClockfeedthroughClockfeedthrough996-6串聯(lián)動態(tài)門（CascadingDynamicGates）直接串聯(lián)動態(tài)門多米諾（骨牌）邏輯100直接串聯(lián)動態(tài)門ClkClkOut1InMpMeMpMeClkClkOut2VtClkInOut1Out2

VVTn101OUT2電荷由于NMOS導(dǎo)通而產(chǎn)生損失——電平下降電平損失原因——輸入在預(yù)充電期間為“1”，求值開始時造成無意的放電。動態(tài)門直接串聯(lián)——不可行。改進方法：預(yù)充電期間輸入為“0”，求值期間只進行0—>1的翻轉(zhuǎn)。102DominoLogicIn1In2PDNIn3MeMpClkClkOut1In4PDNIn5MeMpClkClkOut2Mkp11100001103WhyDomino?ClkClkIniPDNInjIniInjPDNIniPDNInjIniPDNInjLikefallingdominos!104DominoeffectGateoutputsfallinsequence:gate1gate2gate3105DominoManchesterCarryChainCi,0G0CLKCLKP0P1P2P3G1G2G3Ci,4!(G0+P0Ci,0)!(G1+P1G0+P1P0Ci,0)P：PassingG：Generating？？106DominoZeroDetectorCLKIn7In6In5In4In3In2In0In1notzero107CLKA3B3A2B2A1B1A0B0OutDominoComparator108PropertiesofDominoLogic提高了抗噪聲能力VeryhighspeedonlyL-Htransi