Xilinx FPGA普通IO作PLL時鐘輸入

XilinxFPGA普通IO作PLL時鐘輸入在xilinxZC7020的片子上做的實(shí)驗(yàn);[結(jié)論]普通IO不能直接作PLL的時鐘輸入,專用時鐘管腳可以;普通IO可以通過BUFG再連到PLL的時鐘輸入上,但要修改PLL的設(shè)置inputclk的選項(xiàng)中要選擇"NoBuffer";具體內(nèi)部布局分配可以通過Xilinx的FPGAEditor來查看,ZYNQ的時鐘管理也和之前的片子略有不同,之后在另一篇介紹,相關(guān)文檔[Demo1]

//demo1twobufgconnectmoduleiobuf(inputclk,inputrst,outputled);wireclkin_w;BUFGBUFG_inst(.O(clkin_w),//Clockbufferoutput.I(clk)//Clockbufferinput);pll0u_pll0(.CLK_IN1(clkin_w),//IN.CLK_OUT1(clkout),//OUT.RESET(rst));//INassignled=clkout;endmodule鎖相環(huán)PLL默認(rèn)輸入前端有個BUFG單元,而兩個BUFG不能相連,所以會報(bào)這樣的錯:ERROR:NgdBuild:770-IBUFG'u_pll0/clkin1_buf'andBUFG'BUFG_inst'onnet'clkin_w'arelinedupinseries.Buffersofthesamedirectioncannotbeplacedinseries.ERROR:NgdBuild:924-inputpadnet'clkin_w'isdrivingnon-bufferprimitives:[Demo2]//demo2regulariodirectlyconnecttoPLLmoduleiobuf(inputclk,inputrst,outputled);

wireclkin_w;/*BUFGBUFG_inst(.O(clkin_w),//Clockbufferoutput.I(clk)//Clockbufferinput);*/pll0u_pll0(.CLK_IN1(clk),//IN.CLK_OUT1(clkout),//OUT.RESET(rst));//INassignled=clkout;endmodule普通IO不能直接做鎖相環(huán)的輸入,所以會報(bào)這樣的錯:ERROR:Place:1397-AclockIOB/MMCMclockcomponentpairhavebeenfoundthatarenotplacedatanoptimalclockIOB/MMCMsitepair.TheclockIOBcomponentisplacedatsite.ThecorrespondingMMCMcomponentisplacedatsite.TheclockIOcanusethefastpathbetweentheIOBandtheMMCMiftheIOBisplacedonaClockCapableIOBsitethathasdedicatedfastpathtoMMCMsiteswithinthesameclockregion.Youmaywanttoanalyzewhythisproblemexistsandcorrectit.Ifthissuboptimalconditionisacceptableforthisdesign,youmayusetheCLOCK_DEDICATED_ROUTEconstraintinthe.ucffiletodemotethismessagetoaWARNINGandallowyourdesigntocontinue.However,theuseofthisoverrideishighlydiscouragedasitmayleadtoverypoortimingresults.Itisrecommendedthatthiserrorconditionbecorrectedinthedesign.AlistofalltheCOMP.PINsusedinthisclockplacementruleisERROR:Pack:1654-Thetiming-drivenplacementphaseencounteredanerror.如果有ucf中加上這句約束:NETclkCLOCK_DEDICATED_ROUTE=FALSE;依舊會報(bào)錯,在ZYNQ7000系列,這樣還是通不過,如下:ERROR:PhysDesignRules:2256-UnsupportedMMCME2_ADVconfiguration.Thesignalu_pll0/clkin1ontheCLKIN1pinofMMCME2_ADVcompu_pll0/mmcm_adv_instwithCOMPENSATIONmodeZHOLDmustbedrivenbyaclockcapableIOB.ERROR:Pack:1642-ErrorsinphysicalDRC.使用普通的IO,再連接bufg來連到時鐘線上,仍會報(bào)這樣的錯誤,因?yàn)檫€是兩bufg相連了:ERROR:NgdBuild:770-IBUFG'u_pll0/clkin1_buf'andBUFG'BUFG_inst'onnet'clkin_w'arelinedupinseries.Buffersofthesamedirectioncannotbeplacedinseries.ERROR:NgdBuild:924-inputpadnet'clkin_w'isdrivingnon-bufferprimitives:[Demo3]

//dem3regulariowithBUFGthenconnecttoPLLwhichwith"NoBuffer"settingmoduleiobuf(inputclk,inputrst,outputled);wireclkin_w;BUFGBUFG_inst(.O(clkin_w),//Clockbufferoutput.I(clk)//Clockbufferinput);pll0u_pll0(.CLK_IN1(clkin_w),//IN.CLK_OUT1(clkout),