用verilog HDL設(shè)計(jì)的4位頻率計(jì)

./簡(jiǎn)單4位數(shù)字頻率計(jì)設(shè)計(jì)設(shè)計(jì)要求〔1、利用VerilogHDL語言行為描述方法,設(shè)計(jì)一個(gè)簡(jiǎn)單的4位數(shù)字頻率計(jì)；〔2、要求輸入標(biāo)準(zhǔn)時(shí)鐘信號(hào)頻率為1MHz,系統(tǒng)可計(jì)數(shù)頻率圍為1Hz~9999Hz；〔3、系統(tǒng)具有復(fù)位信號(hào),且當(dāng)計(jì)數(shù)頻率發(fā)生溢出時(shí)能夠給出指示信號(hào),計(jì)數(shù)的頻率通過4個(gè)共陰數(shù)碼管進(jìn)行顯示〔動(dòng)態(tài)掃描顯示。系統(tǒng)結(jié)構(gòu)框圖根據(jù)設(shè)計(jì)要求,輸入系統(tǒng)的標(biāo)準(zhǔn)時(shí)鐘信號(hào)要先經(jīng)過分頻后得到一個(gè)周期為2s占空比50%的信號(hào),用來對(duì)輸入信號(hào)采樣,得到采樣信號(hào)GATED_CLK；為了能夠控制計(jì)數(shù)模塊對(duì)采樣的信號(hào)進(jìn)行正常計(jì)數(shù)及保存計(jì)數(shù)后的頻率,這要求,要在計(jì)數(shù)器剛好完成計(jì)數(shù)后立即將數(shù)據(jù)輸出給顯示部分進(jìn)行顯示,并且要為下次計(jì)數(shù)做好準(zhǔn)備,因此數(shù)據(jù)信號(hào)處理部分還要有產(chǎn)生控制計(jì)數(shù)器的兩個(gè)信號(hào)LOAD和COUNTER_CLR,LOAD信號(hào)控制計(jì)數(shù)完成后的數(shù)據(jù)及時(shí)輸出給顯示,COUNTER_CLR信號(hào)控制計(jì)數(shù)器清零；計(jì)數(shù)模塊就是完成對(duì)采樣信號(hào)的計(jì)數(shù),并當(dāng)計(jì)數(shù)發(fā)生溢出時(shí)產(chǎn)生溢出信號(hào)FLOW_UP；顯示控制模塊要完成將計(jì)數(shù)模塊輸入的信號(hào)進(jìn)行譯碼顯示。信號(hào)描述測(cè)試信號(hào)采樣原理：GATED_CLK、LOAD、COUNTER_CLR信號(hào)的關(guān)系：程序中用到的信號(hào)變量：FREQUENCY_COUNTROL_BLOCKFREQUENCY_COUNTER_BLOCKFREQUENCY_DISPLY_BLOCKGATED_CLK采樣信號(hào)COUT計(jì)數(shù)輸出信號(hào)DOUT輸出到數(shù)碼管LOAD控制計(jì)數(shù)器信號(hào)FLOW_UP計(jì)數(shù)溢出信號(hào)CDIN計(jì)數(shù)輸入信號(hào)COUNTER_CLR清零計(jì)數(shù)器信號(hào)CLOCK_IN計(jì)數(shù)器時(shí)鐘信號(hào)DCLK_IN標(biāo)準(zhǔn)時(shí)鐘信號(hào)CLK_IN標(biāo)準(zhǔn)時(shí)鐘信號(hào)LOAD控制計(jì)數(shù)輸出RESET復(fù)位信號(hào)SIGNAL_TEST測(cè)試信號(hào)COUNTER_CLR清零計(jì)數(shù)信號(hào)RESET復(fù)位信號(hào)RESET復(fù)位信號(hào)Verilog程序各子模塊verilog程序：〔1信號(hào)處理模塊_verilog：moduleFREQUENCY_COUNTROL_BLOCK<GATED_CLK,LOAD,COUNTER_CLR,CLK_IN,SIGNAL_TEST,RESET>; outputGATED_CLK; outputLOAD; outputCOUNTER_CLR; inputCLK_IN; inputSIGNAL_TEST; inputRESET; regLOAD; regCOUNTER_CLR; regDIVIDE_CLK; reg[19:0]; regA1,A2;//信號(hào)分頻：由CLK_IN得到分頻后的信號(hào)DIVIDE_CLK<0.5Hz> always<posedgeCLK_IN> begin if<RESET> begin DIVIDE_CLK<=0; cn<=0; end elseif<cn==1000000> begin cn<=0; DIVIDE_CLK<=~DIVIDE_CLK; end else cn<=cn+1; end //頻率計(jì)數(shù)控制信號(hào)的產(chǎn)生：產(chǎn)生LOAD信號(hào)和COUNTER_CLR信號(hào)always<posedgeSIGNAL_TEST> begin A1<=~DIVIDE_CLK; end always<posedgeSIGNAL_TEST> begin A2=A1; end always<A1orA2> begin LOAD=A1&&<!A2>; end always<posedgeSIGNAL_TEST> COUNTER_CLR=LOAD;//產(chǎn)生驅(qū)動(dòng)計(jì)數(shù)模塊的信號(hào)GATED_CLK,也就是被計(jì)數(shù)模塊檢測(cè)的信號(hào) assignGATED_CLK=SIGNAL_TEST&DIVIDE_CLK; endmodule〔2、計(jì)數(shù)器模塊：moduleFREQUENCY_COUNTER_BLOCK<COUT,FLOW_UP,CLOCK_IN,RESET,LOAD,COUNTER_CLR>; output[15:0]COUT; outputFLOW_UP; inputCLOCK_IN; inputLOAD; inputCOUNTER_CLR; inputRESET; reg[15:0]TEMP; regFLOW_UP; parameterB_SIZE=16;//二進(jìn)制位寬,為便于移植,所有定義了成參數(shù) reg[B_SIZE+3:0]bcd;//轉(zhuǎn)換后的BCD碼的位數(shù)要比二進(jìn)制多4位 reg[B_SIZE-1:0]binary; reg[B_SIZE-1:0]bin; reg[B_SIZE+3:0] result;//計(jì)數(shù)器完成計(jì)數(shù)得到二進(jìn)制表示的頻率數(shù)值 always<CLOCK_INorRESETorLOADorCOUNTER_CLR> begin if<RESET|COUNTER_CLR> begin TEMP<=0; FLOW_UP<=0; end elseif<LOAD> binary<=TEMP; elseif<TEMP>9999> begin FLOW_UP<=1; binary<=9999; end else if<CLOCK_IN> TEMP<=TEMP+1; end //將二進(jìn)制表示〔或十六進(jìn)制表示的數(shù)轉(zhuǎn)換為BCD碼的形式,便于數(shù)碼管譯碼顯示 always<binaryorRESET> begin bin=binary; result=0; if<RESET> bcd<=0; else begin repeat<B_SIZE-1> begin result[0]=bin[B_SIZE-1]; if<result[3:0]>4> result[3:0]=result[3:0]+4'd3; if<result[7:4]>4> result[7:4]=result[7:4]+4'd3; if<result[11:8]>4> result[11:8]=result[11:8]+4'd3; if<result[15:12]>4> result[15:12]=result[15:12]+4'd3; if<result[19:16]>4> result[19:16]=result[19:16]+4'd3; result=result<<1; bin=bin<<1; end result[0]=bin[B_SIZE-1]; bcd<=result; end end assignCOUT=bcd[15:0];endmodule〔3信號(hào)顯示處理：moduleFREQUENCY_DISPLY_BLOCK<DOUT,DCLK_IN,RESET,CDIN>; output[10:0]DOUT; input[15:0]CDIN; inputDCLK_IN; inputRESET; reg[10:0]DOUT; reg[3:0]Temp1; reg[1:0]; always<posedgeDCLK_IN>//設(shè)置成動(dòng)態(tài)掃描 begin if<RESET> cn<=0; else begin cn<=cn+1; case<cn> 2'b00:beginDOUT[10:7]<=4'b0001;Temp1<=CDIN[3:0];end 2'b01:beginDOUT[10:7]<=4'b0010;Temp1<=CDIN[7:4];end 2'b10:beginDOUT[10:7]<=4'b0100;Temp1<=CDIN[11:8];end 2'b11:beginDOUT[10:7]<=4'b1000;Temp1<=CDIN[15:12];end endcase end end always<Temp1>//譯碼顯示 begin case<Temp1> 4'b0000:DOUT[6:0]<=7'b0111111;//3fh=0 4'b0001:DOUT[6:0]<=7'b0000110;//06h=1 4'b0010:DOUT[6:0]<=7'b1010110;//56h=2 4'b0011:DOUT[6:0]<=7'b1001111;//4fh=3 4'b0100:DOUT[6:0]<=7'b1100110;//66h=4 4'b0101:DOUT[6:0]<=7'b1101101;//6dh=5 4'b0110:DOUT[6:0]<=7'b1111101;//7dh=6 4'b0111:DOUT[6:0]<=7'b0000111;//07h=7 4'b1000:DOUT[6:0]<=7'b1111111;//7fh=8 4'b1001:DOUT[6:0]<=7'b1101111;//6fh=9 default:DOUT[6:0]<=7'b0111111;//3fh endcase end endmodule頂層verilog程序：moduleFREQUENCY_COUNTER_DISPLY_BLOCK<DOUT,FLOW_UP,CLK,TEST_CLK_IN,RESET>; output[10:0]DOUT; outputFLOW_UP; inputCLK; inputTEST_CLK_IN; inputRESET; wiregated_clk,load,counter_clr; wire[15:0]cout_cdin; FREQUENCY_COUNTROL_BLOCKu1<.GATED_CLK<gated_clk>,.LOAD<load>,.COUNTER_CLR<counter_clr>,.CLK_IN<CLK>,.SIGNAL_TEST<TEST_CLK_IN>,.RESET<RESET>>; FREQUENCY_COUNTER_BLOCKu2<.COUT<cout_cdin>,.FLOW_UP<FLOW_UP>,.CLOCK_IN<gated_clk>,.RESET<RESET>,.LOAD<load>,.COUNTER_CLR<counter_clr>>; FREQUENCY_DISPLY_BLOCKu3<.DOUT<DOUT>,.DCLK_IN<CLK>,.RESET<RESET>,.CDIN<cout_cdin>>;endmodule仿真結(jié)果分析仿真結(jié)果如圖所示,輸入標(biāo)準(zhǔn)時(shí)鐘頻率為1MHz,經(jīng)過分頻后變成頻率為0.5Hz的信號(hào),將其與測(cè)試信號(hào)相與得到采樣信號(hào)GATED_CLK,同時(shí)利用測(cè)試信號(hào)和0.5Hz的分頻信號(hào)