實(shí)驗(yàn)二-用七段LED顯示8421BCD碼的VHDL設(shè)計(jì)

EDA實(shí)驗(yàn)報(bào)告〔二〕實(shí)驗(yàn)地點(diǎn)：211大樓606&609任課教師：竇衡學(xué)生姓名：李志學(xué)號：2402401024實(shí)驗(yàn)二用七段LED顯示8421BCD碼的VHDL設(shè)計(jì)一、預(yù)習(xí)內(nèi)容1、結(jié)合附錄一了解EDA實(shí)驗(yàn)箱的原理；2、七段LED顯示原理；3、怎樣用VHDL實(shí)現(xiàn)8421BCD碼在七段LED數(shù)碼管上顯示。二、實(shí)驗(yàn)?zāi)康牧私釼HDL進(jìn)行EDA設(shè)計(jì)的根本步驟；學(xué)會用MAX+PLUSⅡ進(jìn)行時(shí)序仿真；了解EDA實(shí)驗(yàn)箱的根本功能；三、實(shí)驗(yàn)器材PC機(jī)一臺、EDA教學(xué)實(shí)驗(yàn)系統(tǒng)一臺、下載電纜一根〔已接好〕、導(dǎo)線假設(shè)干四、實(shí)驗(yàn)內(nèi)容用VHDL設(shè)計(jì)具有去除端、使能端，計(jì)數(shù)范圍為0~999的計(jì)數(shù)器設(shè)計(jì)。輸出為8421BCD碼；用VHDL設(shè)計(jì)七段LED譯碼顯示電路；MAX+PLUSⅡ進(jìn)行時(shí)序仿真；下載該程序驗(yàn)證程序是否正確；請事先準(zhǔn)備一個(gè)軟盤或優(yōu)盤，本實(shí)驗(yàn)程序需要保存，后面實(shí)驗(yàn)需要用到。五、實(shí)驗(yàn)步驟1、寫出七段譯碼器和具有去除端、使能端，計(jì)數(shù)范圍為0~999的計(jì)數(shù)器的VHDL源程序，編譯通過；2、進(jìn)行波形仿真；3、選定器件、映射管腳、編譯、下載。六、實(shí)驗(yàn)原理和設(shè)計(jì)1、8421BCD編碼在數(shù)字系統(tǒng)中常用四位二進(jìn)制代碼來表示一位十進(jìn)制數(shù)字0、1、2、﹒﹒﹒、9，稱之為二－十進(jìn)制代碼，即BCD碼。將十進(jìn)制數(shù)編成BCD碼的電路，稱為稱二－十進(jìn)制〔BCD〕編碼器。二-十進(jìn)制編碼的方案很多，假設(shè)BCD編碼器采用8421編碼方案，稱為8421BCD編碼器。2、七段譯碼器下列圖為譯碼器邏輯圖，請按圖進(jìn)行連線。其中A，B，C，D接撥號開關(guān)，a，b，c，d，e，f，g接數(shù)碼顯示接口，管腳映射均為I/O口，映射后，通過撥號開關(guān)改變輸入二進(jìn)制碼，那么輸出數(shù)碼管上顯示相應(yīng)的數(shù)值。譯碼器真值表數(shù)值輸入輸出ABCDabcdefg000001111110100010110000200101101101300111111001401000110011501011011011601101011111701111110000810001111111910011111011A10101110111B10110011111C11001001110D11010111101E11101001111F111110001113、實(shí)現(xiàn)框圖4、VHDL源程序：--0-999BCD碼計(jì)數(shù)器描述LIBRARYIEEE;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;EntityCOUNT100IsPort(Clk,Rst,En,Load:instd_logic;data1,data2,data3:instd_logic_vector(3downto0);conl,conm,conh:bufferstd_logic_vector(3downto0));EndCOUNT100;ArchitectureCOUNTofCOUNT100IsBeginprocess(Rst,Clk)beginifRst='1'thenconl<="0000";conm<="0000";conh<="0000";elsifrising_edge(Clk)thenifEn='1'thenconl<=conl;conh<=conh;conm<=conm;elsifLoad='1'thenconl<=data1;conm<=data2;conh<=data3;elsif(conl="1001"andconm="1001"andconh="1001")thenconl<="0000";conm<="0000";conh<="0000";elsifconl="1001"thenifconm="1001"thenconl<="0000";conm<="0000";conh<=conh+1;elseconm<=conm+1;conl<="0000";endif;elseconl<=conl+1;endif;endif;endprocess;EndCOUNT;--七段譯碼器描述libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityseven_codeisport(count:instd_logic_vector(3downto0);scode:outstd_logic_vector(6downto0));endseven_code;architecturebehaveofseven_codeisbeginprocess(count)begincasecountiswhen"0000"=>scode<="1111110";when"0001"=>scode<="0110000";when"0010"=>scode<="1101101";when"0011"=>scode<="1111001";when"0100"=>scode<="0110011";when"0101"=>scode<="1011011";when"0110"=>scode<="1011000";when"0111"=>scode<="1110000";when"1000"=>scode<="1111111";when"1001"=>scode<="1111011";whenothers=>scode<="0000000";endcase;endprocess;endbehave;七、試驗(yàn)結(jié)果及總結(jié)1、系統(tǒng)仿真情況：計(jì)數(shù)器時(shí)序仿真結(jié)果如下列圖所示系統(tǒng)時(shí)序仿真結(jié)果如下列圖所示2、結(jié)果分析：由系統(tǒng)時(shí)序仿真結(jié)果可以看出，本系統(tǒng)符合設(shè)計(jì)要求，計(jì)數(shù)器的三位計(jì)數(shù)值由七段譯碼器譯碼輸出。八、實(shí)驗(yàn)心得體會通過這次試驗(yàn)我了解了VHDL進(jìn)行EDA設(shè)計(jì)的根本步驟，學(xué)會了用MAX+PLUSⅡ進(jìn)行時(shí)序仿真，了解了EDA實(shí)驗(yàn)箱的根本功能。九、問題及思考如果要求譯出0～9和‘－’，程序該如何修改呢？libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityseven_codeisport(count:instd_logic_vector(3downto0);scode:outstd_logic_vector(6downto0));endseven_code;architecturebehaveofseven_codeisbeginprocess(count)begincasecountiswhen"0000"=>scode<="1111110";when"0001"=>scode<="0110000";when"0010"=>scode<="1101101";when"0011"=>scode<="1111001";when"0100"=>scode<="0110011";when"0101"=>scode<="1011011";when"0110"=>s