verilog編寫的基本電路邏輯及仿真

1、集成電路與Verilog語言 實(shí)驗(yàn)1：分別用門級(jí)建模、數(shù)據(jù)流級(jí)建模、和行為級(jí)建模實(shí)現(xiàn)一個(gè)2選1的MUX，兩個(gè)輸入端分別為A和B，當(dāng)選擇端SEL=0時(shí)，輸出F選擇A；當(dāng)選擇端SEL=1時(shí)，輸出F選擇B。ABSEL門級(jí)建模：源代碼：/MUX2to1 gatelevelmodule MUX_gate(a,b,sel,f); input a; input b; input sel; output f; reg f;wire nsel,y1,y2;not unot(nsel,sel);and u1and(y1,a,nsel);and u2and(y2,b,sel);or uor(f,y1,y2);end

2、module綜合結(jié)果：TB代碼：module tb_MUX_gate;/ Inputsreg a;reg b;reg sel;/ Outputswire f;/ Instantiate the Unit Under Test (UUT)MUX_gate uut (.a(a), .b(b), .sel(sel), .f(f);initial begin/ Initialize Inputsa = 0;b = 0;sel = 0;/ Wait 100 ns for global reset to finish#10/ Add stimulus herea=1;b=0;sel=0;#10; a=1;

3、b=0;sel=1;#10;#10$finish;endendmodule仿真結(jié)果：數(shù)據(jù)流級(jí)建模：源代碼：/MUX2to1 datapromodule MUX_datapro(a,b,sel,f); input a; input b; input sel; output f;reg f;wire nsel,y1,y2;assign nsel=sel;assign y1=a&nsel;assign y2=b&sel;assign f=y1|y2; endmodule綜合結(jié)果：TB代碼：module tb_MUX_datarpro;/ Inputsreg a;reg b;reg sel;/ Out

4、putswire f;/ Instantiate the Unit Under Test (UUT)MUX_datapro uut (.a(a), .b(b), .sel(sel), .f(f);initial begin/ Initialize Inputsa = 0;b = 0;sel = 0;/ Wait 100 ns for global reset to finish#10; / Add stimulus herea=1;b=0;sel=0;#10; a=1;b=0;sel=1;#10;#10$finish;enendmodule仿真結(jié)果：行為級(jí)建模：源代碼：/MUX2to1 beh

5、avmodule MUX_behav(f,a,b,sel);input a,b,sel;output f;reg f;reg y1,y2,nsel;always (a or b or sel)begin nsel =sel; y1 = a&nsel; y2 = b&sel; f = y1|y2; endendmodule綜合結(jié)果：TB代碼：module tb_MUX_behav;/ Inputsreg a;reg b;reg sel;/ Outputswire f;/ Instantiate the Unit Under Test (UUT)MUX_behav uut (.a(a), .b(b

6、), .sel(sel), .f(f);initial begin/ Initialize Inputsa = 0;b = 0;sel = 0;/ Wait 100 ns for global reset to finish#10; / Add stimulus herea=1;b=0;sel=0;#10; a=1;b=0;sel=1;#10;#10$finish;end endmodule仿真結(jié)果：實(shí)驗(yàn)2題目：實(shí)現(xiàn)一個(gè)計(jì)數(shù)器，計(jì)數(shù)時(shí)計(jì)數(shù)器可從0計(jì)到10。源代碼：module counter(din,up1_down0,clk,nrst,sta1_pau0,load,counter); inp

7、ut3:0 din; input up1_down0; input clk; input nrst; input sta1_pau0; input load; output 3:0 counter; reg 3:0 counter;always (posedge clk or negedge nrst)begin if(nrst) counter = 4b0000; else if(load) counter = din; else begin if(sta1_pau0) counter = counter; else if(up1_down0) if (counter = 10) count

8、er = 4b0000; else counter = counter + 1;else if (counter = 0) counter = 4b1010; else counter = counter - 1; end endendmodule綜合結(jié)果：TB代碼：module tb2;/ Inputsreg 3:0 din;reg up1_down0;reg clk;reg nrst;reg sta1_pau0;reg load;/ Outputswire 3:0 counter;/ Instantiate the Unit Under Test (UUT)counter uut (.di

9、n(din), .up1_down0(up1_down0), .clk(clk), .nrst(nrst), .sta1_pau0(sta1_pau0), .load(load), .counter(counter); initial clk = 1b0; always #5 clk = clk;initial begin/ Initialize Inputsdin = 0;up1_down0 = 0;nrst = 0; sta1_pau0 = 0;load = 0;/ Wait 100 ns for global reset to finish#50;/ Add stimulus here/

10、從0開始加計(jì)數(shù) din = 4b0111;nrst = 1; up1_down0 = 1;sta1_pau0 = 1;#210;/暫停sta1_pau0 = 0; #20;/從7開始減計(jì)數(shù)load = 1; #10; load = 0;sta1_pau0 = 1; up1_down0 = 0;#200;#20 $finish;end endmodule仿真結(jié)果：實(shí)驗(yàn)3題目：由Morre狀態(tài)機(jī)設(shè)計(jì)一個(gè)簡(jiǎn)單的交通燈，假定紅燈時(shí)間為9個(gè)時(shí)間單位，綠燈時(shí)間為6個(gè)時(shí)間單位，黃燈時(shí)間為3個(gè)時(shí)間單位。源代碼：module light_machine(clk,nrst,y,t); input clk; inp

11、ut nrst; output 1:0 y; output 3:0 t; reg 3:0 q; reg 1:0 y; reg 1:0 state; reg 3:0 t; parameter green = 2b00,yellow = 2b01,red = 2b11;initial begin q = 4b0; t = 4b0;endalways (posedge clk or negedge nrst)begin if(!nrst) begin state = green; y = 2bz; end else case(state) green: begin q = q +1; t = q;

12、if(q = 5) begin q = 4b0; state = yellow; end else begin y = 2b00; state = green; end end yellow: begin q = q +1; t = q; if (q = 2) begin q = 4b0; state = red;end else begin y = 2b01; state = yellow; end end red: begin q = q + 1; t = q; if (q = 8) begin q = 4b0; state = green;end else beginy = 2b11;s

13、tate = red;end end endcaseendendmodule綜合結(jié)果：TB代碼：module tb_2;/ Inputsreg clk;reg nrst;/ Outputswire 1:0 y;wire 3:0 t;/ Instantiate the Unit Under Test (UUT)light_machine uut (.clk(clk), .nrst(nrst), .y(y), .t(t); initial clk = 1b0; always #5 clk = clk; initial begin/ Initialize Inputsnrst = 0;/ Wait

14、100 ns for global reset to finish#30; / Add stimulus herenrst = 1;#500;#20$finish;end endmodule仿真結(jié)果：實(shí)驗(yàn)4題目：對(duì)一個(gè)400MHz的時(shí)鐘分別完成2、4、8分頻。源代碼：module divclk(clkin,nrst,din, clkout); input clkin; input nrst; input 1:0 din; output clkout; reg 28:0 q; reg clkout; initialbegin q =29b0;end always (posedge clkin o

15、r negedge nrst)begin if(nrst) q = 29b0; else q = q + 29b1; endalways (posedge clkin)begin case(din) 2b00: clkout = q0; 2b01: clkout = q1; 2b10: clkout = q2; default: clkout = 1bz; endcaseendendmodule綜合結(jié)果：TB文件：module tb_div;/ Inputsreg clkin;reg nrst;reg 1:0 din;/ Outputswire clkout;/ Instantiate the

16、 Unit Under Test (UUT)divclk uut (.clkin(clkin), .nrst(nrst), .din(din), .clkout(clkout); initial clkin = 1b0; always #1.25 clkin = clkin; initial begin/ Initialize Inputsnrst = 0;din = 2b11;/ Wait 100 ns for global reset to finish#50; / Add stimulus herenrst = 1;din = 2b00;#50;din = 2b01;#50;din =

17、2b10;#50;din = 2b11;#50;#20$finish;end endmodule仿真結(jié)果：實(shí)驗(yàn)5題目：按照病情嚴(yán)重程度將8名病人分配到8個(gè)病房，1號(hào)病房病情最輕，8號(hào)病房病人病情最嚴(yán)重。每個(gè)病房有一個(gè)按鈕用于呼叫醫(yī)生，在醫(yī)生辦公室有個(gè)顯示屏，用于顯示哪個(gè)病房按了按鈕。由于病情不同，要求當(dāng)病情較嚴(yán)重的病房按了按鈕后，醫(yī)生辦公室的顯示屏要優(yōu)先顯示其病房號(hào)。源代碼：module priority_encoder(clk,I0,I1,I2,I3,I4,I5,I6,I7,Y); input clk; input I0; input I1; input I2; input I3; inpu

18、t I4; input I5; input I6; input I7; output 2:0 Y; reg 2:0 Y;always (posedge clk )begin if(I7) Y = 3b111; else if(I6) Y = 3b110; else if(I5) Y = 3b101; else if(I4) Y = 3b100; else if(I3) Y = 3b011; else if(I2) Y = 3b010; else if(I1) Y = 3b001; else if(I0) Y = 3b000; else Y = 3bz; endendmodule綜合結(jié)果：TB文件：module tb2;/ Inputsreg clk;reg I0;reg I1;reg I2;reg I3;reg I4;reg I5;reg I6;reg I7;/ Outputswire 2:0 Y;/ Instantiate the Unit Under Test (UUT)priority_encoder uut (.clk(clk), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .I5(I5), .I6(I6), .I7(I7), .Y(Y); initial clk = 1b0; alwa