dc synopsys workshoppptdc1_200703_sg_04_area_timing

1、DAY11Introduction to Synthesis2Setting Up and Saving Designs3Design and Library Objects4Area and Timing Constraints2AgendaSynopsys 10-I-011-SSG-013 2007 Synopsys, Inc. All Rights Reserved4- 1Unit ObjectivesAfter completing this unit, you should be able to:n Constrain a design for arean Constrain a d

2、esign for setup timing, under the following conditions:l The designs specs are given or knownl Can be block- or chip-level designl Single clock, single cycle environmentl Default design scenario minimal command optionsn Create and execute a constraints file4- 8RTL Synthesis FlowWrite RTL code and si

3、mulateCreate start-up fileSynthesize the designLoad designs and librariesCreate constraints file Area constraint Timing constraints Environmental attributesApply design constraintsSelect appropriate compile flowWrite out design dataCommands To Be Covered(1 of 2)# Area and Timing ConstraintsTOP.con#r

4、eset_design; # Good practice step set_max_area 245000create_clock -period 2 get_ports Clkcreate_clock period 3.5 name V_Clk; # VIRTUAL clock set_clock_uncertainty setup 0.14 get_clocks Clk set_clock_latency source max 0.3 get_clocks Clk set_clock_latency max 0.12 get_clocks Clk set_clock_transition

5、0.08 get_clocks Clk set_input_delay -max 0.6 -clock Clk all_inputs set_input_delay -max 0.5 -clock V_Clk get_ports “A C F” set_output_delay -max 0.8 -clock Clk all_outputsset_output_delay -max 1.1 -clock V_Clk get_ports “OUT2 OUT7Commands To Be Covered(2 of 2)# Run script #read_verilog A.v B.v TOP.v

6、 current_design MY_TOPredirect tee file precompile.rpt linkredirect append tee file precompile.rpt check_designRUN.tclredirect append tee file precompile.rpt source echo -ver TOP.con redirect append tee file precompile.rpt report_port verbose redirect append tee file precompile.rpt report_clockredir

7、ect append tee file precompile.rpt report_clock skew redirect append tee file precompile.rpt check_timing.UNIX% dc_shell-t -f RUN.tcl | tee i my.loghelp *clockhelp verbose create_clock create_clock help printvar *_libraryman target_librarySpecifying an Area Constraintdc_shell-xg-t read_verilog MY_DE

8、SIGN.vdc_shell-xg-t current_design TOP_CHIP_or_BLOCKdc_shell-xg-tlinkdc_shell-xg-t set_max_area 245000n Area unit is defined by the library supplier its not in the library so ask!l 2-input NAND gatesl Transistorsl mil2, mm2 or m2n How do you determine what value to use?l From the spec or project lea

9、dl If migrating to a newer technology use a smaller % of the old design sizel Estimate based on experienceIs set_max_area 0 acceptable ?Specifying Setup-Timing Constraintsn Objective: Define setup timing constraints for all paths within a sequential designl All input logic paths (starting at input p

10、orts)l The internal (register to register) pathsl All output paths (ending at output ports)n Under the following conditions:l You are given the designs specsl Block- or chip-level designl Single clock, single cycle or environmentAssumed external launching circuitryCurrent designAssumed external capt

11、uring circuitryDefault Design ScenarioJANEs_DESIGNMY_DESIGNJOEs_DESIGNMNXSTClkFF4QBQDDQFF3QBDQFF2QBFF1QBQD發(fā)射捕獲Design Compiler assumes a“synchronously- clocked” environment. By default:n Input data arrives from a pos-edge clocked devicen Output data goes to a pos-edge clocked devicePath 3CLKZDQAPath2

12、Path 1Timing Analysis During/After SynthesisDC breaks designs into timing paths, each with a:n Startpointl Input portl Clock pin of Flip-Flop or registern Endpointl Output portl Any input pin of a sequential device, except clock pin14- 9Constraining Register-to-Register PathsJANEs_DESIGNMY_DESIGNJOE

13、s_DESIGNMNXSTClkFF4QBQDDQFF3QBDQFF2QBFF1QBQDWhat information must you provide to constrain all the register-to-register paths in MY_DESIGN for setup time?4- 27Unit of time is 1ns in this example. Defined in the technology library.Spec:Clock Period = 2nscreate_clock -period 2 get_ports ClkMY_DESIGNTS

14、etup, FF30.2nsNXTmaxSClkDQFF3QBDQFF2QB0ns1ns2nsConstraining Reg-to-Reg Paths: ExampleWhat is the maximum delay requirement Tmax for the register-to-register path through X in the MY_DESIGN? create_clock Required ArgumentsTCL: Embedded command create_clock -period 2 get_ports ClkTCL: Command optionMY

15、_DESIGND Q FF3D Q FF2NXSPeriod0ns1ns2nsUnit of time is 1ns in this example. Defined in the technology library.Port object ClkSame name by defaultRises at 0ns with 50% duty cycle, by defaultClock object ClkDefault Clock Behaviorn Defining the clock in a single-clock design constrains all timing paths

16、 between registers for single-cycle, setup timen By default the clock rises at 0ns and has a 50% duty cyclen By default DC will not “buffer up” the clock network, even when connected to many clock/enable pins of flip-flops/latchesl The clock network is treated as “ideal” - infinite drive capabilityu

17、 Zero rise/fall transition timesu Zero skewu Zero insertion delay or latencyl Estimated skew, latency and transition times can, and should be modeled for a more accurate representation of clock behaviorModeling Clock Treesn Design Compiler is NOT used to synthesized clock buffer treesn Clock tree sy

18、nthesis is usually done by a physical or layout tool, based on actual cell placementD_InD QD QFF1FF2CLKLogical CircuitD_InD Q FF1CLKD QFF2Post-Layout CircuitWhat clock tree effects need to be taken into account by the synthesis tool, prior to layout?Modeling Clock SkewD_InCLKD Q FF1TUD Q FF2Post-Lay

19、out CircuitUncertainty models the maximum delay difference between the clock network branches, known as clock skew, but can also include clock jitter and margin effects:set_clock_uncertainty setup TU get_clocks CLKplaced on clock objectsPre-Layout: clock skew + jitter + marginset_clock_uncertainty a

20、nd Setup TimingExample:create_clock -period 2 get_ports CLK set_clock_uncertainty setup 0.14 get_clocks CLKXD QFF2D QFF1FF2 setup check at: 2 - 0.14 - 0.08 = 1.78FF1 Data Launch Edge (No uncertainty!)/ /.08.14Assume lib setup = 0.08ns011.78 1.92 2 Max allowable delay for block “X”Modeling Latency or

21、 Insertion Delayn Network latency models the average internal delay from thecreate_clock port or pin to the register clock pinsn Source latency models the delay from the actual clock origin to the create_clock port or pin:create_clock -period 10 get_ports CLK set_clock_latency -source max 3 get_cloc

22、ks CLK set_clock_latency max 1 get_clocks CLK ;# pre layout #set_propagated_clock get_clocks CLK ;# post layoutl Used for either ideal or propagated clocks (post layout)CLK3ns1nsOrigin of ClockSource LatencyNetwork LatencyCLKQ DYOUR_DESIGNModeling Transition TimeD_InCLKD Q FF1TTD Q FF2Post-Layout Ci

23、rcuitTransition models the rise and fall times of the clock waveform at the register clock pins:set_clock_transition TT get_clocks CLKPre/Post Layout Clock jitter 0.05 + skew 0.3 + margin 0.15 transition uncertainty latency ideal clock reset_designcreate_clock -p 5 -n MCLK Clk set_clock_uncertainty

24、0.5 MCLKset_clock_transition 0.08 MCLK set_clock_latency -source max 4 MCLK set_clock_latency max 2 MCLKreset_designcreate_clock -p 5 -n MCLK Clk set_clock_uncertainty 0.2 MCLKset_clock_latency -source max 4 MCLK set_propagated_clock MCLKSynthesis ConstraintsPost-CTS STA ConstraintsConstraining Inpu

25、t PathsJANEs_DESIGNMY_DESIGNMANXSClkDQFF3QBDQFF2QBFF1QBQDWhat additional information must you provide to constrain all the input paths (N) in your design for setup time?Constraining Input Paths: Example 1Spec:Latest Data Arrival Time at Port A, after Janes launching clock edge = 0.6nsmydesign.concre

26、ate_clock -period 2 get_ports Clkset_input_delay -max 0.6 -clock Clk get_ports AJANEs_DESIGNMY_DESIGNTSetup, FF20.2nsDQM0.6nsATmaxNXSFF1QBClkDQFF3QBDQFF2QBWhat is the maximum delay Tmax for the input path N inMY_DESIGN? Constraining Input Paths: Example 2Spec:Clock frequency = 400MHz. Maximum delay

27、for path N = 1.5nsU1Clk(400 MHz)0.1nsD QNA=setupTTmax= 1.5nsMY_DESIGNHow do you constrain MY_DESIGN for the indicated Tmax?create_clock get_ports Clkset_input_delay Constraining Output PathsMY_DESIGNJOEs_DESIGNNXSBTDQFF4ClkQBDQFF3QBDQFF2QBWhat additional information must you provide to constrain all

28、 the output paths (S) in your design for setup time?Constraining Output Paths : Example 1Spec:Latest Data Arrival Time at Port B, before Joes capturing clock = 0.8nsmydesign.concreate_clock -period 2 get_ports Clkset_input_delay -max 0.6 -clock Clk get_ports A set_output_delay -max 0.8 -clock Clk ge

29、t_ports BMY_DESIGNJOEs_DESIGNTT +NXTmaxSB0.7ns0.1nsTsetupTDQFF4ClkQBDQFF3QBDQFF2QBWhat is the maximum delay Tmax for the output path throughS in MY_DESIGN? Constraining Output Paths : Example 2Spec:The maximum delay to Port B = 0.7nsClk (500 MHz)ClkSQDBMY_DESIGNTmax 0.7nsU3How do you constrain MY_DE

30、SIGN for the indicated Tmax?create_clock -period 2 get_ports Clkset_output_delay Multiple Inputs/Outputs - Same ConstraintsMY_DESIGNASOut1BMCNOut2D QTClkD Qset_input_delay max 0.5 clock Clk remove_from_collection all_inputs get_ports ClkTo constrain all inputs the same, except for the clock port:set

31、_output_delay max 1.1 clock Clk all_outputsTo constrain all outputs the same:Different Port ConstraintsMY_DESIGNASOut1BMCNOut2D QTClkD QTo constrain most ports the same, except for some:set_input_delay max 0.5 clock Clk all_inputs set_input_delay max 0.8 clock Clk get_ports C remove_input_delay get_

32、ports ClkOverridesAnother way to remove the constraint from the Clk portJANEs_DESIGNMY_DESIGNMANXSCJOEs_DESIGNTsetup 0.1nsTEClkTE0.4nsBFDTG-T0.2nsGFF4QBQDDQFF3QBDQFF2QBFF1QBQDHow do you constrain the combinational path F? What is the maximum delay through F?create_clock -period 2 get_ports Clk set_i

33、nput_delay set_output_delay Exercise: Constraining Combinational PathsTF, max = 4- 284- 52Assumed external launching circuitryAssumed external capturing circuitryConstraining a Purely Combinational DesignJANEs_DESIGNMY_DESIGNMComboTClkFF4QBQDJOEs_DESIGNFF1QBQDWhat is different about this design?How

34、do we constrain such a design?Answer: Use a Virtual Clock!What is a virtual clock?ANSWER:n A clock that is not connected to any port or pin within the current designn Serves as a reference for input or output delaysn Creates a clock object with a user-specified namewithin Design Compilers memoryNo s

35、ource pin or port!Must be named-period 2-name VCLKcreate_clockExercise: Combinational DesignsJANEs_DESIGNTMY_DESIGNM0.4nsMAComboBT500 MHzClkFF4QBQDTsetup 0.1nsTT0.2nsJOEs_DESIGNFF1QBQDHow do you constrain the Combo path? What is the maximum delay through Combo?create_clock _-name VClk period 2 set_i

36、nput_delay set_output_delay TCombo, max = Time Budgeting(1/2)What if you do not know the delays on your inputs or the setup requirements of your outputs?ckt XMY circuitckt YD QFF1?ND QFF2XD QFF3S?DQFF4CLK (100 MHz)A:Create a Time Budget!Time Budgeting(2/2)circuit XMY circuit?NXCLK (100 MHz)40% of cl

37、ockperiodFF2QDFF1QDBetter to budget conservativelythan to compile with paths unconstrained!Time Budgeting Exampletiming_budget.tcl# A generic Time Budgeting script file # for MY_BLOCK, X_BLOCK and Y_BLOCK create_clock -period 10 get_ports CLKset_input_delay -max 6 -clock CLK all_inputs remove_input_

38、delay get_ports CLK set_output_delay -max 6 -clock CLK all_outputsX_BLOCKMY_BLOCKY_BLOCKX10S4N4X10S4N4X10FF4D QD QFF3FF2D QD QFF1Would it be easier to specify a time budget if all outputs were registered?Registered OutputsDQ FF0Y_BLOCKDQ FF3ClkQFF2DFF1ZDQAMY_BLOCKX_BLOCK# Assume every block has regi

39、stered outputs, 10ns clock:set clk_to_q_max 1.5; # Assume slowest register driving your input set clk_to_q_min 0.9; # Assume fastest register driving your output set all_in_ex_clk remove_from_collection all_inputs get_ports Clkset_input_delay-max$clk_to_q_max-clock CLK $all_in_ex_clk set_output_dela

40、y -max expr 10 - $clk_to_q_min -clock CLK all_outputsTCL: Arithmetic expressionAll input paths are constrained by set_input_delayAll register-to-register paths are constrained by create_clockJANEs_DESIGNMY_DESIGNJOEs_DESIGNTiming Constraint SummaryFF4QBQDFF1QBQDDQFF3QBDQFF2QBMNXSTClkAll output paths

41、 are constrained by set_output_delayYou specify how much time is used by external logic.DC calculates how much time is left for the internal logic.Executing Commands Interactivelyn Commands can be typed interactively in DC-shell:l OK for testing or debugging individual commandsl Not efficient for “p

42、roduction work”UNIX% dc_shell-tdc_shell-xg-t read_verilog A.v B.v TOP.v dc_shell-xg-t current_design MY_TOP dc_shell-xg-t linkdc_shell-xg-t check_designdc_shell-xg-t set_max_area 245000dc_shell-xg-t create_clock -period 2 get_ports Clkdc_shell-xg-t set_input_delay -max 0.6 -clock Clk all_inputs.Sour

43、cing Constraints Filesn For better efficiency, capture the constraints in a “constraints file”, which can be executed interactively in DC-shell:dc_shell-xg-t read_verilog A.v B.v TOP.v dc_shell-xg-t current_design MY_TOP dc_shell-xg-t linkdc_shell-xg-t check_designdc_shell-xg-t source echo verbose T

44、OP.con.set_max_area 245000TOP.concreate_clock -period 2 get_ports Clk set_input_delay -max 0.6 -clock Clk all_inputs.Executing Run Scripts in “Batch Mode”n For maximum efficiency capture run commands in a run script and execute in batch modeUNIX% dc_shell-t -f RUN.tcl | tee i run.logl Allows you to

45、spend time on “other tasks” while DC is runningread_verilog A.v B.v TOP.v current_design MY_TOPlinkRUN.tclcheck_designsource echo verbose TOP.con.l Do this only once you are certain the run script and constraints file are complete and correctOther tasksConstraints File Recommendations (1 of 3)Since

46、constraints are saved in the ddc design format it is recommended to:Erase all constraints from the current design before applying new constraints.reset_design set_max_area 245000create_clock -period 2 get_ports Clk.!When applying multiple constraint scripts, there should only be ONE reset_design com

47、mand.Include comments in your scripts# Comments in Tcl# If you want to comment on the same line, be sure # to use a semicolon before the comment:create_clock p 5 n V_Clk; # This is a VIRTUAL clockConstraints File Recommendations (2 of 3)This semicolon is required!Comment a line in a DC-Tcl script us

48、ing the # characterConstraints File Recommendations (3 of 3)n Use common extensions:e.g.RUN.tcl orDESIGN.conn Avoid using aliases and abbreviating commandsn Avoid abbreviating command options:create_clock period 5 get_ports clkn Avoid “snake scripts”Check the Syntax of ConstraintsUNIX% dcprocheck TO

49、P.conUNIX% dcprocheck TOP.con.Unknown option create_clock -freq create_clock -freq 3.0 get_ports clkn dcprocheck is a syntax-checking utility that is included with Design Compilern Available if you can launch DC no additional user setup requiredCheck the Values/Options of Constraintsdc_shell-xg-t report_port verbose.Output DelayMinMaxRelatedFanoutn Verify port constraints (non-clock)report_port -verboseOut