基于EDA的數(shù)字秒表設(shè)計(jì).ppt

基于eda的數(shù)字秒表設(shè)計(jì),實(shí)驗(yàn)要求,1、數(shù)字秒表主要由：分頻器、掃描顯示譯碼器、一百進(jìn)制計(jì)數(shù)器、六十進(jìn)制計(jì)數(shù)器（或十進(jìn)制計(jì)數(shù)器與6進(jìn)制計(jì)數(shù)器）、十二進(jìn)制計(jì)數(shù)器（或二十四進(jìn)制計(jì)數(shù)器）電路組成。在整個(gè)秒表中最關(guān)鍵的是如何獲得一個(gè)精確的100hz計(jì)時(shí)脈沖，除此之外，數(shù)字秒表需有清零控制端，以及啟動(dòng)控制端、保持保持，以便數(shù)字時(shí)鐘能隨意停止及啟動(dòng)。（時(shí)鐘50m） 2、數(shù)字秒表顯示由時(shí)（12或24進(jìn)制任選）、分（60進(jìn)制）、秒（60進(jìn)制）、百分之一秒（一百進(jìn)制）組成，利用掃描顯示譯碼電路在八個(gè)數(shù)碼管顯示。 3、能夠完成清零、啟動(dòng)、保持（可以使用鍵盤或撥碼開(kāi)關(guān)置數(shù)）功能。 4、時(shí)、分、秒、百分之一秒顯示準(zhǔn)確。,實(shí)驗(yàn)設(shè)計(jì)提示,分頻模塊,實(shí)驗(yàn)設(shè)計(jì)提示,library ieee; use ieee.std_logic_1164.all; entity div is port(clr,clk: in bit; q: buffer bit); end div; architecture a of div is signal counter:integer range 0 to 249999; begin process(clr,clk) begin if (clk=1 and clkevent) then if clr=0 then counter=0; elsif counter=249999 then counter=0; q= not q; else counter=counter+1; end if; end if; end process; end a;,實(shí)驗(yàn)設(shè)計(jì)提示,十進(jìn)制計(jì)數(shù)器,實(shí)驗(yàn)設(shè)計(jì)提示,entity cnt10 is port(clk:in std_logic; clr:in std_logic; start:in std_logic; daout:buffer std_logic_vector(3 downto 0); co:out std_logic); end entity cnt10; architecture art of cnt10 is begin process(clk,clr,start) begin if clr=0 then daout=“0000“; elsif (clkevent and clk=1)then if (start=1)then if daout=“1001“then daout=“0000“;co=1; else daout=daout+1;co=0; end if; end if; end if; end process; end art;,實(shí)驗(yàn)設(shè)計(jì)提示,六進(jìn)制計(jì)數(shù)器,實(shí)驗(yàn)設(shè)計(jì)提示,entity cnt6 is port(clk,clr,start:in std_logic; daout:buffer std_logic_vector(3 downto 0); co:out std_logic); end entity cnt6; architecture art of cnt6 is begin process(clk,clr,start) begin if clr=0 then daout=“0000“; elsif (clkevent and clk=1)then if (start=1)then if daout=“0101“then daout=“0000“;co=1; else daout=daout+1; co=0; end if; end if; end if; end process; end art;,實(shí)驗(yàn)設(shè)計(jì)提示,顯示譯碼模塊,實(shí)驗(yàn)設(shè)計(jì)提示,entity deled is port(num:in std_logic_vector(3 downto 0); led:out std_logic_vector(6 downto 0); end deled ; architecture a of deled is begin process(num) begin case num