超大規(guī)模集成電路第八次作業(yè)2016秋段成華

1、Assignment 81. Access relevant reference books or technicaldata books and give accuratedefinitions for the following timing parameters:(1)design entity,(6)delta delay,(2)signal driver,(7)simulation time,(3)transaction,(8)simulation cycle,(4)event,(9)inertial time,(5)time queue,(10) transport time.(1

2、)design entity: In VHDL a given logic circuit represented as adesign entity. Adesign entity, in return , consists of two different types of description: the interface description and one or more architectural bodies. The interface description declares the entity and describes its inputs and outputs.

3、(2) signal driver: If a process contains one or more signal assignment statement that schedule future values for some signal X, the VHDL simulator creates a single value holder called asignal driver .(3) transaction:A pair consisting of a value and time. The value part represents afuture value of th

4、e driver; the time part represents the time at which the value part becomes the current value of driver.(4) event: Its a kind of signal property and presents signal jump. Such as if(clkevent and clk=1).(5) time queue: Its used to keep some signal transactions in the simulator. Time queue entries are

5、 represented as a two-tuple of the form(SN,V), where SN is a signal name and V is the value the signal is scheduled to assume at the scheduled time. Each time queue entry is called a signal transaction.(6) delta delay: A period of time greater than 0, but less than any standard time unit no number o

6、f delta delayadded together can cause simulation time to advance.(7) simulation time: The elapsed time in standard time units during simulation.(8) simulation cycle: Every time simulation time advances, a simulation cycle occurs, which we now define more formally. The execution of a model consists o

7、f an initialization phase followed by the repetitive execution of processesin the process network. Each repetition is said to be simulation cycle.(9) inertial time: Example: Z = I after 10ns; The signal propagation will take place if and only if input I persists at a given level for 10ns-the amount

8、of time specified in the after clause.(10)transport time: Z = transport I after 10ns; All changes on I will propagate to Z, regardless of how long the value of I stays at the new level.2. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description types, i.e., behavioral, data

9、flow and structural descriptions. Synthesize andsimulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and crea

10、ted by your own as sources added to your VHDL project.Logic schematic of 74-139:Function table of one decoder of 74-139:INPUTSENABLSELECOUTPUTSTEYYYYGBA0123HXXHHHHLLLLHHHLLHHLHHLHLHHLHLHHHHHL（ 1）、行為描述代碼如下：- Company: - Engineer:- Create Date:21:14:09 12/02/2016- Design Name:- Module Name: deceoder_be

11、h - Behavioral- Project Name:- Target Devices:- Tool versions:- Description:- Dependencies:- Revision:- Revision 0.01 - File Created- Additional Comments:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaratio

12、n if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity deceoder_beh isPort ( G1,G2 : in std_logic;A : in std_logic_vector(1 downto 0);end deceoder_beh;architecture Behavioral of deceoder_beh isbeginde1: process (A, G1)beginif G1 = 1 theny1 Y1 Y1 Y1

13、Y1 Y1 = 1111;end case;end if;end process;de2: process (B, G2)beginif G2 = 1 thenY2 Y2 Y2 Y2 Y2 Y2 0);signal B : std_logic_vector(1 downto 0) := (others = 0); -Outputssignal Y1 : std_logic_vector(3 downto 0);signal Y2 : std_logic_vector(3 downto 0);BEGIN- Instantiate the Unit Under Test (UUT) uut: de

14、ceoder_beh PORT MAP (G1 = G1,G2 = G2, A=A, B=B, Y1 = Y1,Y2 = Y2);- Stimulus processstim_proc: processbegin- insert stimulus hereG1 =1;WAIT FOR 100 ns;G1 =0;A = 00;B = 00;- - -Current Time:200nsWAIT FOR 100 ns;G1 =0;A = 01;B = 01;- - -Current Time:300nsWAIT FOR 100 ns;G1 =0;A = 10;B = 10;- - -Current

15、 Time:400nsWAIT FOR 100 ns;G1 =0;a = 11;b = 11;WAIT FOR 100 ns;end process;END;測(cè)試波形如下：可以看到當(dāng) G1=0 和 G2=0 可以正常的譯碼，當(dāng) G1=1 和 G2=1，則 Y1 和 Y2 都輸出 ”1111”。（2）數(shù)據(jù)流代碼如下：- Company:- Engineer:- Create Date:23:14:31 12/02/2016- Design Name:- Module Name:decoder_dataf - Behavioral- Project Name:- Target Devices:-

16、Tool versions:- Revision:- Revision 0.01 - File Created- Additional Comments:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use U

17、NISIM.VComponents.all;entity decoder_dataf isPort ( G1,G2:in std_logic;A : in std_logic_vector(1 downto 0);B : in std_logic_vector(1 downto 0);Y1 : out std_logic_vector(3 downto 0);Y2 : out std_logic_vector(3 downto 0); end decoder_dataf;architecture dataflow of decoder_dataf issignal G11,G22 :std_l

18、ogic;signal A0,A1 :std_logic;signal B0,B1 :std_logic;beginG11 = not G1;G22 = not G2;A0 = not A(0);B0 = not B(0);A1 = not A(1);B1 = not B(1);Y1(0) = not (G11 and A0 and A1);Y2(0) = not (G22 and B0 and B1);Y1(1) = not (G11 and A1 and (not A0);Y2(1) = not (G22 and B1 and (not B0);Y1(2) = not (G11 and A

19、0 and (not A1);Y2(2) = not (G22 and B0 and (not B1);Y1(3) = not (G11 and (not A0) and (not A1);Y2(3) = not (G22 and (not B0) and (not B1);end dataflow;TestBench代碼沒(méi)有改變?？梢钥吹脚c（1）中結(jié)論一致得到如下波形。（3）結(jié)構(gòu)描述代碼如下：- Company:- Create Date:12:01:26 12/03/2016- Design Name:- Module Name:decoder_stuc - Behavioral- Pro

20、ject Name:- Target Devices:- Tool versions:- Description:- Dependencies:- Revision:- Revision 0.01 - File Created- Additional Comments:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating-

21、 any Xilinx primitives in this code.library UNISIM;use UNISIM.VComponents.all;entity decoder_stuc isG2 : INstd_logic;A : INstd_logic_vector(1 downto 0);B : INstd_logic_vector(1 downto 0);Y1 : OUTY2 : OUTstd_logic_vector(3 downto 0);std_logic_vector(3 downto 0);end decoder_stuc;architecture struct of

22、 decoder_stuc issignal G11,G22 :std_logic;signal A0,A1 :std_logic;signal B0,B1 :std_logic;signal A00,A11 :std_logic;signal B00,B11 :std_logic;signal Y11 :std_logic_vector(3 downto 0);signal Y22 :std_logic_vector(3 downto 0);beginU0 : INV port map (A0, A(0);U1 : INV port map (B0, B(0);U2 : INV port m

23、ap (G11, G1);U3 : INV port map (G22, G2);U4 : INV port map (A1, A(1);U5 : INV port map (B1, B(1);U6 : INV port map (A00, A0);U7 : INV port map (B00, B0);U8 : INV port map (A11, A1);U9 : INV port map (B11, B1);U10: nand3 port map (Y11(0), A0, A1, G11);U11: nand3 port map (Y22(0), B0, B1, G22);U12: na

24、nd3 port map (Y11(1), G11, A1, A00);U13: nand3 port map (Y22(1), G22, B1, B00);U14: nand3 port map (Y11(2), G11, A0, A11);U15: nand3 port map (Y22(2), G22, B0, B11);U16: nand3 port map (Y11(3), G11, A00, A11);U17: nand3 port map (Y22(3), G22, B00, B11);Y1 = Y11;Y2 = Y22;end struct;TestBench代碼沒(méi)有改變?？梢?/p>

25、看到與（1）中結(jié)論一致得到如下波形。3. Analyze and simulate the following code lists (code1 and code 2) with the same input signals shown below by presenting POW and OL. If the data type of“a, b, c, d, u, v, w, x, y, z ”is declared as std_logic, what changes the simulation outputs will be?Code 1:entity delta isport(a

26、, b, c, d: in bit; u, v, w, x, y, z: bufferbit);end delta;architecture ar_delta of delta isbeginz= not y;y= w or x;x= u or v;w= u and v;v= c or d;u= a and b;end ar_delta;Code 2:entity delta isport(a, b, c, d: in bit; u, v, w, x, y, z: bufferbit);end delta;architecture ar_delta of delta isbeginz= not

27、 y after 10 ns;y= w or x after 10 ns;x= u or v after 10 ns;w= u and v after 10 ns;v= c or d after 10 ns;u a,b = b,c = c,d = d,u = u,v = v,w = w,x = x,y = y,z = z);- Stimulus processstim_proc: processbegina =1;b =0;c =1;d =0;WAIT FOR 100 ns;a =1;b =0;c =0;d =0;WAIT FOR 100 ns;a =0;b =0;c =0;d =0;WAIT

28、 FOR 100 ns;a =0;b =0;c =0;d =1;WAIT FOR 100 ns;a =0;b =1;c =0;d =1;WAIT FOR 100 ns;a =0;b =1;c =1;d =0;WAIT FOR 100 ns;a =1;b =1;c =1;d =0;WAIT FOR 100 ns;a =1;b =1;c =0;d =0;WAIT FOR 100 ns;a =0;b =0;c =0;d =1;WAIT FOR 100 ns;a =0;b =0;c =0;d 1.0+4：y 的動(dòng)作發(fā)生在 w、 x 之后，所以在 w、x 中有一個(gè)發(fā)生變化，那么下一個(gè) 延時(shí)之后， y 才

29、動(dòng)作： 0-1.0+5 ：z 的動(dòng)作發(fā)生在 y 之后，所以在 y：0-1 之后，下一個(gè) 延時(shí)之后，z 才動(dòng)作：1-0.此時(shí)，在輸入沒(méi)有新的變化情況下， 所有的輸出信號(hào)都已經(jīng)更新完畢。 此后的時(shí)間，信號(hào)的更新分析方法同上面的分析。 其中值得注意的一點(diǎn)就是， 在每次輸入信號(hào)變化的時(shí)候， 這個(gè)變化在 ModelSim 中是有一個(gè) 延時(shí)的。如下圖所示：結(jié)論：輸出的改變?cè)谳斎氲闹蹈淖冎蟀l(fā)生， 且延時(shí) 決定于電路。 本電路的輸出與輸入信號(hào)之間的 延時(shí)關(guān)系：u 比 a、 b 延時(shí)一個(gè) . v 比 c、 d 延時(shí)一個(gè) .w 比 u、v 延時(shí)一個(gè) x 比 u、v 延時(shí)一個(gè) .y 比 w、x 延時(shí)一個(gè) .z 比

30、 y 延時(shí)一個(gè) .分析： CODE2說(shuō)明： code2的描述屬于（ Standard Time Unit Delay STUD）。該段代碼與code1 的主要區(qū)別就是在每條賦值語(yǔ)句之后添加一個(gè)固定的延時(shí)10ns，這樣便可以更清楚地觀察信號(hào)之間的延時(shí)關(guān)系。譬如u 在 a 或者 b 改變之后 10ns 作出反應(yīng)，而 w 則在 u 改變 10ns 后作出跳變，也就是 a, b 變化 20ns 之后作出變化，關(guān)于這一點(diǎn)可以參考綜合后的電路和對(duì) code1的分析。即 w 決定于 a，b，c，d 四個(gè)信號(hào)，而對(duì)于這幾個(gè)信號(hào)的反應(yīng)延時(shí)均為 20ns。分析 LIST 看到二者還是有區(qū)別的， 例如在 300ns

31、 時(shí)候，CODE1 一個(gè) 接一個(gè) 時(shí)間下改變輸出，而 CODE2 只在輸入信號(hào)改變時(shí)候需要一個(gè) ，后面不需要再使用 ，after 10ns 代表了實(shí)際的延時(shí)輸出，由于輸入信號(hào)的變化引起的輸出信號(hào)的每一次變化都需要 10ns（被忽略）的延時(shí)證明了前面的輸出影響到了后面的輸出，他們是有順序的輸出，分析與CODE1 一樣。區(qū)別只是CODE1是 改變輸出，而 CODE2 是 10ns 改變輸出。（2）、將輸入和輸出的代碼的類型改為std_logic，代碼無(wú)大改動(dòng)直接給出輸出波形和 LIST 。CODE1 和 CODE2 輸出波形如下：CODE1 波形CODE2 波形CODE1 LISTCODE2LIS

32、T分析 CODE1：觀察輸出波形 bit 與 std_logic 兩種類型結(jié)果一樣，對(duì)比bit 和 std_logic 兩種類型的 list 表，我們發(fā)現(xiàn)，它們的 延時(shí)效果是一樣的。只是 std_logic 類型在初始賦值階段的輸出有 Unknown 的情況。分析 CODE2：和 bit 數(shù)據(jù)類型最大的不同就是在 a，b，c，d 的數(shù)據(jù)值確定之前， u，v 等數(shù)據(jù)為紅色表示，即不確定狀態(tài) UUnknown 。在輸入的 a，b 等值確定之前， x ， y，z 等數(shù)值不能確定，根據(jù) std_logic 的九值邏輯原則，此時(shí)的輸出值為 Unknown。但是，每過(guò)一個(gè) 10ns 的延時(shí)，就會(huì)有一個(gè)輸出

33、從 Unknown 狀態(tài)變化為其他狀態(tài)。經(jīng)過(guò) 40ns 后，輸出隨輸入信號(hào)的變化和前面分析的一樣。（3）、總結(jié)：通過(guò) code1和 code2的比較以及將代碼中的 bit 數(shù)據(jù)類型轉(zhuǎn)化為 std_logic 類型后比較可以得到以下結(jié)論：1、數(shù)據(jù)類型 std_logic 是九值邏輯，相對(duì) bit 數(shù)據(jù)類型多了 U、 X 等數(shù)據(jù)類型，在信號(hào)被賦值以前， std_logic 和 bit 數(shù)據(jù)類型的不同就表現(xiàn)出來(lái)了；2、仿真延時(shí)單元 是硬件描述中的基本時(shí)間單位，每一個(gè)延時(shí)以及反應(yīng)過(guò)程都是以 為單位進(jìn)行的。 譬如賦值語(yǔ)句后， 在沒(méi)有延時(shí)操作的情況下， 系統(tǒng)至少經(jīng)過(guò)一個(gè) 才能將值傳給信號(hào)；3、在前仿真中，當(dāng)使用標(biāo)準(zhǔn)時(shí)間單元延時(shí)（Standard Time Unit Delay），即“ after 10ns”等操作存在時(shí)， 將被忽略，因?yàn)榻?jīng)過(guò)了一個(gè)大的延時(shí)之