杭電計(jì)組實(shí)驗(yàn)-實(shí)現(xiàn)R型指令的CPU設(shè)計(jì)實(shí)驗(yàn)

1、杭電計(jì)組實(shí)驗(yàn)-實(shí)現(xiàn)R型指令的CPU設(shè)計(jì)實(shí)驗(yàn)作者:日期:#實(shí)驗(yàn)報(bào)告姓名陽(yáng)光男學(xué)號(hào)16041321班級(jí)16052317專(zhuān)業(yè)計(jì)算機(jī)科學(xué)與技術(shù)課程名稱(chēng)計(jì)算機(jī)組成原理與系統(tǒng)結(jié)構(gòu)試 驗(yàn)任課老師張翔老師指導(dǎo)老師張翔老師機(jī)位號(hào)無(wú)實(shí)驗(yàn)序號(hào)8實(shí)驗(yàn)名 稱(chēng)實(shí)驗(yàn)八 實(shí)現(xiàn)R型指令的CPU設(shè)計(jì)實(shí)驗(yàn)實(shí)驗(yàn)時(shí)間2018/5/25實(shí)驗(yàn)地占八、1 教 225實(shí)驗(yàn)設(shè)備 號(hào)個(gè)人電腦一、實(shí)驗(yàn)程序源代碼頂層LED測(cè)試模塊：module Top_LED(clk,rst,SW,LED);in put clk,rst;in put 2:0SW;output reg7:0LED;wire ZF,OF;wire 31:0ALU_F;top_R_cpu

2、 test_cpu(rst,clk,ZF,OF,ALU_F); always(*)begi ncase(SW)3b000:L ED=ALU_F7:0;3b001:LED=ALU_F15:8;3b010:LED=ALU_F23:16;3b011:LED=ALU_F31:24;3b100:begin LED7:2=0;LED1=0F;LED0=ZF;e nd default:LED=0;endcaseend2018年_6_月 1 日成績(jī)：en dmodule頂層R型CPU模塊：module top_R_cpu(input rst,input clk,output ZF,output OF,outp

3、ut 31:0F); reg write_reg;wire 31:0l nst_code;wire 31:0R_Data_A;wire 31:0R_Data_B;reg 2:0ALU_OP;pc pc_c onn ect(clk,rst,I nst_code);Register_file R_co nn ect(I nst_code25:21,l nst_code20:16,In st_code15:11,write_reg,F,clk,rst, R_Data_A,R_Data_B);ALU ALU_co nn ect(R_Data_A,R_Data_B,F,ALU_OPOF);always(

4、*)begi nwrite_reg=0;ALU_OP=0;if(I nst_code31:26=0)begi ncase(I nst_code5:0)6b100000:ALU_OP=3b100;6b100010:ALU_OP=3b101;6b100100:ALU_OP=3b000;6b100101:ALU_OP=3b001;6b100110:ALU_OP=3b010;6b100111:ALU_OP=3b011;6b101011:ALU_OP=3b110;6b000100:ALU_OP=3b111;endcasewrite_reg=1;endenden dmodulePC取指令模塊：module

5、 pc(i nput clk,i nput rst,output 31:0l nst_code); reg 31:0PC;wire31:0PC_ new;in itialPC=32h00000000;In st_ROM In st_ROM1 (.clka(clk),.addra(PC7:2),.douta(I nst_code);assign PC_n ew二24h000000,PC_ new7:0; always (n egedge clk or posedge rst) begi nif(rst)PC=32h00000000;else PC=PC_new;enden dmodule寄存器堆

6、模塊:moduleB);Register_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data in put 4:0R_Addr_A;in put 4:0R_Addr_B;in put 4:0W_Addr;in put Write_Reg;in put 31:0W_Data;in put Clk;in put Reset;output 31:0R_Data_A;output 31:0R_Data_B;reg 31:0REG_Files0:31;3initial/仿真過(guò)程中的初始化begi nfor(i=

7、0;iv=31;i二i+1)REG_Filesi=O;endassign R_Data_A=REG_FilesR_Addr_A; assign R_Data_B=REG_FilesR_Addr_B; always(posedge Clk or posedge Reset) begi nif(Reset)for(i=0;i=31;i=i+1)REG_Filesi=O;elseif(Write_Reg&W_Addr!=0)REG_FilesW_Addr=W_Data;enden dmoduleALU算術(shù)邏輯運(yùn)算單元模塊：module ALU(A,B,F,ALU_QZF,OF);in put 31:

8、0A,B;in put 2:0ALU_OP;output reg ZF,OF;output reg31:0F;reg C32;always(*)begi nOF=1b0;C32=1b0;case(ALU_OP)3b000:F=A&B;3b001:F=A|B;3b010:F=AAB;3bO11:F=(AB);3b100:begin C32,F=A+B;OF=A31AB31AF31AC32;e nd3b101:begin C32,F二A-B;OF二A31AB31AF31FC32;e nd 3b110:if(AB)F=1;elseF=0;3b111:F=B A;endcaseif(F=0)ZF=1;

9、elseZF=0;enden dmodule測(cè)試代碼：module test;/In putsreg rst;reg clk;/ Outputswire ZF;wire OF;wire 31:0 F;/ I nsta ntiate the Unit Under Test (UUT) top_R_cpu uut (.rst(rst),.clk(clk),ZF(ZF),.OF(OF),F(F)；in itial beg in/I nitialize In putsrst = 0;clk = 0;/ Wait 100 ns for global reset to finish#100;clk=1;/

10、 Add stimulus here forever beg in#50; clk=clk;endend en dmodule二、仿真波形9構(gòu):三、電路圖頂層電路模塊SW（2:0toppledLED（7：0）elkretTop_LEDTop_LED頂層電路內(nèi)部結(jié)四、引腳配置（約束文件）NET LED7 LOC :=T11;NET LED6 LOC :=R11;NET LED5 LOC :=N11;NET LED4 LOC =M11;NET LED3 LOC :=V15;NET LED2 LOC :=U15;NET LED1 LOC :=V16;NET LED0 LOC :=U16;NET SW2 LOC=V9;NET SW1 LOC=T9;NET SW0 LOC :=T10;NET clk LOC =C9;NET rst LOC =C4;五、思考與探索(1)R型指令CPU實(shí)驗(yàn)結(jié)果記錄表序號(hào)指令執(zhí)行結(jié)果標(biāo)志結(jié)論10000827FFFFFFFF00正確20001102b0000_000100正確3004218200000_000200正確4006220200000_000300正確5008328200000_000500正確600a330200000_000700正確7004638040000_000E00正確800a648200000_000C00正確90126400