加速度傳感器KXSD9芯片手冊(cè) PDF

1、 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010Product DescriptionThe KXSD9 is a tri-axis silicon micromachined accelerometer with a user selectable full- scale output range of 2g, 4g, 6g or 8g. The sense element is fabricated using Kionixs proprietary plasma mi

2、cromachining process technology. Acceleration sensing is based on the principle of a differential capacitance arising from acceleration-induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variation, temperature, and environmental stres

3、s. The sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. A separate ASIC device packaged with the sense element provides signal conditioning, self-test, and temperature compensation. The accelerometer is delivered in a 3 x

4、 3 x 0.9 mm LGA plastic packageoperating from a 1.8 3.6V DC supply. Either I2C or SPI interfaces can be used to communicate to the chip to trigger A/D conversions or manage power consumption.Functional DiagramXSensorYChargeLPFSensorAmpZTempSensorSensorVdd 5A/DSPI/I 2CIO Vdd 1Motion Detection3 AUX IN

5、GND 468910736 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:607-257-1146310-1547-1007221647 - Page 1 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010Product SpecificationsTable 1. Mechanical(s

6、pecifications are for operation at 3.3V and T = 25C unless stated otherwise)ParametersUnitsMinTypicalMaxOperating Temperature RangeC-40-85Zero-g Offsetcounts184320482253Zero-g Offset Variation from RT over Temp.mg/C0.5 (xy)3 (z)FS1=1, FS0=1 ( 2g)794819844Sensitivity1FS1=1, FS0=0 ( 4g)counts/g3904104

7、30FS1=0, FS0=1 ( 6g)257273289FS1=0, FS0=0 ( 8g)189205221Sensitivity Variation from RT over Temp.%/C0.01 (xy)0.04 (z)Offset Ratiometric Error (Vdd = 3.3V 5%)%0.3Sensitivity Ratiometric Error (Vdd = 3.3V 5%)%1.1 (xy)0.6 (z)Self Test Output change on Activationg1.11.5 (xy)1.90.030.5 (z)1.1Mechanical Re

8、sonance (-3dB)2Hz4000 (xy)2000 (z)Non-Linearity% of FS0.1Cross Axis Sensitivity%2Noise Density (on filter pins)g / Hz750Notes:1. User selectable from CTRL_REGC2. Resonance as defined by the dampened mechanical sensor.36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080

9、fax:607-257-1146310-1547-1007221647 - Page 2 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010Table 2. Electrical(specifications are for operation at 3.3V and T = 25C unless stated otherwise)ParametersUnitsMinTypicalMaxSupply Volta

10、ge (Vdd)OperatingVI/O Pads Supply Voltage (VIO)V1.7VddOperating (full power)120220320Current ConsumptionMotion Wake UpA407515Hz ModeStandby0.1Output Low Voltage1V-0.3 * VioOutput High VoltageV0.9 * Vio-Input Low VoltageV-0.2 * VioInput High VoltageV0.8 * Vio-Input Pull-down CurrentA0LPF (-3

11、dB) = 50Hz15.9Power Up Time2LPF (-3dB) = 100Hz8.0LPF (-3dB) = 500Hzms1.6LPF (-3dB) = 1,000Hz0.8LPF (-3dB) = 2,000Hz0.4A/D Conversion times200SPI Communication Rate3MHz1I2C Communication RateKHz400Bandwidth (-3dB)4Hz405060Notes:1. Assuming I2C communication and minimum 1.5Kohm pull-up resistor on SCL

12、 and SDA.2. Power up time is determined after the enabling of the part and is determined by the low-pass filter (LPF) set in CTRL_REGC.3. SPI Communication Rate can be optimized for faster communication per the SPI timing diagram below.4. Factory programmable to have a switched capacitor low pass fi

13、lter at 2kHz, 1kHz, 500Hz, 100Hz, 50Hz or no low pass filter. Optionally, the user can define with in CTRL_REGC. Maximum defined by the frequency response of the sensors.36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:607-257-1146310-1547-1007221647www.kionix.c

14、om - Page 3 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010KXSD9 SPI Timing Diagramt1t2t3 t4t5t6 t7nCSSCLKSDIbit 7bit 6bit 1bit 0bit 7bit 6bit 1bit 0SDObit 7bit 6bit 1bit 0t8t9t11t10Table 3. SPI TimingNumberDescriptionMINMAXUnits-Enable transi

15、tion from low to high after Vdd above 1.6V1mst1nCS low to first SCLK setup time130-nst2SCLK pulse width: high (Does not apply to the last bit of a byte.)130-nst3SCLK pulse width: low (Does not apply to the last bit of a byte.)130-nst4SCLK pulse width: high (Only on last bit of a byte.)200-nst5SCLK p

16、ulse width: low (Only on last bit of a byte.)350-nst6nCS low after the final SCLK falling edge350-nst7nCS pulse width: high130-nst8SDI valid to SCLK rising edge10-nst9SCLK rising edge to SDI invalid100-nst10SCLK falling edge to SDO valid-130nst11SCLK falling edge to SDO invalid0-nsNotesRecommended S

17、PI SCLK1-usA/D conversion SCLK hold (t5)200-us36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:607-257-1146310-1547-1007221647 - Page 4 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010Table 4.

18、 EnvironmentalParametersUnitsMinTypicalMaxSupply Voltage (Vdd)Absolute LimitsV-0.3-6.0Operating Temperature RangeC-40-85Storage Temperature RangeC-55-150Mech. Shock (powered and unpowered)g-5000 for 0.5ms10000 for 0.2msESDHBMV-2000Caution: ESD Sensitive and Mechanical Shock Sensitive Component, impr

19、oper handling can cause permanent damage to the device.This product conforms to Directive 2002/95/EC of the European Parliament and of the Council of the European Union (RoHS). Specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or

20、 polybrominated diphenyl ethers (PBDE) above the maximum concentration values (MCV) by weight in any of its homogenous materials. Homogenous materials are ofuniform composition throughout.This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this HF product contain a m

21、aximum total halogen content of 1500 ppm with less than 900-ppmbromine and less than 900-ppm chlorine.SolderingSoldering recommendations are available upon request or from .36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:607-257-1146310-1547-10072

22、21647 - Page 5 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010Application SchematicSDA/SDO109SCL/SCLKIO Vdd128ADDR/SDIAUX INKXSD9MOT3746CS5C1VddTable 5. KXSD9 Pin DescriptionsPinNameDescription1IO VddThe power supply input for th

23、e digital communication bus2DNCReserved Do Not Connect3AUX INAuxiliary Input for analog/digital conversion4GNDGround5VddThe power supply input. Decouple this pin to ground with a 0.1uF ceramic capacitor.6nCSSPI EnableI2C/SPI mode selection (1 = I2C mode, 0 = SPI mode)7MOTMotion Wakeup Interrupt8ADDR

24、/SDII2C programmable address bit/SPI Serial Data Input9SCL/SCLKI2C Serial Clock/SPI Serial Clock10SDA/SD0I2C Serial Data/SPI Serial Data Output36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:607-257-1146310-1547-1007221647 - Page 6 o

25、f 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010Test Specifications! Special Characteristics:These characteristics have been identified as being critical to the customer. Every part is tested to verify its conformance to specification prior to shipment.Table

26、6. Test SpecificationsParameterSpecificationTest ConditionsZero-g Offset RT2048 +/- 205 counts25C, Vdd = 3.3 VSensitivity RT819+/- 25 counts/g25C, Vdd = 3.3 VCurrent Consumption - Operating120= Idd = 320 uA25C, Vdd = 3.3 V36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-

27、1080 fax:607-257-1146310-1547-1007221647 - Page 7 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010Package Dimensions and Orientation3 x 3 x 0.9 mm LGAAll dimensions and tolerances conform to ASME Y14.5M-199436 Thornwood Dr. Ithaca

28、, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:607-257-1146310-1547-1007221647 - Page 8 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010OrientationPin 1 +Y+X+ZWhen device is accelerated in +X, +Y or +Z direction,

29、the corresponding output will increase.Static X/Y/Z Output Response versus Orientation to Earths surface (1-g):FS1=1, FS0=1 ( 2g)Position123456DiagramTopBottomBottomTopX204828672048122920482048countscountscountscountscountscountsY286720481229204820482048countscountscountscountscountscountsZ204820482

30、048204828671229countscountscountscountscountscountsX-Polarity0+0-00Y-Polarity+0-000Z-Polarity0000+-(1-g)Earths Surface36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:607-257-1146310-1547-1007221647 - Page 9 of 25 2g Tri-axis Digital

31、Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010KXSD9 Digital InterfacesThe Kionix KXSD9 digital accelerometer has the ability to communicate on both I2C and SPI digital serial interface busses. This flexibility allows for easy system integration by eliminating analog-to-digital conv

32、erter requirements and by providing direct communication with system micro-controllers. In doing so, all of the digital communication pins have shared responsibilities.The serial interface terms and descriptions as indicated in Table 7 below will be observed throughout this document.TermDescriptionT

33、ransmitterThe device that transmits data to the bus.ReceiverThe device that receives data from the bus.MasterThe device that initiates a transfer, generates clock signals and terminates a transfer.SlaveThe device addressed by the Master.Table 7. Serial Interface TerminologiesI2C Serial InterfaceThe

34、KXSD9 has the ability to communicate on an I2C bus. I2C is primarily used for synchronous serial communication between a Master device and one or more Slave devices. The Master, typically a micro controller, provides the serial clock signal and addresses Slave devices on the bus. The KXSD9 always op

35、erates as a Slave device during standard Master-Slave I2C operation as shown in Figure 1 on the following page.I2C is a two-wire serial interface that contains a Serial Clock (SCL) line and a Serial Data (SDA) line. SCL is a serial clock that is provided by the Master, but can be held low by any Sla

36、ve device, putting the Master into a wait condition. SDA is a bi-directional line used to transmit and receive data to and from the interface. Data is transmitted MSB (Most Significant Bit) first in 8-bit per byte format, and the number of bytes transmitted per transfer is unlimited. The I2C bus is

37、considered free when both lines are high.36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:607-257-1146310-1547-1007221647 - Page 10 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010SDA SCLVddSD

38、AMCUSCLSDAKXSD9SCLADDRSDAKXSD9SCLADDRFigure 1 Multiple KXSD9 I2C ConnectionI2C OperationTransactions on the I2C bus begin after the Master transmits a start condition (S), which is defined as a high-to-low transition on the data line while the SCL line is held high. The bus is considered busy after

39、this condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in the seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be receiving data 1 from the Slave or transmitting data 0 to the Slave. When a Sla

40、ve Address is sent, each device on the bus compares the seven MSBs with its internally-stored address. If they match, the device considers itself addressed by the Master. The KXSD9s Slave Address is comprised of a programmable part and a fixed part, which allows for connection of multiple KXSD9s to

41、the same I2C bus. The Slave Address associated with the KXSD9 is 001100X, where the programmable bit, X, is determined by the assignment of ADDR (pin 8) to GND or Vdd. Figure 1 above shows how two KXSD9s would be implemented on an I2C bus.It is mandatory that receiving devices acknowledge (ACK) each

42、 transaction. Therefore, the transmitter must release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or Slave, is obliged to generate a

43、n ACK after each byte of data has been received. To conclude a transaction, the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high. The I2C bus is now free.36 Thornwood Dr. Ithaca, NY 14850 2009 Kionix All Rights Reservedtel: 607-257-1080 fax:6

44、07-257-1146310-1547-1007221647 - Page 11 of 25 2g Tri-axis Digital Accelerometer SpecificationsPART NUMBER:KXSD9-2050Rev. 3Jul-2010Writing to a KXSD9 8-bit RegisterUpon power up, the Master must write to the KXSD9s control registers to set its operational mode. Therefore,

45、 when writing to a control register on the I2C bus, as shown Sequence 1 on the following page, the following protocol must be observed: After a start condition, SAD+W transmission, and the KXSD9 ACK has been returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command

46、is telling the KXSD9 to which 8-bit register the Master will be writing the data. Since this is I2C mode, the MSB of the RA command should always be zero (0). The KXSD9 acknowledges the RA and the Master transmits the data to be stored in the 8-bit register. The KXSD9 acknowledges that it has receiv

47、ed the data and the Master transmits a stop condition (P) to end the data transfer. The data sent to the KXSD9 is now stored in the appropriate register. The KXSD9 automatically increments the received RA commands and, therefore, multiple bytes of data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on the following page.Reading from a KXSD9 8-bit RegisterWhen reading data from a KXSD9 8-bit register on the I2C bus, as shown in Sequence 3 on the next page, the following protocol must be observed: The Master first transmits a start c