基于AT89C51單片機(jī)中英文文獻(xiàn)翻譯

1、AT89C51的概況1 AT89C51 應(yīng)用單片機(jī)廣泛應(yīng)用于商業(yè)：諸如調(diào)制解調(diào)器，電動(dòng)機(jī)控制系統(tǒng)，空調(diào)控制系統(tǒng), 汽車發(fā)動(dòng)機(jī)和其他一些領(lǐng)域。這些單片機(jī)的禹速處理速度和增強(qiáng)烈外圍設(shè)備集合 使得它們適合于這種高速爭(zhēng)件應(yīng)用場(chǎng)合。然而，這些關(guān)鍵應(yīng)用領(lǐng)域也要求這些單 片機(jī)高度可靠。健壯的測(cè)試環(huán)境和用于驗(yàn)證這些無(wú)論在元部件層次還是系統(tǒng)級(jí)別 的單片機(jī)的介適的丁具環(huán)境保證了高可靠性和低幣場(chǎng)風(fēng)險(xiǎn)。Intel平臺(tái)丁程部門 開(kāi)發(fā)了一種血向?qū)ο蟮挠糜隍?yàn)證它的AT89C51汽年單片機(jī)多線性測(cè)試壞境。這種 壞境的冃標(biāo)不僅是為AT89C51汽車單片機(jī)提供一種健壯測(cè)試壞境，而且開(kāi)發(fā)一種 能夠容易擴(kuò)展并重復(fù)用來(lái)騙證其他兒種將來(lái)

2、的單片機(jī)。開(kāi)發(fā)的這種壞境連接了 AT89C5U本文討論了這種測(cè)試環(huán)境的設(shè)計(jì)和原理，它的和備種硬件、軟件壞境 部件的交互性，以及如何使用AT89C51o1. 1介紹8位AT89C51 CI1M0S工藝單片機(jī)被設(shè)計(jì)用于處理高速計(jì)算和快速輸入/輸 出。HCS51單片機(jī)典型的應(yīng)用是高速事件控制系統(tǒng)。商業(yè)應(yīng)用包括調(diào)制解調(diào)器， 電動(dòng)機(jī)控制系統(tǒng)，打印機(jī)，影印機(jī)，空調(diào)控制系統(tǒng)，碗盤驅(qū)動(dòng)器和醫(yī)療設(shè)備。汽 乍T.業(yè)把ICS51單片機(jī)用于發(fā)動(dòng)機(jī)控制系統(tǒng)，懸掛系統(tǒng)和反鎖制動(dòng)系統(tǒng)。AT89C51 尤其很好適用于得益于它的處理速度和增強(qiáng)烈片上外圍功能集，諸如：汽車動(dòng)力 控制，車輛動(dòng)態(tài)懸掛，反鎖制動(dòng)和穩(wěn)定性控制應(yīng)川。山于這

3、些決定性應(yīng)用，市場(chǎng) 盂要一種對(duì)靠的具有低干擾潛伏響應(yīng)的費(fèi)用-效能控制器，服務(wù)大量時(shí)間和審件 驅(qū)動(dòng)的在實(shí)時(shí)應(yīng)用需要的集成外閑的能力，只有在總程序包中高出平均處理功 率的中央處理器。擁有操作不可預(yù)測(cè)的設(shè)備的經(jīng)濟(jì)和法律風(fēng)險(xiǎn)是很高的。一H進(jìn) 入市場(chǎng)，尤其任務(wù)決定性應(yīng)川諸如動(dòng)駕駛儀或反鎖制動(dòng)系統(tǒng)，錯(cuò)誤將是財(cái)力上 所禁止的。重新設(shè)計(jì)的費(fèi)用對(duì)以高達(dá)500K美元，如果產(chǎn)品族庁有同樣內(nèi)核或外 圍設(shè)計(jì)缺陷的話，費(fèi)用會(huì)更高。另外，部件的替代品領(lǐng)域是極苴昂貴的，因?yàn)樵O(shè) 備要用來(lái)把模塊典型地焊接成一個(gè)總體的價(jià)值比各個(gè)部件髙幾倍。為了緩和這些 問(wèn)題，在最壞的環(huán)境和電壓條件下對(duì)這牝單片機(jī)進(jìn)彳亍牙論在部件級(jí)別還是系統(tǒng)級(jí) 別上

4、的綜合測(cè)試是必需的。Intel Chandler平臺(tái)T.程組提供了備種單片機(jī)和處 理器的系統(tǒng)驗(yàn)證。這種系統(tǒng)的驗(yàn)證處理可以被分解為三個(gè)主要部分。系統(tǒng)的類烈 和應(yīng)用需求決定了能夠在設(shè)備上執(zhí)行的測(cè)試類型。1.2 AT89C51提供以下標(biāo)準(zhǔn)功能：4k字節(jié)FLASH閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM, 32個(gè)I/O 口線，2個(gè)16位 定時(shí)/計(jì)數(shù)器，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器 及時(shí)鐘電路。同時(shí)，AT89C51降至OHz的靜態(tài)邏輯操作，并支持兩種可選的節(jié)電 丁作模式?？臻e方式體制CPU的丁作,但允許RAM,定時(shí)/計(jì)數(shù)器,串行通信口及 中斷系統(tǒng)繼續(xù)T作。掉電方式保存RAI中的內(nèi)容，

5、但振蕩器體制工作并禁止其他 所有不見(jiàn)丁作直到下一個(gè)碾件復(fù)位。DMMG MO COHTWXmsTRucno* REG6TEBPORT 1LATCH圖1-2-1 AT89C51方框圖1.3引腳功能說(shuō)明Vcc：電源電壓GND：地P0 n： P0 口繪一組8位漏極開(kāi)路犁雙向I/O 口，也即地址/數(shù)據(jù)總線復(fù) 丿IJ。作為輸出丨I川時(shí)，毎位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端II 弓“1”町作為高阻抗輸入端用。在訪問(wèn)外部數(shù)據(jù)“儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組 TWP2REQ6TERACCOFT 0 EWERSSCK POSTERTMF1PORT 2 DRIVERSLISTER 仙UTCM2PUSH口線分

6、時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問(wèn)期間激活內(nèi)部上拉電阻。 在Flash編程時(shí)，P0 口接受指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn) 時(shí)，要求外接上拉電阻。P1 口： P1是一個(gè)帶內(nèi)部上拉電阻的8位雙向I/O 口，P1的輸出緩沖級(jí) 可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過(guò)內(nèi)部的 上拉電阻把端口拉到高電平,此時(shí)可作輸入口。作為輸入口使用時(shí)，因?yàn)閮?nèi)部存 在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL） o Flash編程 和程序校驗(yàn)期間，P1接受低8位地址。 P2 口: P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O 口, P2的輸出緩沖 級(jí)可驅(qū)動(dòng)（吸收

7、或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫1”，通過(guò)內(nèi)部 的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作為輸入口使用時(shí)，I大I為內(nèi)部 存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。在訪問(wèn)外 部程序存儲(chǔ)器或16位四肢的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX DPTR指令）時(shí)， P2 口送出高8位地址數(shù)據(jù)，在訪問(wèn)8位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX RI指令）時(shí)，P2 口線上的內(nèi)容（也即特殊功能寄存器（SFR）區(qū)中R2寄存器的 內(nèi)容），在整個(gè)訪問(wèn)期間不改變。Flash編程和程序校驗(yàn)時(shí)，P2也接收高位地 址和其他控制信號(hào)。P3 II： P3是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I/O I

8、I, P3的輸出緩沖 級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過(guò)內(nèi)部 的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作為輸入口使用時(shí)，I対為內(nèi)部 存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（UL） o P3 口還接 收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí),RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電 平將使單片機(jī)復(fù)位。ALE/PROG： *|訪問(wèn)外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE （地址鎖存允許） 輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問(wèn)外部存儲(chǔ)器，ALE仍以時(shí)鐘振 蕩頻率的1/6輸出尚定的正脈沖信號(hào)，因此它可對(duì)外

9、輸出時(shí)鐘或川于定時(shí)I I的。 要注意的是，每半訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過(guò)一個(gè)ALE脈沖。對(duì)Flash存儲(chǔ)器 編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必耍，可通過(guò)對(duì)特殊功能 寄存器（SFR）區(qū)中的8EH單元DO位置位,可禁止ALE操作。該位置位后,只有 一條MOVX和IOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí) 行外部程序時(shí)，應(yīng)設(shè)置ALE無(wú)效。 PSEN：程序存儲(chǔ)允許輸出是外部程序存儲(chǔ)器的讀選通型號(hào)，嚴(yán)I89C51由外 部存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，毎個(gè)機(jī)器周期兩次PSE有效，即輸出兩個(gè)脈沖。 在此期間，汨訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器，這兩次有效的PSEN信號(hào)不出現(xiàn)。EA/V

10、PP：外部訪問(wèn)允許。欲使CPU僅訪問(wèn)外部程序存儲(chǔ)器（地址為OOOOHFFFFH） , EA端必須保持低電平（接地）。需注意的是：如果加密 位LB1被編程,復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平（接Vcc端）， CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令-Flash存儲(chǔ)器編程時(shí)，該引腳加上+12v的 編程允許電源Vpp, M|然這必須是該器件使用12v編WjtllkVppoXTAL1：振蕩器反相放人器及內(nèi)部時(shí)鐘發(fā)生器的輸入端。XTAL2：振蕩黠反相放大器的輸出端。89C51中有一個(gè)川于構(gòu)成內(nèi)部振蕩 器的高增益反相放大器，引腳XTAL1和XTAL2分別是該放大器的輸入端和輸出端。 這個(gè)放大器與作為反

11、饋元件的片外石英品體或陶瓷諧振器一起構(gòu)成IH激振蕩器， 振蕩電路參見(jiàn)圖5。外接右英晶體或陶瓷諧振器及電容Cl、C2接在放人器的反饋 冋路中構(gòu)成并聯(lián)振蕩電路。對(duì)電容Cl、C2雖沒(méi)有十分嚴(yán)格的要求，但電容容量 的大小會(huì)輕微影響振蕩頻率的高低、振蕩器T作的穩(wěn)足性、起振的難易程度及溫 度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30Pf土10 Pf,而如使用陶瓷 諧振器建議選擇40Pf10Pf。用戶也可以采用外部時(shí)鐘。這種情況下,外部時(shí)鐘 脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端XTAL2則懸空。掉電模式：在掉電模式下，振蕩器停止匸作，進(jìn)入掉電模式的指令是授后一條被執(zhí)行的 指令，片內(nèi)RAM和特殊

12、功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。推出掉電模 式的唯一方法是峽件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM 中的內(nèi)容，在Vcc恢復(fù)到正常T作電平前，復(fù)位應(yīng)無(wú)效，且必須保持運(yùn)時(shí)間以 使振蕩器巫啟動(dòng)并穩(wěn)定丁作o89C51的程序存儲(chǔ)器陣列是采川字節(jié)再入方式編程 的，每次寫入個(gè)字符，要對(duì)整個(gè)芯片的EPR0U程序存儲(chǔ)器寫入 個(gè)非空字節(jié)， 必須使用片擦除的方法將整個(gè)存儲(chǔ)器的內(nèi)容清楚。2編用方法編程前，設(shè)盤好地址、數(shù)據(jù)及控制信號(hào)，編程單元的地址加在P1 口和P2 口見(jiàn)表6, PSEN保持低電平,ALE、EA和RST保持高電平。校驗(yàn)時(shí)，P0 口必須接的P2.0P2. 3（11位地址范圉為00

13、00HOFFFH）,數(shù)據(jù)從P0口輸入,引腳P2. 6、 P2.7和P3.6、P3. 7的電平設(shè)置見(jiàn)表6, PSEB為低電平，RST保持高電平,EA/Vpp 引腳是編程電源的輸入端，按耍求加上編程電斥,ALE/PROG引腳輸入編程脈沖（負(fù) 脈沖）。編程時(shí),可采用420MHz的時(shí)鐘振蕩器,89C51編程方法如下:在地 址線上加上要編程單元的地址信號(hào)在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。激活相應(yīng) 的控制信號(hào)。在高電壓編程方式時(shí)，將EA/Vpp端加上+12v編程電壓。毎對(duì)Flash 心儲(chǔ)陣列寫入一個(gè)字節(jié)或毎塢入一個(gè)程序加密位，加上個(gè)ALE/PROG編程脈沖。 改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)15步驟，知

14、道全部文件編程結(jié)束“ 每個(gè)字節(jié)寫入周期是自身定時(shí)的，通常約為1.5ms。數(shù)據(jù)査詢89C51單片機(jī)用 數(shù)據(jù)查詢方式來(lái)檢測(cè)一個(gè)寫周期是否結(jié)束，在一個(gè)寫周期中，如需要讀取放后寫 入的那個(gè)字節(jié)，則讀岀的數(shù)據(jù)的最高位（P0. 7）是原來(lái)寫入字節(jié)的垠高位的反碼。 寫周期開(kāi)始后，可在任意時(shí)刻進(jìn)行數(shù)據(jù)査詢。2.IReady/Busy:字節(jié)編程的進(jìn)度町通過(guò)Ready/Busy輸出信號(hào)檢測(cè)，編程期間，ALE變?yōu)榍?電平“H”后P3.4 （Ready/Busy）端被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編 程完成后，P3.4變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀態(tài)。程序校驗(yàn)：如果加密位LB、LB2沒(méi)有進(jìn)行編程，則代碼數(shù)據(jù)對(duì)通過(guò)地址和

15、 數(shù)抓線讀冋原編寫的數(shù)拯，采用卜圖的電路，用序存儲(chǔ)器的地址由P1 口和P2 口 的P2.0P2. 3輸入，數(shù)據(jù)由P0 口讀出,P206、P2.7和P3. 6、P3. 7的控制信號(hào)上10k左右的上拉電阻。RGM圖2-2-2校驗(yàn)電路圖2-1-1編程電路22芯片擦除:利用控制信號(hào)的正確組合（表6）并保持ALE/PR03引腳10ms的低電平脈沖寬 度即可將EPROM陣列（4k字節(jié)）和三個(gè)加密位整片擦除，代碼陣列在片擦除操作 中將任何非空單元寫入” 1”，這步驟需在編程之前進(jìn)行。2. 3讀片內(nèi)簽名寧節(jié)：89C51單片機(jī)內(nèi)有3個(gè)簽名字節(jié),地址為030H. 031H和032H。于聲明該器件 的廠商、號(hào)和編程

16、電壓。讀簽名字節(jié)的過(guò)程和單元030H、03111和032H的正常校 驗(yàn)相仿，只需要將P3.6和P3.7保持低電平，返回值童義如下：（03011） = 1EH聲明產(chǎn)品由ATMEL公司制造。（031H） = 51H聲明為89C51單片機(jī)。（03211） = FFH聲明為12V編程電壓。（03211） = 0511聲明為5編程電壓。2.4編程接口：采川控制信號(hào)的正確組合可對(duì)Flash閃速存儲(chǔ)陣列中的每一代碼字節(jié)進(jìn)行 寫入和心儲(chǔ)器的整片擦除，嗎操作周期是自身定時(shí)的，初始化后它將自動(dòng)定時(shí)到 操作窕成。微機(jī)接口實(shí)現(xiàn)兩種信息形式的交換。在il算機(jī)之外，由電子系統(tǒng)所處 理的信息以一種物理信號(hào)形式存在，但在程序

17、中，它是用數(shù)字表示的。任-接口 的功能都可分為以某種形式進(jìn)行數(shù)據(jù)庫(kù)變換的一些操作，所以外部和內(nèi)部形式的 轉(zhuǎn)換是山許多步驟完成的。模擬-數(shù)字轉(zhuǎn)換器（ADC）川來(lái)將連續(xù)變化信號(hào)變成相 應(yīng)的數(shù)字雖，這數(shù)字雖町是可能性的二進(jìn)制數(shù)值中的一固定值。如果傳感器輸出 不是連續(xù)變化的，就不需模擬-數(shù)字轉(zhuǎn)換。這種情況下，信號(hào)調(diào)理單元必須將輸 入信號(hào)變換成為另一信號(hào)，也可直接與接I I的下-部分，即微計(jì)算機(jī)木身的輸入 輸出何L；相連接。輸出接口采用和似的形式，明顯的差別在于信息流的方向相反: 是從程序到外部世界。這種情況下，程序可稱為輸出程序，它監(jiān)督接口的操作并 完成數(shù)字-模擬轉(zhuǎn)換器（DAC）所需數(shù)字的標(biāo)定。該子程

18、序依次送出信息給輸出器 件，產(chǎn)牛相應(yīng)的電信號(hào)，HlDAC轉(zhuǎn)換成模擬形式。繪后信號(hào)經(jīng)調(diào)理（通常是放 大）以形成適應(yīng)丁執(zhí)行器操作的形式。在微機(jī)電路5吏川的信號(hào)兒乎總是太小而 不能被口接地連到“外部世界”，因而必須用某種形式將其轉(zhuǎn)換成更適宜的形式。 接口電路部分的設(shè)計(jì)是使用微機(jī)的丁程師所面臨放重要的任務(wù)Z。我們已經(jīng)了 解到微機(jī)屮，信號(hào)以離散的位形式表示。半微機(jī)要與只有打開(kāi)或關(guān)閉操作的設(shè)備 相連時(shí)，這種數(shù)字形式是垠有用的，這里每一位都可表示一開(kāi)關(guān)或執(zhí)行器的狀態(tài)。 為了解決實(shí)際問(wèn)題，一個(gè)單片機(jī)不僅包括CPU,程序和數(shù)據(jù)存儲(chǔ)器，另外，它必 須含有通過(guò)CPU訪問(wèn)外部信息的更件。一 H.CPU收集到數(shù)據(jù)信息和

19、流程，它必須 能夠改變外部領(lǐng)域的i部分，這些硬件設(shè)備稱作外圍設(shè)備，它們是CPU通往外部 的窗口單片機(jī)可利用外閑設(shè)備中最基木的用于一般用途的I/O接口，每個(gè)I/O接口 既可作為輸入端乂可作為輸岀端，每個(gè)I/O接口的功能取決與程序初始化階段對(duì) 數(shù)據(jù)方位寄存器相應(yīng)位進(jìn)行宜一和清零操作，通過(guò)CPU指令對(duì)數(shù)據(jù)寄存器和應(yīng)位 進(jìn)行置一和淸冬來(lái)置一和清冬輸出端口，同樣輸入端口邏輯位也可以通過(guò)CPU指 令訪問(wèn)。一些類烈的吊行口單元允許CPU與外部設(shè)備進(jìn)行串口通信，用吊口位代 替平行位進(jìn)行通信需要少許的I/O 口，這樣使通信費(fèi)用降低但速度也相對(duì)慢些。 $U傳送町以同步也可以界步。The General Situa

20、tion of AT89C51Chapter I The application of AT89C51Microcontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems, automotive engine and among others. The high processing speed and enhanced peripheral set of these microcontr

21、ollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable The high reliability and low market risks can be ensured by a robust testing process and a proper tools environment for the

22、 validation of these microcontrollers both at the component and at the system level. Intel Plaform Engineering department developed an object-oriented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers The goals of thisenvironment was not only to provide a

23、robust testing environment for the AT89C51 automotive microcontrollers, but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers. The environment was developed in conjunction with Microsoft Foundation Classes (AT89C51). The pap

24、er describes the design and mechanism of this test environment, its interactions with various hardware/software environmental components, and how to use AT89C51.1.1 IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speedcalculations and fast input/oulput operations. MC

25、S 51 microcontrollers are typically used for high-speed event control systems. Commercial applications include modems,motor-control systems, printers, photocopiers, air conditioner control systems, disk drives,and medical instruments The automotive industry use MCS 51 microcontrollers in engine-cont

26、rol systems, airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control, vehicle dynamic suspension, antilock braki

27、ng, and stability control applications Because of these critical applications, the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CP

28、U with above average processing power in a single package The financial and legal risk of having devices that operate unpredictably is very high Once in the market, particularly in mission criticalapplications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Red

29、esign costs can run as high as a $500K, much more if the fix means 2 back annotating it across a product family that share the same core and/or peripheral design flaw In addition, field replacements of components is extremely expensive, as the devices are typically sealed in modules with a total val

30、ue several times that of the component. To mitigate these problems, it is essential that comprehensive testing of the con (rollers be carried out at both the component level and system level under worst case environmental and voltage conditions.This complete and thorough validation necessitates not

31、only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully.Intel Chandler Platform Engineering group provides post silicon system validation (SV) of various micro-controllers and processors The system validation process can be broken into t

32、hree major parts.The type of the device and its application requirements determine which types of testing arc performed on the device1.2 The AT89C51 provides the following standard features:4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt

33、architecture full duple ser -ial port, on-chip oscillator and clock circuitryn addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM. timer/counters,serial p

34、ort and interrupt sys -tem to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.AJO COMTRXIHSTRUCnOM REGISTERr廠MUfPSWJPORT 1 ixrcMPCT 1 Cfl 陡 PSPOT S 0WRS啦GAM COE55 RE3STERFigure 1-2-1 Block

35、Diagraml-3Pin DescriptionVCC Supply voltage.GND GroundPort 0： Port 0 is an 8-bit open-drain bidirectional I/O port. As an output port, each pin cansink eight TTL inputs. When Is are written to port 0 pins, the pins can be used as high impedance inputs. Port 0 may also be configured to be the multipl

36、exed loworder address/data busduring accesses to external program and data memory In this mode PO has inlernalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the codebyles during program veri flcatio n. External pull ups are required during programveriflcation.QND :

37、PC.Tmo P27” 瞬郃理!r* rp BlFFRIM：REMEMTIRCB：OHRe*Port 1: Port I is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/so -urcc four TTL inputs.Whcn Is are written to Port 1 pins they are pulled high by the internul pullups and can be used as inputs As inputs, Port

38、 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and veriflcation.Port 2： Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 outpuibuffers can sink

39、/source four TTL inputs.When Is are written to Port 2 pins they arepulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups Port 2 emits the high-order address byte during fetc

40、hes from external program memory and during accesses to Port 2 pins that arc externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-ordcr address byte during fetches from external program memory and during accesses to external data memory that use

41、 16-bit addresses (MOVXDPTR). In this application, it uses strong internal pull-ups when emitting Is. During accesses to external data memory that use 8-bit addresses (MOVX Rl), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the highrder address bits and some cont

42、rol signals durin Flash programming and verification.Port 3： Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 outpuibuffers can sink/sou -rce four TTL inputs.When Is are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs As inputs

43、,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups Port 3 also serves the functions of various special featuresof the AT89C51 as listed below:RST： Reset input. A high on this pin for two machine cycles while the oscillator is running resets the deviceA

44、LE/PROG： Address Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.In nomial operation ALE is emitted at a constant rate of 1/6 the oscillator frequency,and may be used for ext

45、ernal timing or clocking purposes Nolc， however, that one ALEpulse is skipped duri ng each access to external DataMemory.If desired, ALE operationcan be disabled hy setting bit 0 of SFR location 8EH. With the bit set, ALE is active onlyduring a MOVX or MOVC instruction. Otherwise, the pin is weakly

46、pulled high. Settingthe ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN： Program Store Enable is the read strobe to external program memory. When theAT89C51 is executing code from external program memory, PSEN is activated twiceeach machine cycle, except that

47、two PSEN activations are skipped during each access toexternal data niemory.EA/VPP： External Access Enable. EA must be strapped to GND in order to enable the deviceto fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA w

48、ill be internally latched onreset.EA should be strapped to VCC for internal program executions This pin alsreceives the 12-volt programming enable voltage (VPP) during Flash programming, forparts that require 12-volt VPP.XTAL1: Input to the inverting oscillator amplifier and input to the internal cl

49、ock operatingcircuil.XTAL2 : Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL 1 and XTAL2 are the input and output, respectively, of an inverting amplifierwhich can be configured for use as an on-chip oscillator, as shown in Figure I. Either aquartz crystal or ceramic re

50、sonator may be used To drive the device from an extemalclock source, XTAL2 should be left unconnected while XTALI is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two fli

51、p-flop, but minimum and maximum voltage high and low time specifications must be observed Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active The mode is invoked by software The content of the on-chip RAM and all the special functions registers remain

52、unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset

53、 algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not b

54、e one that writes to a port pin or to external memory.Power-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the power-down mode is tennina

55、ted. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal openHing level and must be held active long enough to allow the oscillator to restart and stabilize.The AT89C51

56、 code memory array is programmed byte-bybyte in either programming mode To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode2 Programming AlgorithmBefore programming the AT89C51, the address, ciala and control signals should be set up a

57、ccording to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps. I. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines 3. Activate the correct combination of control signals. 4. Raise EA

58、/VPP to 12V for the high-voltage programming mode 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of

59、 the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data arc valid

60、on all outputs, and the next cycle may begin. Data Polling may begin any lime after a write cycle has been initiated2Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pul