實(shí)驗(yàn)五存儲(chǔ)器設(shè)計(jì)

1、計(jì)算機(jī)組成原理實(shí)驗(yàn)五存儲(chǔ)器設(shè)計(jì)實(shí)驗(yàn)報(bào)告姓名：吳速碘 黃紫微 學(xué)號(hào)：13052 班級(jí)：計(jì)算機(jī)二班日期2015、5、25實(shí)驗(yàn)五 存儲(chǔ)器設(shè)計(jì)一、 實(shí)驗(yàn)?zāi)康?、 掌握RAM和ROM的Verilog語(yǔ)言描述方法；2、 學(xué)習(xí)用宏模塊的方法定制RAM和ROM。二、 實(shí)驗(yàn)任務(wù)1、設(shè)計(jì)并實(shí)現(xiàn)一個(gè)128*16 的單端口的RAM；2、設(shè)計(jì)并實(shí)現(xiàn)一個(gè)128*16的ROM；3、設(shè)計(jì)并實(shí)現(xiàn)一個(gè)雙端口的128*16的RAM4、設(shè)計(jì)并實(shí)現(xiàn)一個(gè)16*32的FIFO。5、設(shè)計(jì)并實(shí)現(xiàn)正弦信號(hào)發(fā)生器，見(jiàn)“正弦信號(hào)發(fā)生器實(shí)驗(yàn)指南”。三、 實(shí)驗(yàn)步驟1 編寫(xiě)Verilog代碼（見(jiàn)附頁(yè)）2功能仿真進(jìn)行分析與綜合，排除語(yǔ)法上的錯(cuò)誤建立波形仿真

2、文件，輸入激勵(lì)生成功能仿真網(wǎng)表進(jìn)行功能仿真，觀察輸出結(jié)果3選擇器件DE2_70開(kāi)發(fā)板的使用者請(qǐng)選擇EP2C70F896C64綁定管腳5 下載驗(yàn)證DE2_70開(kāi)發(fā)板的下載:使用USB-Blaster進(jìn)行下載四、實(shí)驗(yàn)內(nèi)容五、實(shí)驗(yàn)思考題1、分析存儲(chǔ)器采用三態(tài)輸出的原因是什么？存儲(chǔ)器的輸出端是連接在數(shù)據(jù)總線上的。數(shù)據(jù)總線相當(dāng)于一條車流頻繁的大馬路，必須在綠燈條件下，車輛才能進(jìn)入這條大馬路，否則要撞車發(fā)生交通事故。同理， 存儲(chǔ)器中的數(shù)據(jù)是不能隨意傳送到數(shù)據(jù)總線上的。例如，若數(shù)據(jù)總線上的數(shù)據(jù)是“1”(高電平5V)，存儲(chǔ)器中的數(shù)據(jù)是“0”(低電平0V)，兩種數(shù)據(jù)若碰到 一起就會(huì)發(fā)生短路而損壞單片機(jī)。因此，存

3、儲(chǔ)器輸出端口不僅能呈現(xiàn)“l(fā)”和“0”兩種狀態(tài)，還應(yīng)具有第三種狀態(tài)“高阻"態(tài)。呈“高阻"態(tài)時(shí)，輸出端口相當(dāng)于 斷開(kāi)，對(duì)數(shù)據(jù)總線不起作用，此時(shí)數(shù)據(jù)總線可被其他器件占用。當(dāng)其他器件呈“高阻”態(tài)時(shí)，存儲(chǔ)器在片選允許和輸出允許的條件下，才能將自己的數(shù)據(jù)輸出到數(shù)據(jù) 總線上。2、單端口和雙端口的區(qū)別是什么？單端口ram是ram的讀寫(xiě)只有一個(gè)端口，同時(shí)只能讀或者只能寫(xiě)。雙端口ram是ram讀端口和寫(xiě)端口分開(kāi)，一個(gè)端口能讀，另一個(gè)端口可以同時(shí)寫(xiě)。3、什么情況下考慮采用雙端口存儲(chǔ)器？（1）為了使CPU不致因?yàn)榈却鎯?chǔ)器讀寫(xiě)操作的完成而無(wú)事可做,可以采取一些加速CPU和存儲(chǔ)器之間有效傳輸?shù)奶厥獯?/p>

4、施:l 采用更高速的主存儲(chǔ)器，或加長(zhǎng)存儲(chǔ)器的字長(zhǎng)；l 采用并行操作的雙端口存儲(chǔ)器；l 在CPU和主存儲(chǔ)器之間插入一個(gè)高速緩沖存儲(chǔ)器（Cache），以縮短讀出時(shí)間；l 在每個(gè)存儲(chǔ)器周期中存取幾個(gè)字(采用交叉存儲(chǔ)器)（2） 雙端口存儲(chǔ)器是指同一個(gè)存儲(chǔ)器具有兩組相互獨(dú)立的讀寫(xiě)控制線路,由于進(jìn)行并行的獨(dú)立操作，是一種高速工作的存儲(chǔ)器。（3）l 當(dāng)兩個(gè)端口的地址不相同時(shí)，在兩個(gè)端口上進(jìn)行讀寫(xiě)操作，一定不會(huì)發(fā)生沖突。當(dāng)任一端口被選中驅(qū)動(dòng)時(shí)，就可對(duì)整個(gè)存儲(chǔ)器進(jìn)行存取，每一個(gè)端口都有自己的片選控制和輸出驅(qū)動(dòng)控制。l 當(dāng)兩個(gè)端口同時(shí)存取存儲(chǔ)器同一存儲(chǔ)單元時(shí)，便發(fā)生讀寫(xiě)沖突。為解決此問(wèn)題，特設(shè)置了BUSY標(biāo)志。由

5、片上的判斷邏輯決定對(duì)哪個(gè)端口優(yōu)先進(jìn)行讀寫(xiě)操作，而暫時(shí)關(guān)閉另一個(gè)被延遲的端口。l 總之，當(dāng)兩個(gè)端口均為開(kāi)放狀態(tài)（BUSY為高電平）且存取地址相同時(shí)，發(fā)生讀寫(xiě)沖突此時(shí)判斷邏輯可以使地址匹配或片使能匹配下降至5ns，并決定對(duì)哪個(gè)端口進(jìn)行存取4、FIFO的工作特點(diǎn)是什么？為什么常用于實(shí)現(xiàn)程序中的子程序調(diào)用、遞歸等？特點(diǎn)：FIFO存儲(chǔ)器是系統(tǒng)的緩沖環(huán)節(jié)，如果沒(méi)有FIFO存儲(chǔ)器，整個(gè)系統(tǒng)就不可能正常工作，它主要有幾方面的功能：1）對(duì)連續(xù)的數(shù)據(jù)流進(jìn)行緩存，防止在進(jìn)機(jī)和存儲(chǔ)操作時(shí)丟失數(shù)據(jù)；2）數(shù)據(jù)集中起來(lái)進(jìn)行進(jìn)機(jī)和存儲(chǔ)，可避免頻繁的總線操作，減輕CPU的負(fù)擔(dān)；3）允許系統(tǒng)進(jìn)行DMA操作，提高數(shù)據(jù)的傳輸速度。這

6、是至關(guān)重要的一點(diǎn)，如果不采用DMA操作，數(shù)據(jù)傳輸將達(dá)不到傳輸要求，而且大大增加CPU的負(fù)擔(dān)，無(wú)法同時(shí)完成數(shù)據(jù)的存儲(chǔ)工作。因此，選擇合適的存儲(chǔ)芯片對(duì)于提高系統(tǒng)性能很重要，在以往的設(shè)計(jì)中經(jīng)常采用的是“乒乓型”存儲(chǔ)方式，這種方式就是采用兩片存儲(chǔ)器， 數(shù)據(jù)首先進(jìn)入其中一片，當(dāng)數(shù)據(jù)滿時(shí)再讓數(shù)據(jù)進(jìn)入第二片存儲(chǔ)器，同時(shí)通過(guò)邏輯控制，將第一片存儲(chǔ)器中的數(shù)據(jù)取走，以此類推，兩片輪流對(duì)數(shù)據(jù)進(jìn)行緩存。這種方 式有著較明顯的缺點(diǎn)，首先是控制復(fù)雜，要有專門(mén)的邏輯來(lái)維護(hù)這種輪流機(jī)制;其次，數(shù)據(jù)流的流向要不斷變化，限制了數(shù)據(jù)流的速率，還容易產(chǎn)生干擾。從數(shù)據(jù)傳 輸上說(shuō)，緩存芯片容量越大，對(duì)后續(xù)時(shí)序要求就越低，可減少總線操作的

7、頻次；但從數(shù)據(jù)存儲(chǔ)上說(shuō)，就意味著需要開(kāi)辟更大的內(nèi)存空間來(lái)進(jìn)行進(jìn)行緩沖，會(huì)增加計(jì)算機(jī)的內(nèi)存開(kāi)銷，而且容量越大，成本也越高。因此，在綜合考慮系統(tǒng)性能和成本的基礎(chǔ)上，選擇滿足系統(tǒng)需要的芯片即可。在FIFO存儲(chǔ)器而不是地址總線上附加了表示內(nèi)部緩沖器狀態(tài)（Buffer Full，緩沖器已滿；Buffer Empty，緩沖器為空）的狀態(tài)引腳，連接于FIFO的雙方利用該狀態(tài)進(jìn)行操作的控制。另外，還設(shè)計(jì)了在接通電源及復(fù)位（Reset）或由于操作中的某些異常等原因而重新初始化（無(wú)數(shù)據(jù)狀態(tài)）FIFO的復(fù)位引腳，這可以說(shuō)是FIFO存儲(chǔ)器的特點(diǎn)。20 / 20文檔可自由編輯打印Verilog代碼sinwaveVmod

8、ule sinwaveV#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)(input clk, output reg (DATA_WIDTH-1):0 q);reg (ADDR_WIDTH-1):0 Q1;wire newclk;reg 4:0 clk_cnt;assign newclk=clk_cnt4;always (posedge CLK)beginclk_cnt<=clk_cnt+1;endalways (posedge newclk)begin Q1<=Q1+1;endlpm_rom0lpm_rom0_inst (.add

9、ress ( Q1),.clock ( CLK ),.q ( DOUT );endmoduletest1/ synopsys translate_offtimescale 1 ps / 1 ps/ synopsys translate_onmodule test1 (address,clock,data,wren,q);input6:0 address;input clock;input15:0 data;input wren;output15:0 q;ifndef ALTERA_RESERVED_QIS/ synopsys translate_offendiftri1 clock;ifnde

10、f ALTERA_RESERVED_QIS/ synopsys translate_onendifwire 15:0 sub_wire0;wire 15:0 q = sub_wire015:0;altsyncramaltsyncram_component (.address_a (address),.clock0 (clock),.data_a (data),.wren_a (wren),.q_a (sub_wire0),.aclr0 (1'b0),.aclr1 (1'b0),.address_b (1'b1),.addressstall_a (1'b0),.a

11、ddressstall_b (1'b0),.byteena_a (1'b1),.byteena_b (1'b1),.clock1 (1'b1),.clocken0 (1'b1),.clocken1 (1'b1),.clocken2 (1'b1),.clocken3 (1'b1),.data_b (1'b1),.eccstatus (),.q_b (),.rden_a (1'b1),.rden_b (1'b1),.wren_b (1'b0);defparamaltsyncram_component.c

12、lock_enable_input_a = "BYPASS",altsyncram_component.clock_enable_output_a = "BYPASS",altsyncram_ended_device_family = "Cyclone IV GX",altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",altsyncram_component.lpm_type = "altsyncram",al

13、tsyncram_component.numwords_a = 128,altsyncram_component.operation_mode = "SINGLE_PORT",altsyncram_component.outdata_aclr_a = "NONE",altsyncram_component.outdata_reg_a = "CLOCK0",altsyncram_component.power_up_uninitialized = "FALSE",altsyncram_component.read_d

14、uring_write_mode_port_a = "NEW_DATA_NO_NBE_READ",altsyncram_component.widthad_a = 7,altsyncram_component.width_a = 16,altsyncram_component.width_byteena_a = 1;endmoduletest2/ synopsys translate_offtimescale 1 ps / 1 ps/ synopsys translate_onmodule test2 (address,clock,q);input6:0 address;i

15、nput clock;output15:0 q;ifndef ALTERA_RESERVED_QIS/ synopsys translate_offendiftri1 clock;ifndef ALTERA_RESERVED_QIS/ synopsys translate_onendifwire 15:0 sub_wire0;wire 15:0 q = sub_wire015:0;altsyncramaltsyncram_component (.address_a (address),.clock0 (clock),.q_a (sub_wire0),.aclr0 (1'b0),.acl

16、r1 (1'b0),.address_b (1'b1),.addressstall_a (1'b0),.addressstall_b (1'b0),.byteena_a (1'b1),.byteena_b (1'b1),.clock1 (1'b1),.clocken0 (1'b1),.clocken1 (1'b1),.clocken2 (1'b1),.clocken3 (1'b1),.data_a (161'b1),.data_b (1'b1),.eccstatus (),.q_b (),.

17、rden_a (1'b1),.rden_b (1'b1),.wren_a (1'b0),.wren_b (1'b0);defparamaltsyncram_component.address_aclr_a = "NONE",altsyncram_component.clock_enable_input_a = "BYPASS",altsyncram_component.clock_enable_output_a = "BYPASS",altsyncram_component.init_file = &q

18、uot;vv_CPU.mif",altsyncram_ended_device_family = "Cyclone IV GX",altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",altsyncram_component.lpm_type = "altsyncram",altsyncram_component.numwords_a = 128,altsyncram_component.operation_mode = "ROM&

19、quot;,altsyncram_component.outdata_aclr_a = "NONE",altsyncram_component.outdata_reg_a = "CLOCK0",altsyncram_component.widthad_a = 7,altsyncram_component.width_a = 16,altsyncram_component.width_byteena_a = 1;endmoduletest3/ synopsys translate_offtimescale 1 ps / 1 ps/ synopsys tra

20、nslate_onmodule test3 (clock,data,rdaddress,wraddress,wren,q);input clock;input15:0 data;input6:0 rdaddress;input6:0 wraddress;input wren;output15:0 q;ifndef ALTERA_RESERVED_QIS/ synopsys translate_offendiftri1 clock;tri0 wren;ifndef ALTERA_RESERVED_QIS/ synopsys translate_onendifwire 15:0 sub_wire0

21、;wire 15:0 q = sub_wire015:0;altsyncramaltsyncram_component (.address_a (wraddress),.clock0 (clock),.data_a (data),.wren_a (wren),.address_b (rdaddress),.q_b (sub_wire0),.aclr0 (1'b0),.aclr1 (1'b0),.addressstall_a (1'b0),.addressstall_b (1'b0),.byteena_a (1'b1),.byteena_b (1'

22、b1),.clock1 (1'b1),.clocken0 (1'b1),.clocken1 (1'b1),.clocken2 (1'b1),.clocken3 (1'b1),.data_b (161'b1),.eccstatus (),.q_a (),.rden_a (1'b1),.rden_b (1'b1),.wren_b (1'b0);defparamaltsyncram_component.address_aclr_b = "NONE",altsyncram_component.address_r

23、eg_b = "CLOCK0",altsyncram_component.clock_enable_input_a = "BYPASS",altsyncram_component.clock_enable_input_b = "BYPASS",altsyncram_component.clock_enable_output_b = "BYPASS",altsyncram_ended_device_family = "Cyclone IV GX",altsyncram_c

24、omponent.lpm_type = "altsyncram",altsyncram_component.numwords_a = 128,altsyncram_component.numwords_b = 128,altsyncram_component.operation_mode = "DUAL_PORT",altsyncram_component.outdata_aclr_b = "NONE",altsyncram_component.outdata_reg_b = "CLOCK0",altsyncram

25、_component.power_up_uninitialized = "FALSE",altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",altsyncram_component.widthad_a = 7,altsyncram_component.widthad_b = 7,altsyncram_component.width_a = 16,altsyncram_component.width_b = 16,altsyncram_component.width_byteena_a = 1;endmoduletest4/ synopsys translate_offtimescale 1 ps / 1 ps/ synopsys translate_onmodule test4 (clock,data,rdreq,wrreq,empty,full,q,usedw);input clock;input15:0 data;input rdreq;input wrreq;output empty;output full;output15:0 q;output4:0 usedw;